1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/module.h>
31#include <linux/firmware.h>
32
33#include "aic94xx.h"
34#include "aic94xx_reg.h"
35#include "aic94xx_hwi.h"
36#include "aic94xx_seq.h"
37#include "aic94xx_dump.h"
38
39u32 MBAR0_SWB_SIZE;
40
41
42
43static int asd_get_user_sas_addr(struct asd_ha_struct *asd_ha)
44{
45
46 if (asd_ha->hw_prof.sas_addr[0])
47 return 0;
48
49 return sas_request_addr(asd_ha->sas_ha.core.shost,
50 asd_ha->hw_prof.sas_addr);
51}
52
53static void asd_propagate_sas_addr(struct asd_ha_struct *asd_ha)
54{
55 int i;
56
57 for (i = 0; i < ASD_MAX_PHYS; i++) {
58 if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0)
59 continue;
60
61
62 ASD_DPRINTK("setting phy%d addr to %llx\n", i,
63 SAS_ADDR(asd_ha->hw_prof.sas_addr));
64 memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr,
65 asd_ha->hw_prof.sas_addr, SAS_ADDR_SIZE);
66 }
67}
68
69
70
71static void asd_init_phy_identify(struct asd_phy *phy)
72{
73 phy->identify_frame = phy->id_frm_tok->vaddr;
74
75 memset(phy->identify_frame, 0, sizeof(*phy->identify_frame));
76
77 phy->identify_frame->dev_type = SAS_END_DEVICE;
78 if (phy->sas_phy.role & PHY_ROLE_INITIATOR)
79 phy->identify_frame->initiator_bits = phy->sas_phy.iproto;
80 if (phy->sas_phy.role & PHY_ROLE_TARGET)
81 phy->identify_frame->target_bits = phy->sas_phy.tproto;
82 memcpy(phy->identify_frame->sas_addr, phy->phy_desc->sas_addr,
83 SAS_ADDR_SIZE);
84 phy->identify_frame->phy_id = phy->sas_phy.id;
85}
86
87static int asd_init_phy(struct asd_phy *phy)
88{
89 struct asd_ha_struct *asd_ha = phy->sas_phy.ha->lldd_ha;
90 struct asd_sas_phy *sas_phy = &phy->sas_phy;
91
92 sas_phy->enabled = 1;
93 sas_phy->class = SAS;
94 sas_phy->iproto = SAS_PROTOCOL_ALL;
95 sas_phy->tproto = 0;
96 sas_phy->type = PHY_TYPE_PHYSICAL;
97 sas_phy->role = PHY_ROLE_INITIATOR;
98 sas_phy->oob_mode = OOB_NOT_CONNECTED;
99 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
100
101 phy->id_frm_tok = asd_alloc_coherent(asd_ha,
102 sizeof(*phy->identify_frame),
103 GFP_KERNEL);
104 if (!phy->id_frm_tok) {
105 asd_printk("no mem for IDENTIFY for phy%d\n", sas_phy->id);
106 return -ENOMEM;
107 } else
108 asd_init_phy_identify(phy);
109
110 memset(phy->frame_rcvd, 0, sizeof(phy->frame_rcvd));
111
112 return 0;
113}
114
115static void asd_init_ports(struct asd_ha_struct *asd_ha)
116{
117 int i;
118
119 spin_lock_init(&asd_ha->asd_ports_lock);
120 for (i = 0; i < ASD_MAX_PHYS; i++) {
121 struct asd_port *asd_port = &asd_ha->asd_ports[i];
122
123 memset(asd_port->sas_addr, 0, SAS_ADDR_SIZE);
124 memset(asd_port->attached_sas_addr, 0, SAS_ADDR_SIZE);
125 asd_port->phy_mask = 0;
126 asd_port->num_phys = 0;
127 }
128}
129
130static int asd_init_phys(struct asd_ha_struct *asd_ha)
131{
132 u8 i;
133 u8 phy_mask = asd_ha->hw_prof.enabled_phys;
134
135 for (i = 0; i < ASD_MAX_PHYS; i++) {
136 struct asd_phy *phy = &asd_ha->phys[i];
137
138 phy->phy_desc = &asd_ha->hw_prof.phy_desc[i];
139 phy->asd_port = NULL;
140
141 phy->sas_phy.enabled = 0;
142 phy->sas_phy.id = i;
143 phy->sas_phy.sas_addr = &phy->phy_desc->sas_addr[0];
144 phy->sas_phy.frame_rcvd = &phy->frame_rcvd[0];
145 phy->sas_phy.ha = &asd_ha->sas_ha;
146 phy->sas_phy.lldd_phy = phy;
147 }
148
149
150 for_each_phy(phy_mask, phy_mask, i) {
151 int err = asd_init_phy(&asd_ha->phys[i]);
152 if (err)
153 return err;
154 }
155
156 return 0;
157}
158
159
160
161static int asd_init_sw(struct asd_ha_struct *asd_ha)
162{
163 struct pci_dev *pcidev = asd_ha->pcidev;
164 int err;
165 u32 v;
166
167
168 err = pci_read_config_dword(pcidev, PCI_CONF_MBAR_KEY, &v);
169 if (err) {
170 asd_printk("couldn't access conf. space of %s\n",
171 pci_name(pcidev));
172 goto Err;
173 }
174 if (v)
175 err = pci_write_config_dword(pcidev, PCI_CONF_MBAR_KEY, v);
176 if (err) {
177 asd_printk("couldn't write to MBAR_KEY of %s\n",
178 pci_name(pcidev));
179 goto Err;
180 }
181
182
183
184
185 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR);
186 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWB,
187 REG_BASE_ADDR_CSEQCIO);
188 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWC, REG_BASE_ADDR_EXSI);
189 asd_ha->io_handle[0].swa_base = REG_BASE_ADDR;
190 asd_ha->io_handle[0].swb_base = REG_BASE_ADDR_CSEQCIO;
191 asd_ha->io_handle[0].swc_base = REG_BASE_ADDR_EXSI;
192 MBAR0_SWB_SIZE = asd_ha->io_handle[0].len - 0x80;
193 if (!asd_ha->iospace) {
194
195 pci_write_config_dword(pcidev, PCI_CONF_MBAR1, OCM_BASE_ADDR);
196 asd_ha->io_handle[1].swa_base = OCM_BASE_ADDR;
197 }
198 spin_lock_init(&asd_ha->iolock);
199Err:
200 return err;
201}
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216static int asd_init_scbs(struct asd_ha_struct *asd_ha)
217{
218 struct asd_seq_data *seq = &asd_ha->seq;
219 int bitmap_bytes;
220
221
222 asd_ha->seq.tc_index_bitmap_bits = asd_ha->hw_prof.max_scbs;
223 asd_ha->seq.tc_index_array = kzalloc(asd_ha->seq.tc_index_bitmap_bits*
224 sizeof(void *), GFP_KERNEL);
225 if (!asd_ha->seq.tc_index_array)
226 return -ENOMEM;
227
228 bitmap_bytes = (asd_ha->seq.tc_index_bitmap_bits+7)/8;
229 bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
230 asd_ha->seq.tc_index_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
231 if (!asd_ha->seq.tc_index_bitmap) {
232 kfree(asd_ha->seq.tc_index_array);
233 asd_ha->seq.tc_index_array = NULL;
234 return -ENOMEM;
235 }
236
237 spin_lock_init(&seq->tc_index_lock);
238
239 seq->next_scb.size = sizeof(struct scb);
240 seq->next_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool, GFP_KERNEL,
241 &seq->next_scb.dma_handle);
242 if (!seq->next_scb.vaddr) {
243 kfree(asd_ha->seq.tc_index_bitmap);
244 kfree(asd_ha->seq.tc_index_array);
245 asd_ha->seq.tc_index_bitmap = NULL;
246 asd_ha->seq.tc_index_array = NULL;
247 return -ENOMEM;
248 }
249
250 seq->pending = 0;
251 spin_lock_init(&seq->pend_q_lock);
252 INIT_LIST_HEAD(&seq->pend_q);
253
254 return 0;
255}
256
257static void asd_get_max_scb_ddb(struct asd_ha_struct *asd_ha)
258{
259 asd_ha->hw_prof.max_scbs = asd_get_cmdctx_size(asd_ha)/ASD_SCB_SIZE;
260 asd_ha->hw_prof.max_ddbs = asd_get_devctx_size(asd_ha)/ASD_DDB_SIZE;
261 ASD_DPRINTK("max_scbs:%d, max_ddbs:%d\n",
262 asd_ha->hw_prof.max_scbs,
263 asd_ha->hw_prof.max_ddbs);
264}
265
266
267
268static void asd_dl_tasklet_handler(unsigned long);
269
270static int asd_init_dl(struct asd_ha_struct *asd_ha)
271{
272 asd_ha->seq.actual_dl
273 = asd_alloc_coherent(asd_ha,
274 ASD_DL_SIZE * sizeof(struct done_list_struct),
275 GFP_KERNEL);
276 if (!asd_ha->seq.actual_dl)
277 return -ENOMEM;
278 asd_ha->seq.dl = asd_ha->seq.actual_dl->vaddr;
279 asd_ha->seq.dl_toggle = ASD_DEF_DL_TOGGLE;
280 asd_ha->seq.dl_next = 0;
281 tasklet_init(&asd_ha->seq.dl_tasklet, asd_dl_tasklet_handler,
282 (unsigned long) asd_ha);
283
284 return 0;
285}
286
287
288
289static int asd_alloc_edbs(struct asd_ha_struct *asd_ha, gfp_t gfp_flags)
290{
291 struct asd_seq_data *seq = &asd_ha->seq;
292 int i;
293
294 seq->edb_arr = kmalloc(seq->num_edbs*sizeof(*seq->edb_arr), gfp_flags);
295 if (!seq->edb_arr)
296 return -ENOMEM;
297
298 for (i = 0; i < seq->num_edbs; i++) {
299 seq->edb_arr[i] = asd_alloc_coherent(asd_ha, ASD_EDB_SIZE,
300 gfp_flags);
301 if (!seq->edb_arr[i])
302 goto Err_unroll;
303 memset(seq->edb_arr[i]->vaddr, 0, ASD_EDB_SIZE);
304 }
305
306 ASD_DPRINTK("num_edbs:%d\n", seq->num_edbs);
307
308 return 0;
309
310Err_unroll:
311 for (i-- ; i >= 0; i--)
312 asd_free_coherent(asd_ha, seq->edb_arr[i]);
313 kfree(seq->edb_arr);
314 seq->edb_arr = NULL;
315
316 return -ENOMEM;
317}
318
319static int asd_alloc_escbs(struct asd_ha_struct *asd_ha,
320 gfp_t gfp_flags)
321{
322 struct asd_seq_data *seq = &asd_ha->seq;
323 struct asd_ascb *escb;
324 int i, escbs;
325
326 seq->escb_arr = kmalloc(seq->num_escbs*sizeof(*seq->escb_arr),
327 gfp_flags);
328 if (!seq->escb_arr)
329 return -ENOMEM;
330
331 escbs = seq->num_escbs;
332 escb = asd_ascb_alloc_list(asd_ha, &escbs, gfp_flags);
333 if (!escb) {
334 asd_printk("couldn't allocate list of escbs\n");
335 goto Err;
336 }
337 seq->num_escbs -= escbs;
338 ASD_DPRINTK("num_escbs:%d\n", seq->num_escbs);
339
340 for (i = 0; i < seq->num_escbs; i++, escb = list_entry(escb->list.next,
341 struct asd_ascb,
342 list)) {
343 seq->escb_arr[i] = escb;
344 escb->scb->header.opcode = EMPTY_SCB;
345 }
346
347 return 0;
348Err:
349 kfree(seq->escb_arr);
350 seq->escb_arr = NULL;
351 return -ENOMEM;
352
353}
354
355static void asd_assign_edbs2escbs(struct asd_ha_struct *asd_ha)
356{
357 struct asd_seq_data *seq = &asd_ha->seq;
358 int i, k, z = 0;
359
360 for (i = 0; i < seq->num_escbs; i++) {
361 struct asd_ascb *ascb = seq->escb_arr[i];
362 struct empty_scb *escb = &ascb->scb->escb;
363
364 ascb->edb_index = z;
365
366 escb->num_valid = ASD_EDBS_PER_SCB;
367
368 for (k = 0; k < ASD_EDBS_PER_SCB; k++) {
369 struct sg_el *eb = &escb->eb[k];
370 struct asd_dma_tok *edb = seq->edb_arr[z++];
371
372 memset(eb, 0, sizeof(*eb));
373 eb->bus_addr = cpu_to_le64(((u64) edb->dma_handle));
374 eb->size = cpu_to_le32(((u32) edb->size));
375 }
376 }
377}
378
379
380
381
382
383
384
385
386static int asd_init_escbs(struct asd_ha_struct *asd_ha)
387{
388 struct asd_seq_data *seq = &asd_ha->seq;
389 int err = 0;
390
391
392 int edbs = 2*(1+asd_ha->hw_prof.num_phys);
393
394 seq->num_escbs = (edbs+ASD_EDBS_PER_SCB-1)/ASD_EDBS_PER_SCB;
395 seq->num_edbs = seq->num_escbs * ASD_EDBS_PER_SCB;
396
397 err = asd_alloc_edbs(asd_ha, GFP_KERNEL);
398 if (err) {
399 asd_printk("couldn't allocate edbs\n");
400 return err;
401 }
402
403 err = asd_alloc_escbs(asd_ha, GFP_KERNEL);
404 if (err) {
405 asd_printk("couldn't allocate escbs\n");
406 return err;
407 }
408
409 asd_assign_edbs2escbs(asd_ha);
410
411
412
413
414
415 seq->pending = seq->num_escbs;
416 seq->can_queue = 1 + (asd_ha->hw_prof.max_scbs - seq->pending)/2;
417
418 return 0;
419}
420
421
422
423
424
425
426
427
428
429
430int asd_chip_hardrst(struct asd_ha_struct *asd_ha)
431{
432 int i;
433 int count = 100;
434 u32 reg;
435
436 for (i = 0 ; i < 4 ; i++) {
437 asd_write_reg_dword(asd_ha, COMBIST, HARDRST);
438 }
439
440 do {
441 udelay(1);
442 reg = asd_read_reg_dword(asd_ha, CHIMINT);
443 if (reg & HARDRSTDET) {
444 asd_write_reg_dword(asd_ha, CHIMINT,
445 HARDRSTDET|PORRSTDET);
446 return 0;
447 }
448 } while (--count > 0);
449
450 return -ENODEV;
451}
452
453
454
455
456
457
458
459
460
461static int asd_init_chip(struct asd_ha_struct *asd_ha)
462{
463 int err;
464
465 err = asd_chip_hardrst(asd_ha);
466 if (err) {
467 asd_printk("couldn't hard reset %s\n",
468 pci_name(asd_ha->pcidev));
469 goto out;
470 }
471
472 asd_disable_ints(asd_ha);
473
474 err = asd_init_seqs(asd_ha);
475 if (err) {
476 asd_printk("couldn't init seqs for %s\n",
477 pci_name(asd_ha->pcidev));
478 goto out;
479 }
480
481 err = asd_start_seqs(asd_ha);
482 if (err) {
483 asd_printk("couldn't start seqs for %s\n",
484 pci_name(asd_ha->pcidev));
485 goto out;
486 }
487out:
488 return err;
489}
490
491#define MAX_DEVS ((OCM_MAX_SIZE) / (ASD_DDB_SIZE))
492
493static int max_devs = 0;
494module_param_named(max_devs, max_devs, int, S_IRUGO);
495MODULE_PARM_DESC(max_devs, "\n"
496 "\tMaximum number of SAS devices to support (not LUs).\n"
497 "\tDefault: 2176, Maximum: 65663.\n");
498
499static int max_cmnds = 0;
500module_param_named(max_cmnds, max_cmnds, int, S_IRUGO);
501MODULE_PARM_DESC(max_cmnds, "\n"
502 "\tMaximum number of commands queuable.\n"
503 "\tDefault: 512, Maximum: 66047.\n");
504
505static void asd_extend_devctx_ocm(struct asd_ha_struct *asd_ha)
506{
507 unsigned long dma_addr = OCM_BASE_ADDR;
508 u32 d;
509
510 dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
511 asd_write_reg_addr(asd_ha, DEVCTXBASE, (dma_addr_t) dma_addr);
512 d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
513 d |= 4;
514 asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
515 asd_ha->hw_prof.max_ddbs += MAX_DEVS;
516}
517
518static int asd_extend_devctx(struct asd_ha_struct *asd_ha)
519{
520 dma_addr_t dma_handle;
521 unsigned long dma_addr;
522 u32 d;
523 int size;
524
525 asd_extend_devctx_ocm(asd_ha);
526
527 asd_ha->hw_prof.ddb_ext = NULL;
528 if (max_devs <= asd_ha->hw_prof.max_ddbs || max_devs > 0xFFFF) {
529 max_devs = asd_ha->hw_prof.max_ddbs;
530 return 0;
531 }
532
533 size = (max_devs - asd_ha->hw_prof.max_ddbs + 1) * ASD_DDB_SIZE;
534
535 asd_ha->hw_prof.ddb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
536 if (!asd_ha->hw_prof.ddb_ext) {
537 asd_printk("couldn't allocate memory for %d devices\n",
538 max_devs);
539 max_devs = asd_ha->hw_prof.max_ddbs;
540 return -ENOMEM;
541 }
542 dma_handle = asd_ha->hw_prof.ddb_ext->dma_handle;
543 dma_addr = ALIGN((unsigned long) dma_handle, ASD_DDB_SIZE);
544 dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
545 dma_handle = (dma_addr_t) dma_addr;
546 asd_write_reg_addr(asd_ha, DEVCTXBASE, dma_handle);
547 d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
548 d &= ~4;
549 asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
550
551 asd_ha->hw_prof.max_ddbs = max_devs;
552
553 return 0;
554}
555
556static int asd_extend_cmdctx(struct asd_ha_struct *asd_ha)
557{
558 dma_addr_t dma_handle;
559 unsigned long dma_addr;
560 u32 d;
561 int size;
562
563 asd_ha->hw_prof.scb_ext = NULL;
564 if (max_cmnds <= asd_ha->hw_prof.max_scbs || max_cmnds > 0xFFFF) {
565 max_cmnds = asd_ha->hw_prof.max_scbs;
566 return 0;
567 }
568
569 size = (max_cmnds - asd_ha->hw_prof.max_scbs + 1) * ASD_SCB_SIZE;
570
571 asd_ha->hw_prof.scb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
572 if (!asd_ha->hw_prof.scb_ext) {
573 asd_printk("couldn't allocate memory for %d commands\n",
574 max_cmnds);
575 max_cmnds = asd_ha->hw_prof.max_scbs;
576 return -ENOMEM;
577 }
578 dma_handle = asd_ha->hw_prof.scb_ext->dma_handle;
579 dma_addr = ALIGN((unsigned long) dma_handle, ASD_SCB_SIZE);
580 dma_addr -= asd_ha->hw_prof.max_scbs * ASD_SCB_SIZE;
581 dma_handle = (dma_addr_t) dma_addr;
582 asd_write_reg_addr(asd_ha, CMDCTXBASE, dma_handle);
583 d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
584 d &= ~1;
585 asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
586
587 asd_ha->hw_prof.max_scbs = max_cmnds;
588
589 return 0;
590}
591
592
593
594
595
596
597
598
599
600
601
602
603
604static int asd_init_ctxmem(struct asd_ha_struct *asd_ha)
605{
606 int bitmap_bytes;
607
608 asd_get_max_scb_ddb(asd_ha);
609 asd_extend_devctx(asd_ha);
610 asd_extend_cmdctx(asd_ha);
611
612
613 bitmap_bytes = (asd_ha->hw_prof.max_ddbs+7)/8;
614 bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
615 asd_ha->hw_prof.ddb_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
616 if (!asd_ha->hw_prof.ddb_bitmap)
617 return -ENOMEM;
618 spin_lock_init(&asd_ha->hw_prof.ddb_lock);
619
620 return 0;
621}
622
623int asd_init_hw(struct asd_ha_struct *asd_ha)
624{
625 int err;
626 u32 v;
627
628 err = asd_init_sw(asd_ha);
629 if (err)
630 return err;
631
632 err = pci_read_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, &v);
633 if (err) {
634 asd_printk("couldn't read PCIC_HSTPCIX_CNTRL of %s\n",
635 pci_name(asd_ha->pcidev));
636 return err;
637 }
638 err = pci_write_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL,
639 v | SC_TMR_DIS);
640 if (err) {
641 asd_printk("couldn't disable split completion timer of %s\n",
642 pci_name(asd_ha->pcidev));
643 return err;
644 }
645
646 err = asd_read_ocm(asd_ha);
647 if (err) {
648 asd_printk("couldn't read ocm(%d)\n", err);
649
650
651 }
652
653 err = asd_read_flash(asd_ha);
654 if (err) {
655 asd_printk("couldn't read flash(%d)\n", err);
656
657
658
659 }
660
661 asd_init_ctxmem(asd_ha);
662
663 if (asd_get_user_sas_addr(asd_ha)) {
664 asd_printk("No SAS Address provided for %s\n",
665 pci_name(asd_ha->pcidev));
666 err = -ENODEV;
667 goto Out;
668 }
669
670 asd_propagate_sas_addr(asd_ha);
671
672 err = asd_init_phys(asd_ha);
673 if (err) {
674 asd_printk("couldn't initialize phys for %s\n",
675 pci_name(asd_ha->pcidev));
676 goto Out;
677 }
678
679 asd_init_ports(asd_ha);
680
681 err = asd_init_scbs(asd_ha);
682 if (err) {
683 asd_printk("couldn't initialize scbs for %s\n",
684 pci_name(asd_ha->pcidev));
685 goto Out;
686 }
687
688 err = asd_init_dl(asd_ha);
689 if (err) {
690 asd_printk("couldn't initialize the done list:%d\n",
691 err);
692 goto Out;
693 }
694
695 err = asd_init_escbs(asd_ha);
696 if (err) {
697 asd_printk("couldn't initialize escbs\n");
698 goto Out;
699 }
700
701 err = asd_init_chip(asd_ha);
702 if (err) {
703 asd_printk("couldn't init the chip\n");
704 goto Out;
705 }
706Out:
707 return err;
708}
709
710
711
712
713
714
715
716
717
718
719
720
721
722static void asd_chip_reset(struct asd_ha_struct *asd_ha)
723{
724 ASD_DPRINTK("chip reset for %s\n", pci_name(asd_ha->pcidev));
725 asd_chip_hardrst(asd_ha);
726}
727
728
729
730static void asd_dl_tasklet_handler(unsigned long data)
731{
732 struct asd_ha_struct *asd_ha = (struct asd_ha_struct *) data;
733 struct asd_seq_data *seq = &asd_ha->seq;
734 unsigned long flags;
735
736 while (1) {
737 struct done_list_struct *dl = &seq->dl[seq->dl_next];
738 struct asd_ascb *ascb;
739
740 if ((dl->toggle & DL_TOGGLE_MASK) != seq->dl_toggle)
741 break;
742
743
744 spin_lock_irqsave(&seq->tc_index_lock, flags);
745 ascb = asd_tc_index_find(seq, (int)le16_to_cpu(dl->index));
746 spin_unlock_irqrestore(&seq->tc_index_lock, flags);
747 if (unlikely(!ascb)) {
748 ASD_DPRINTK("BUG:sequencer:dl:no ascb?!\n");
749 goto next_1;
750 } else if (ascb->scb->header.opcode == EMPTY_SCB) {
751 goto out;
752 } else if (!ascb->uldd_timer && !del_timer(&ascb->timer)) {
753 goto next_1;
754 }
755 spin_lock_irqsave(&seq->pend_q_lock, flags);
756 list_del_init(&ascb->list);
757 seq->pending--;
758 spin_unlock_irqrestore(&seq->pend_q_lock, flags);
759 out:
760 ascb->tasklet_complete(ascb, dl);
761
762 next_1:
763 seq->dl_next = (seq->dl_next + 1) & (ASD_DL_SIZE-1);
764 if (!seq->dl_next)
765 seq->dl_toggle ^= DL_TOGGLE_MASK;
766 }
767}
768
769
770
771
772
773
774
775static void asd_process_donelist_isr(struct asd_ha_struct *asd_ha)
776{
777 tasklet_schedule(&asd_ha->seq.dl_tasklet);
778}
779
780
781
782
783
784static void asd_com_sas_isr(struct asd_ha_struct *asd_ha)
785{
786 u32 comstat = asd_read_reg_dword(asd_ha, COMSTAT);
787
788
789 asd_write_reg_dword(asd_ha, COMSTAT, 0xFFFFFFFF);
790
791 if (comstat & CSBUFPERR) {
792 asd_printk("%s: command/status buffer dma parity error\n",
793 pci_name(asd_ha->pcidev));
794 } else if (comstat & CSERR) {
795 int i;
796 u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
797 dmaerr &= 0xFF;
798 asd_printk("%s: command/status dma error, DMAERR: 0x%02x, "
799 "CSDMAADR: 0x%04x, CSDMAADR+4: 0x%04x\n",
800 pci_name(asd_ha->pcidev),
801 dmaerr,
802 asd_read_reg_dword(asd_ha, CSDMAADR),
803 asd_read_reg_dword(asd_ha, CSDMAADR+4));
804 asd_printk("CSBUFFER:\n");
805 for (i = 0; i < 8; i++) {
806 asd_printk("%08x %08x %08x %08x\n",
807 asd_read_reg_dword(asd_ha, CSBUFFER),
808 asd_read_reg_dword(asd_ha, CSBUFFER+4),
809 asd_read_reg_dword(asd_ha, CSBUFFER+8),
810 asd_read_reg_dword(asd_ha, CSBUFFER+12));
811 }
812 asd_dump_seq_state(asd_ha, 0);
813 } else if (comstat & OVLYERR) {
814 u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
815 dmaerr = (dmaerr >> 8) & 0xFF;
816 asd_printk("%s: overlay dma error:0x%x\n",
817 pci_name(asd_ha->pcidev),
818 dmaerr);
819 }
820 asd_chip_reset(asd_ha);
821}
822
823static void asd_arp2_err(struct asd_ha_struct *asd_ha, u32 dchstatus)
824{
825 static const char *halt_code[256] = {
826 "UNEXPECTED_INTERRUPT0",
827 "UNEXPECTED_INTERRUPT1",
828 "UNEXPECTED_INTERRUPT2",
829 "UNEXPECTED_INTERRUPT3",
830 "UNEXPECTED_INTERRUPT4",
831 "UNEXPECTED_INTERRUPT5",
832 "UNEXPECTED_INTERRUPT6",
833 "UNEXPECTED_INTERRUPT7",
834 "UNEXPECTED_INTERRUPT8",
835 "UNEXPECTED_INTERRUPT9",
836 "UNEXPECTED_INTERRUPT10",
837 [11 ... 19] = "unknown[11,19]",
838 "NO_FREE_SCB_AVAILABLE",
839 "INVALID_SCB_OPCODE",
840 "INVALID_MBX_OPCODE",
841 "INVALID_ATA_STATE",
842 "ATA_QUEUE_FULL",
843 "ATA_TAG_TABLE_FAULT",
844 "ATA_TAG_MASK_FAULT",
845 "BAD_LINK_QUEUE_STATE",
846 "DMA2CHIM_QUEUE_ERROR",
847 "EMPTY_SCB_LIST_FULL",
848 "unknown[30]",
849 "IN_USE_SCB_ON_FREE_LIST",
850 "BAD_OPEN_WAIT_STATE",
851 "INVALID_STP_AFFILIATION",
852 "unknown[34]",
853 "EXEC_QUEUE_ERROR",
854 "TOO_MANY_EMPTIES_NEEDED",
855 "EMPTY_REQ_QUEUE_ERROR",
856 "Q_MONIRTT_MGMT_ERROR",
857 "TARGET_MODE_FLOW_ERROR",
858 "DEVICE_QUEUE_NOT_FOUND",
859 "START_IRTT_TIMER_ERROR",
860 "ABORT_TASK_ILLEGAL_REQ",
861 [43 ... 255] = "unknown[43,255]"
862 };
863
864 if (dchstatus & CSEQINT) {
865 u32 arp2int = asd_read_reg_dword(asd_ha, CARP2INT);
866
867 if (arp2int & (ARP2WAITTO|ARP2ILLOPC|ARP2PERR|ARP2CIOPERR)) {
868 asd_printk("%s: CSEQ arp2int:0x%x\n",
869 pci_name(asd_ha->pcidev),
870 arp2int);
871 } else if (arp2int & ARP2HALTC)
872 asd_printk("%s: CSEQ halted: %s\n",
873 pci_name(asd_ha->pcidev),
874 halt_code[(arp2int>>16)&0xFF]);
875 else
876 asd_printk("%s: CARP2INT:0x%x\n",
877 pci_name(asd_ha->pcidev),
878 arp2int);
879 }
880 if (dchstatus & LSEQINT_MASK) {
881 int lseq;
882 u8 lseq_mask = dchstatus & LSEQINT_MASK;
883
884 for_each_sequencer(lseq_mask, lseq_mask, lseq) {
885 u32 arp2int = asd_read_reg_dword(asd_ha,
886 LmARP2INT(lseq));
887 if (arp2int & (ARP2WAITTO | ARP2ILLOPC | ARP2PERR
888 | ARP2CIOPERR)) {
889 asd_printk("%s: LSEQ%d arp2int:0x%x\n",
890 pci_name(asd_ha->pcidev),
891 lseq, arp2int);
892
893 } else if (arp2int & ARP2HALTC)
894 asd_printk("%s: LSEQ%d halted: %s\n",
895 pci_name(asd_ha->pcidev),
896 lseq,halt_code[(arp2int>>16)&0xFF]);
897 else
898 asd_printk("%s: LSEQ%d ARP2INT:0x%x\n",
899 pci_name(asd_ha->pcidev), lseq,
900 arp2int);
901 }
902 }
903 asd_chip_reset(asd_ha);
904}
905
906
907
908
909
910static void asd_dch_sas_isr(struct asd_ha_struct *asd_ha)
911{
912 u32 dchstatus = asd_read_reg_dword(asd_ha, DCHSTATUS);
913
914 if (dchstatus & CFIFTOERR) {
915 asd_printk("%s: CFIFTOERR\n", pci_name(asd_ha->pcidev));
916 asd_chip_reset(asd_ha);
917 } else
918 asd_arp2_err(asd_ha, dchstatus);
919}
920
921
922
923
924
925static void asd_rbi_exsi_isr(struct asd_ha_struct *asd_ha)
926{
927 u32 stat0r = asd_read_reg_dword(asd_ha, ASISTAT0R);
928
929 if (!(stat0r & ASIERR)) {
930 asd_printk("hmm, EXSI interrupted but no error?\n");
931 return;
932 }
933
934 if (stat0r & ASIFMTERR) {
935 asd_printk("ASI SEEPROM format error for %s\n",
936 pci_name(asd_ha->pcidev));
937 } else if (stat0r & ASISEECHKERR) {
938 u32 stat1r = asd_read_reg_dword(asd_ha, ASISTAT1R);
939 asd_printk("ASI SEEPROM checksum 0x%x error for %s\n",
940 stat1r & CHECKSUM_MASK,
941 pci_name(asd_ha->pcidev));
942 } else {
943 u32 statr = asd_read_reg_dword(asd_ha, ASIERRSTATR);
944
945 if (!(statr & CPI2ASIMSTERR_MASK)) {
946 ASD_DPRINTK("hmm, ASIERR?\n");
947 return;
948 } else {
949 u32 addr = asd_read_reg_dword(asd_ha, ASIERRADDR);
950 u32 data = asd_read_reg_dword(asd_ha, ASIERRDATAR);
951
952 asd_printk("%s: CPI2 xfer err: addr: 0x%x, wdata: 0x%x, "
953 "count: 0x%x, byteen: 0x%x, targerr: 0x%x "
954 "master id: 0x%x, master err: 0x%x\n",
955 pci_name(asd_ha->pcidev),
956 addr, data,
957 (statr & CPI2ASIBYTECNT_MASK) >> 16,
958 (statr & CPI2ASIBYTEEN_MASK) >> 12,
959 (statr & CPI2ASITARGERR_MASK) >> 8,
960 (statr & CPI2ASITARGMID_MASK) >> 4,
961 (statr & CPI2ASIMSTERR_MASK));
962 }
963 }
964 asd_chip_reset(asd_ha);
965}
966
967
968
969
970
971
972
973static void asd_hst_pcix_isr(struct asd_ha_struct *asd_ha)
974{
975 u16 status;
976 u32 pcix_status;
977 u32 ecc_status;
978
979 pci_read_config_word(asd_ha->pcidev, PCI_STATUS, &status);
980 pci_read_config_dword(asd_ha->pcidev, PCIX_STATUS, &pcix_status);
981 pci_read_config_dword(asd_ha->pcidev, ECC_CTRL_STAT, &ecc_status);
982
983 if (status & PCI_STATUS_DETECTED_PARITY)
984 asd_printk("parity error for %s\n", pci_name(asd_ha->pcidev));
985 else if (status & PCI_STATUS_REC_MASTER_ABORT)
986 asd_printk("master abort for %s\n", pci_name(asd_ha->pcidev));
987 else if (status & PCI_STATUS_REC_TARGET_ABORT)
988 asd_printk("target abort for %s\n", pci_name(asd_ha->pcidev));
989 else if (status & PCI_STATUS_PARITY)
990 asd_printk("data parity for %s\n", pci_name(asd_ha->pcidev));
991 else if (pcix_status & RCV_SCE) {
992 asd_printk("received split completion error for %s\n",
993 pci_name(asd_ha->pcidev));
994 pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
995
996 return;
997 } else if (pcix_status & UNEXP_SC) {
998 asd_printk("unexpected split completion for %s\n",
999 pci_name(asd_ha->pcidev));
1000 pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
1001
1002 return;
1003 } else if (pcix_status & SC_DISCARD)
1004 asd_printk("split completion discarded for %s\n",
1005 pci_name(asd_ha->pcidev));
1006 else if (ecc_status & UNCOR_ECCERR)
1007 asd_printk("uncorrectable ECC error for %s\n",
1008 pci_name(asd_ha->pcidev));
1009 asd_chip_reset(asd_ha);
1010}
1011
1012
1013
1014
1015
1016
1017
1018
1019irqreturn_t asd_hw_isr(int irq, void *dev_id)
1020{
1021 struct asd_ha_struct *asd_ha = dev_id;
1022 u32 chimint = asd_read_reg_dword(asd_ha, CHIMINT);
1023
1024 if (!chimint)
1025 return IRQ_NONE;
1026
1027 asd_write_reg_dword(asd_ha, CHIMINT, chimint);
1028 (void) asd_read_reg_dword(asd_ha, CHIMINT);
1029
1030 if (chimint & DLAVAIL)
1031 asd_process_donelist_isr(asd_ha);
1032 if (chimint & COMINT)
1033 asd_com_sas_isr(asd_ha);
1034 if (chimint & DEVINT)
1035 asd_dch_sas_isr(asd_ha);
1036 if (chimint & INITERR)
1037 asd_rbi_exsi_isr(asd_ha);
1038 if (chimint & HOSTERR)
1039 asd_hst_pcix_isr(asd_ha);
1040
1041 return IRQ_HANDLED;
1042}
1043
1044
1045
1046static struct asd_ascb *asd_ascb_alloc(struct asd_ha_struct *asd_ha,
1047 gfp_t gfp_flags)
1048{
1049 extern struct kmem_cache *asd_ascb_cache;
1050 struct asd_seq_data *seq = &asd_ha->seq;
1051 struct asd_ascb *ascb;
1052 unsigned long flags;
1053
1054 ascb = kmem_cache_zalloc(asd_ascb_cache, gfp_flags);
1055
1056 if (ascb) {
1057 ascb->dma_scb.size = sizeof(struct scb);
1058 ascb->dma_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool,
1059 gfp_flags,
1060 &ascb->dma_scb.dma_handle);
1061 if (!ascb->dma_scb.vaddr) {
1062 kmem_cache_free(asd_ascb_cache, ascb);
1063 return NULL;
1064 }
1065 memset(ascb->dma_scb.vaddr, 0, sizeof(struct scb));
1066 asd_init_ascb(asd_ha, ascb);
1067
1068 spin_lock_irqsave(&seq->tc_index_lock, flags);
1069 ascb->tc_index = asd_tc_index_get(seq, ascb);
1070 spin_unlock_irqrestore(&seq->tc_index_lock, flags);
1071 if (ascb->tc_index == -1)
1072 goto undo;
1073
1074 ascb->scb->header.index = cpu_to_le16((u16)ascb->tc_index);
1075 }
1076
1077 return ascb;
1078undo:
1079 dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
1080 ascb->dma_scb.dma_handle);
1081 kmem_cache_free(asd_ascb_cache, ascb);
1082 ASD_DPRINTK("no index for ascb\n");
1083 return NULL;
1084}
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
1103 *asd_ha, int *num,
1104 gfp_t gfp_flags)
1105{
1106 struct asd_ascb *first = NULL;
1107
1108 for ( ; *num > 0; --*num) {
1109 struct asd_ascb *ascb = asd_ascb_alloc(asd_ha, gfp_flags);
1110
1111 if (!ascb)
1112 break;
1113 else if (!first)
1114 first = ascb;
1115 else {
1116 struct asd_ascb *last = list_entry(first->list.prev,
1117 struct asd_ascb,
1118 list);
1119 list_add_tail(&ascb->list, &first->list);
1120 last->scb->header.next_scb =
1121 cpu_to_le64(((u64)ascb->dma_scb.dma_handle));
1122 }
1123 }
1124
1125 return first;
1126}
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146static void asd_swap_head_scb(struct asd_ha_struct *asd_ha,
1147 struct asd_ascb *ascb)
1148{
1149 struct asd_seq_data *seq = &asd_ha->seq;
1150 struct asd_ascb *last = list_entry(ascb->list.prev,
1151 struct asd_ascb,
1152 list);
1153 struct asd_dma_tok t = ascb->dma_scb;
1154
1155 memcpy(seq->next_scb.vaddr, ascb->scb, sizeof(*ascb->scb));
1156 ascb->dma_scb = seq->next_scb;
1157 ascb->scb = ascb->dma_scb.vaddr;
1158 seq->next_scb = t;
1159 last->scb->header.next_scb =
1160 cpu_to_le64(((u64)seq->next_scb.dma_handle));
1161}
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173static void asd_start_scb_timers(struct list_head *list)
1174{
1175 struct asd_ascb *ascb;
1176 list_for_each_entry(ascb, list, list) {
1177 if (!ascb->uldd_timer) {
1178 ascb->timer.function = asd_ascb_timedout;
1179 ascb->timer.expires = jiffies + AIC94XX_SCB_TIMEOUT;
1180 add_timer(&ascb->timer);
1181 }
1182 }
1183}
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1205 int num)
1206{
1207 unsigned long flags;
1208 LIST_HEAD(list);
1209 int can_queue;
1210
1211 spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1212 can_queue = asd_ha->hw_prof.max_scbs - asd_ha->seq.pending;
1213 if (can_queue >= num)
1214 asd_ha->seq.pending += num;
1215 else
1216 can_queue = 0;
1217
1218 if (!can_queue) {
1219 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1220 asd_printk("%s: scb queue full\n", pci_name(asd_ha->pcidev));
1221 return -SAS_QUEUE_FULL;
1222 }
1223
1224 asd_swap_head_scb(asd_ha, ascb);
1225
1226 __list_add(&list, ascb->list.prev, &ascb->list);
1227
1228 asd_start_scb_timers(&list);
1229
1230 asd_ha->seq.scbpro += num;
1231 list_splice_init(&list, asd_ha->seq.pend_q.prev);
1232 asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1233 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1234
1235 return 0;
1236}
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1257 int num)
1258{
1259 unsigned long flags;
1260
1261 spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1262 asd_swap_head_scb(asd_ha, ascb);
1263 asd_ha->seq.scbpro += num;
1264 asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1265 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1266
1267 return 0;
1268}
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1279{
1280 if (phy_id < ASD_MAX_PHYS) {
1281 u32 v = asd_read_reg_dword(asd_ha, LmCONTROL(phy_id));
1282 if (op)
1283 v |= LEDPOL;
1284 else
1285 v &= ~LEDPOL;
1286 asd_write_reg_dword(asd_ha, LmCONTROL(phy_id), v);
1287 }
1288}
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1300{
1301 if (phy_id < ASD_MAX_PHYS) {
1302 u32 v;
1303
1304 v = asd_read_reg_dword(asd_ha, GPIOOER);
1305 if (op)
1306 v |= (1 << phy_id);
1307 else
1308 v &= ~(1 << phy_id);
1309 asd_write_reg_dword(asd_ha, GPIOOER, v);
1310
1311 v = asd_read_reg_dword(asd_ha, GPIOCNFGR);
1312 if (op)
1313 v |= (1 << phy_id);
1314 else
1315 v &= ~(1 << phy_id);
1316 asd_write_reg_dword(asd_ha, GPIOCNFGR, v);
1317 }
1318}
1319
1320
1321
1322static int asd_enable_phy(struct asd_ha_struct *asd_ha, int phy_id)
1323{
1324 struct asd_phy *phy = &asd_ha->phys[phy_id];
1325
1326 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, INT_ENABLE_2), 0);
1327 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, HOT_PLUG_DELAY),
1328 HOTPLUG_DELAY_TIMEOUT);
1329
1330
1331
1332 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_0),
1333 phy->phy_desc->phy_control_0);
1334 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_1),
1335 phy->phy_desc->phy_control_1);
1336 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_2),
1337 phy->phy_desc->phy_control_2);
1338 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_3),
1339 phy->phy_desc->phy_control_3);
1340
1341 asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(phy_id),
1342 ASD_COMINIT_TIMEOUT);
1343
1344 asd_write_reg_addr(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(phy_id),
1345 phy->id_frm_tok->dma_handle);
1346
1347 asd_control_led(asd_ha, phy_id, 1);
1348
1349 return 0;
1350}
1351
1352int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask)
1353{
1354 u8 phy_m;
1355 u8 i;
1356 int num = 0, k;
1357 struct asd_ascb *ascb;
1358 struct asd_ascb *ascb_list;
1359
1360 if (!phy_mask) {
1361 asd_printk("%s called with phy_mask of 0!?\n", __func__);
1362 return 0;
1363 }
1364
1365 for_each_phy(phy_mask, phy_m, i) {
1366 num++;
1367 asd_enable_phy(asd_ha, i);
1368 }
1369
1370 k = num;
1371 ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL);
1372 if (!ascb_list) {
1373 asd_printk("no memory for control phy ascb list\n");
1374 return -ENOMEM;
1375 }
1376 num -= k;
1377
1378 ascb = ascb_list;
1379 for_each_phy(phy_mask, phy_m, i) {
1380 asd_build_control_phy(ascb, i, ENABLE_PHY);
1381 ascb = list_entry(ascb->list.next, struct asd_ascb, list);
1382 }
1383 ASD_DPRINTK("posting %d control phy scbs\n", num);
1384 k = asd_post_ascb_list(asd_ha, ascb_list, num);
1385 if (k)
1386 asd_ascb_free_list(ascb_list);
1387
1388 return k;
1389}
1390