LXR linux/drivers/scsi/pm8001/pm8001

   1/*
   2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3 *
   4 * Copyright (c) 2008-2009 USI Co., Ltd.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 * 1. Redistributions of source code must retain the above copyright
  11 *    notice, this list of conditions, and the following disclaimer,
  12 *    without modification.
  13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14 *    substantially similar to the "NO WARRANTY" disclaimer below
  15 *    ("Disclaimer") and any redistribution must be conditioned upon
  16 *    including a substantially similar Disclaimer requirement for further
  17 *    binary redistribution.
  18 * 3. Neither the names of the above-listed copyright holders nor the names
  19 *    of any contributors may be used to endorse or promote products derived
  20 *    from this software without specific prior written permission.
  21 *
  22 * Alternatively, this software may be distributed under the terms of the
  23 * GNU General Public License ("GPL") version 2 as published by the Free
  24 * Software Foundation.
  25 *
  26 * NO WARRANTY
  27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37 * POSSIBILITY OF SUCH DAMAGES.
  38 *
  39 */
  40
  41#ifndef _PM8001_SAS_H_
  42#define _PM8001_SAS_H_
  43
  44#include <linux/kernel.h>
  45#include <linux/module.h>
  46#include <linux/spinlock.h>
  47#include <linux/delay.h>
  48#include <linux/types.h>
  49#include <linux/ctype.h>
  50#include <linux/dma-mapping.h>
  51#include <linux/pci.h>
  52#include <linux/interrupt.h>
  53#include <linux/workqueue.h>
  54#include <scsi/libsas.h>
  55#include <scsi/scsi_tcq.h>
  56#include <scsi/sas_ata.h>
  57#include <linux/atomic.h>
  58#include "pm8001_defs.h"
  59
  60#define DRV_NAME                "pm80xx"
  61#define DRV_VERSION             "0.1.38"
  62#define PM8001_FAIL_LOGGING     0x01 /* Error message logging */
  63#define PM8001_INIT_LOGGING     0x02 /* driver init logging */
  64#define PM8001_DISC_LOGGING     0x04 /* discovery layer logging */
  65#define PM8001_IO_LOGGING       0x08 /* I/O path logging */
  66#define PM8001_EH_LOGGING       0x10 /* libsas EH function logging*/
  67#define PM8001_IOCTL_LOGGING    0x20 /* IOCTL message logging */
  68#define PM8001_MSG_LOGGING      0x40 /* misc message logging */
  69#define pm8001_printk(format, arg...)   printk(KERN_INFO "pm80xx %s %d:" \
  70                        format, __func__, __LINE__, ## arg)
  71#define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD)   \
  72do {                                            \
  73        if (unlikely(HBA->logging_level & LEVEL))       \
  74                do {                                    \
  75                        CMD;                            \
  76                } while (0);                            \
  77} while (0);
  78
  79#define PM8001_EH_DBG(HBA, CMD)                 \
  80        PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
  81
  82#define PM8001_INIT_DBG(HBA, CMD)               \
  83        PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
  84
  85#define PM8001_DISC_DBG(HBA, CMD)               \
  86        PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
  87
  88#define PM8001_IO_DBG(HBA, CMD)         \
  89        PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
  90
  91#define PM8001_FAIL_DBG(HBA, CMD)               \
  92        PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
  93
  94#define PM8001_IOCTL_DBG(HBA, CMD)              \
  95        PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
  96
  97#define PM8001_MSG_DBG(HBA, CMD)                \
  98        PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
  99
 100
 101#define PM8001_USE_TASKLET
 102#define PM8001_USE_MSIX
 103#define PM8001_READ_VPD
 104
 105
 106#define DEV_IS_EXPANDER(type)   ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
 107#define IS_SPCV_12G(dev)        ((dev->device == 0X8074)                \
 108                                || (dev->device == 0X8076)              \
 109                                || (dev->device == 0X8077)              \
 110                                || (dev->device == 0X8070)              \
 111                                || (dev->device == 0X8072))
 112
 113#define PM8001_NAME_LENGTH              32/* generic length of strings */
 114extern struct list_head hba_list;
 115extern const struct pm8001_dispatch pm8001_8001_dispatch;
 116extern const struct pm8001_dispatch pm8001_80xx_dispatch;
 117
 118struct pm8001_hba_info;
 119struct pm8001_ccb_info;
 120struct pm8001_device;
 121/* define task management IU */
 122struct pm8001_tmf_task {
 123        u8      tmf;
 124        u32     tag_of_task_to_be_managed;
 125};
 126struct pm8001_ioctl_payload {
 127        u32     signature;
 128        u16     major_function;
 129        u16     minor_function;
 130        u16     length;
 131        u16     status;
 132        u16     offset;
 133        u16     id;
 134        u8      *func_specific;
 135};
 136
 137#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
 138#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
 139#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET            0x00     /* HNFBUFL */
 140#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET            0x04     /* HNFBUFH */
 141#define MPI_FATAL_EDUMP_TABLE_LENGTH               0x08     /* HNFBLEN */
 142#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE            0x0C     /* FDDHSHK */
 143#define MPI_FATAL_EDUMP_TABLE_STATUS               0x10     /* FDDTSTAT */
 144#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN            0x14     /* ACCDDLEN */
 145#define MPI_FATAL_EDUMP_HANDSHAKE_RDY              0x1
 146#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY             0x0
 147#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD                 0x0
 148#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED           0x1
 149#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
 150#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE      0x3
 151#define TYPE_GSM_SPACE        1
 152#define TYPE_QUEUE            2
 153#define TYPE_FATAL            3
 154#define TYPE_NON_FATAL        4
 155#define TYPE_INBOUND          1
 156#define TYPE_OUTBOUND         2
 157struct forensic_data {
 158        u32  data_type;
 159        union {
 160                struct {
 161                        u32  direct_len;
 162                        u32  direct_offset;
 163                        void  *direct_data;
 164                } gsm_buf;
 165                struct {
 166                        u16  queue_type;
 167                        u16  queue_index;
 168                        u32  direct_len;
 169                        void  *direct_data;
 170                } queue_buf;
 171                struct {
 172                        u32  direct_len;
 173                        u32  direct_offset;
 174                        u32  read_len;
 175                        void  *direct_data;
 176                } data_buf;
 177        };
 178};
 179
 180/* bit31-26 - mask bar */
 181#define SCRATCH_PAD0_BAR_MASK                    0xFC000000
 182/* bit25-0  - offset mask */
 183#define SCRATCH_PAD0_OFFSET_MASK                 0x03FFFFFF
 184/* if AAP error state */
 185#define SCRATCH_PAD0_AAPERR_MASK                 0xFFFFFFFF
 186/* Inbound doorbell bit7 */
 187#define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP        0x80
 188/* Inbound doorbell bit7 SPCV */
 189#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO  0x80
 190#define MAIN_MERRDCTO_MERRDCES                   0xA0/* DWORD 0x28) */
 191
 192struct pm8001_dispatch {
 193        char *name;
 194        int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
 195        int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
 196        void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
 197        int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
 198        void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
 199        irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 200        u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
 201        int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 202        void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 203        void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
 204        void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
 205        int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
 206                struct pm8001_ccb_info *ccb);
 207        int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
 208                struct pm8001_ccb_info *ccb);
 209        int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
 210                struct pm8001_ccb_info *ccb);
 211        int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
 212        int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
 213        int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
 214                struct pm8001_device *pm8001_dev, u32 flag);
 215        int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
 216        int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
 217                u32 phy_id, u32 phy_op);
 218        int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
 219                struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
 220                u32 cmd_tag);
 221        int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
 222                struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
 223        int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
 224        int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
 225        int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
 226                void *payload);
 227        int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
 228                struct pm8001_device *pm8001_dev, u32 state);
 229        int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
 230                u32 state);
 231        int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
 232                u32 state);
 233        int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
 234};
 235
 236struct pm8001_chip_info {
 237        u32     encrypt;
 238        u32     n_phy;
 239        const struct pm8001_dispatch    *dispatch;
 240};
 241#define PM8001_CHIP_DISP        (pm8001_ha->chip->dispatch)
 242
 243struct pm8001_port {
 244        struct asd_sas_port     sas_port;
 245        u8                      port_attached;
 246        u16                     wide_port_phymap;
 247        u8                      port_state;
 248        struct list_head        list;
 249};
 250
 251struct pm8001_phy {
 252        struct pm8001_hba_info  *pm8001_ha;
 253        struct pm8001_port      *port;
 254        struct asd_sas_phy      sas_phy;
 255        struct sas_identify     identify;
 256        struct scsi_device      *sdev;
 257        u64                     dev_sas_addr;
 258        u32                     phy_type;
 259        struct completion       *enable_completion;
 260        u32                     frame_rcvd_size;
 261        u8                      frame_rcvd[32];
 262        u8                      phy_attached;
 263        u8                      phy_state;
 264        enum sas_linkrate       minimum_linkrate;
 265        enum sas_linkrate       maximum_linkrate;
 266        struct completion       *reset_completion;
 267        bool                    port_reset_status;
 268        bool                    reset_success;
 269};
 270
 271/* port reset status */
 272#define PORT_RESET_SUCCESS      0x00
 273#define PORT_RESET_TMO          0x01
 274
 275struct pm8001_device {
 276        enum sas_device_type    dev_type;
 277        struct domain_device    *sas_device;
 278        u32                     attached_phy;
 279        u32                     id;
 280        struct completion       *dcompletion;
 281        struct completion       *setds_completion;
 282        u32                     device_id;
 283        u32                     running_req;
 284};
 285
 286struct pm8001_prd_imt {
 287        __le32                  len;
 288        __le32                  e;
 289};
 290
 291struct pm8001_prd {
 292        __le64                  addr;           /* 64-bit buffer address */
 293        struct pm8001_prd_imt   im_len;         /* 64-bit length */
 294} __attribute__ ((packed));
 295/*
 296 * CCB(Command Control Block)
 297 */
 298struct pm8001_ccb_info {
 299        struct list_head        entry;
 300        struct sas_task         *task;
 301        u32                     n_elem;
 302        u32                     ccb_tag;
 303        dma_addr_t              ccb_dma_handle;
 304        struct pm8001_device    *device;
 305        struct pm8001_prd       buf_prd[PM8001_MAX_DMA_SG];
 306        struct fw_control_ex    *fw_control_context;
 307        u8                      open_retry;
 308};
 309
 310struct mpi_mem {
 311        void                    *virt_ptr;
 312        dma_addr_t              phys_addr;
 313        u32                     phys_addr_hi;
 314        u32                     phys_addr_lo;
 315        u32                     total_len;
 316        u32                     num_elements;
 317        u32                     element_size;
 318        u32                     alignment;
 319};
 320
 321struct mpi_mem_req {
 322        /* The number of element in the  mpiMemory array */
 323        u32                     count;
 324        /* The array of structures that define memroy regions*/
 325        struct mpi_mem          region[USI_MAX_MEMCNT];
 326};
 327
 328struct encrypt {
 329        u32     cipher_mode;
 330        u32     sec_mode;
 331        u32     status;
 332        u32     flag;
 333};
 334
 335struct sas_phy_attribute_table {
 336        u32     phystart1_16[16];
 337        u32     outbound_hw_event_pid1_16[16];
 338};
 339
 340union main_cfg_table {
 341        struct {
 342        u32                     signature;
 343        u32                     interface_rev;
 344        u32                     firmware_rev;
 345        u32                     max_out_io;
 346        u32                     max_sgl;
 347        u32                     ctrl_cap_flag;
 348        u32                     gst_offset;
 349        u32                     inbound_queue_offset;
 350        u32                     outbound_queue_offset;
 351        u32                     inbound_q_nppd_hppd;
 352        u32                     outbound_hw_event_pid0_3;
 353        u32                     outbound_hw_event_pid4_7;
 354        u32                     outbound_ncq_event_pid0_3;
 355        u32                     outbound_ncq_event_pid4_7;
 356        u32                     outbound_tgt_ITNexus_event_pid0_3;
 357        u32                     outbound_tgt_ITNexus_event_pid4_7;
 358        u32                     outbound_tgt_ssp_event_pid0_3;
 359        u32                     outbound_tgt_ssp_event_pid4_7;
 360        u32                     outbound_tgt_smp_event_pid0_3;
 361        u32                     outbound_tgt_smp_event_pid4_7;
 362        u32                     upper_event_log_addr;
 363        u32                     lower_event_log_addr;
 364        u32                     event_log_size;
 365        u32                     event_log_option;
 366        u32                     upper_iop_event_log_addr;
 367        u32                     lower_iop_event_log_addr;
 368        u32                     iop_event_log_size;
 369        u32                     iop_event_log_option;
 370        u32                     fatal_err_interrupt;
 371        u32                     fatal_err_dump_offset0;
 372        u32                     fatal_err_dump_length0;
 373        u32                     fatal_err_dump_offset1;
 374        u32                     fatal_err_dump_length1;
 375        u32                     hda_mode_flag;
 376        u32                     anolog_setup_table_offset;
 377        u32                     rsvd[4];
 378        } pm8001_tbl;
 379
 380        struct {
 381        u32                     signature;
 382        u32                     interface_rev;
 383        u32                     firmware_rev;
 384        u32                     max_out_io;
 385        u32                     max_sgl;
 386        u32                     ctrl_cap_flag;
 387        u32                     gst_offset;
 388        u32                     inbound_queue_offset;
 389        u32                     outbound_queue_offset;
 390        u32                     inbound_q_nppd_hppd;
 391        u32                     rsvd[8];
 392        u32                     crc_core_dump;
 393        u32                     rsvd1;
 394        u32                     upper_event_log_addr;
 395        u32                     lower_event_log_addr;
 396        u32                     event_log_size;
 397        u32                     event_log_severity;
 398        u32                     upper_pcs_event_log_addr;
 399        u32                     lower_pcs_event_log_addr;
 400        u32                     pcs_event_log_size;
 401        u32                     pcs_event_log_severity;
 402        u32                     fatal_err_interrupt;
 403        u32                     fatal_err_dump_offset0;
 404        u32                     fatal_err_dump_length0;
 405        u32                     fatal_err_dump_offset1;
 406        u32                     fatal_err_dump_length1;
 407        u32                     gpio_led_mapping;
 408        u32                     analog_setup_table_offset;
 409        u32                     int_vec_table_offset;
 410        u32                     phy_attr_table_offset;
 411        u32                     port_recovery_timer;
 412        u32                     interrupt_reassertion_delay;
 413        u32                     fatal_n_non_fatal_dump;         /* 0x28 */
 414        u32                     ila_version;
 415        u32                     inc_fw_version;
 416        } pm80xx_tbl;
 417};
 418
 419union general_status_table {
 420        struct {
 421        u32                     gst_len_mpistate;
 422        u32                     iq_freeze_state0;
 423        u32                     iq_freeze_state1;
 424        u32                     msgu_tcnt;
 425        u32                     iop_tcnt;
 426        u32                     rsvd;
 427        u32                     phy_state[8];
 428        u32                     gpio_input_val;
 429        u32                     rsvd1[2];
 430        u32                     recover_err_info[8];
 431        } pm8001_tbl;
 432        struct {
 433        u32                     gst_len_mpistate;
 434        u32                     iq_freeze_state0;
 435        u32                     iq_freeze_state1;
 436        u32                     msgu_tcnt;
 437        u32                     iop_tcnt;
 438        u32                     rsvd[9];
 439        u32                     gpio_input_val;
 440        u32                     rsvd1[2];
 441        u32                     recover_err_info[8];
 442        } pm80xx_tbl;
 443};
 444struct inbound_queue_table {
 445        u32                     element_pri_size_cnt;
 446        u32                     upper_base_addr;
 447        u32                     lower_base_addr;
 448        u32                     ci_upper_base_addr;
 449        u32                     ci_lower_base_addr;
 450        u32                     pi_pci_bar;
 451        u32                     pi_offset;
 452        u32                     total_length;
 453        void                    *base_virt;
 454        void                    *ci_virt;
 455        u32                     reserved;
 456        __le32                  consumer_index;
 457        u32                     producer_idx;
 458};
 459struct outbound_queue_table {
 460        u32                     element_size_cnt;
 461        u32                     upper_base_addr;
 462        u32                     lower_base_addr;
 463        void                    *base_virt;
 464        u32                     pi_upper_base_addr;
 465        u32                     pi_lower_base_addr;
 466        u32                     ci_pci_bar;
 467        u32                     ci_offset;
 468        u32                     total_length;
 469        void                    *pi_virt;
 470        u32                     interrup_vec_cnt_delay;
 471        u32                     dinterrup_to_pci_offset;
 472        __le32                  producer_index;
 473        u32                     consumer_idx;
 474};
 475struct pm8001_hba_memspace {
 476        void __iomem            *memvirtaddr;
 477        u64                     membase;
 478        u32                     memsize;
 479};
 480struct isr_param {
 481        struct pm8001_hba_info *drv_inst;
 482        u32 irq_id;
 483};
 484struct pm8001_hba_info {
 485        char                    name[PM8001_NAME_LENGTH];
 486        struct list_head        list;
 487        unsigned long           flags;
 488        spinlock_t              lock;/* host-wide lock */
 489        spinlock_t              bitmap_lock;
 490        struct pci_dev          *pdev;/* our device */
 491        struct device           *dev;
 492        struct pm8001_hba_memspace io_mem[6];
 493        struct mpi_mem_req      memoryMap;
 494        struct encrypt          encrypt_info; /* support encryption */
 495        struct forensic_data    forensic_info;
 496        u32                     fatal_bar_loc;
 497        u32                     forensic_last_offset;
 498        u32                     fatal_forensic_shift_offset;
 499        u32                     forensic_fatal_step;
 500        u32                     evtlog_ib_offset;
 501        u32                     evtlog_ob_offset;
 502        void __iomem    *msg_unit_tbl_addr;/*Message Unit Table Addr*/
 503        void __iomem    *main_cfg_tbl_addr;/*Main Config Table Addr*/
 504        void __iomem    *general_stat_tbl_addr;/*General Status Table Addr*/
 505        void __iomem    *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
 506        void __iomem    *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
 507        void __iomem    *pspa_q_tbl_addr;
 508                        /*MPI SAS PHY attributes Queue Config Table Addr*/
 509        void __iomem    *ivt_tbl_addr; /*MPI IVT Table Addr */
 510        void __iomem    *fatal_tbl_addr; /*MPI IVT Table Addr */
 511        union main_cfg_table    main_cfg_tbl;
 512        union general_status_table      gs_tbl;
 513        struct inbound_queue_table      inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM];
 514        struct outbound_queue_table     outbnd_q_tbl[PM8001_MAX_SPCV_OUTB_NUM];
 515        struct sas_phy_attribute_table  phy_attr_table;
 516                                        /* MPI SAS PHY attributes */
 517        u8                      sas_addr[SAS_ADDR_SIZE];
 518        struct sas_ha_struct    *sas;/* SCSI/SAS glue */
 519        struct Scsi_Host        *shost;
 520        u32                     chip_id;
 521        const struct pm8001_chip_info   *chip;
 522        struct completion       *nvmd_completion;
 523        int                     tags_num;
 524        unsigned long           *tags;
 525        struct pm8001_phy       phy[PM8001_MAX_PHYS];
 526        struct pm8001_port      port[PM8001_MAX_PHYS];
 527        u32                     id;
 528        u32                     irq;
 529        u32                     iomb_size; /* SPC and SPCV IOMB size */
 530        struct pm8001_device    *devices;
 531        struct pm8001_ccb_info  *ccb_info;
 532#ifdef PM8001_USE_MSIX
 533        int                     number_of_intr;/*will be used in remove()*/
 534#endif
 535#ifdef PM8001_USE_TASKLET
 536        struct tasklet_struct   tasklet[PM8001_MAX_MSIX_VEC];
 537#endif
 538        u32                     logging_level;
 539        u32                     fw_status;
 540        u32                     smp_exp_mode;
 541        const struct firmware   *fw_image;
 542        struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
 543        u32                     reset_in_progress;
 544};
 545
 546struct pm8001_work {
 547        struct work_struct work;
 548        struct pm8001_hba_info *pm8001_ha;
 549        void *data;
 550        int handler;
 551};
 552
 553struct pm8001_fw_image_header {
 554        u8 vender_id[8];
 555        u8 product_id;
 556        u8 hardware_rev;
 557        u8 dest_partition;
 558        u8 reserved;
 559        u8 fw_rev[4];
 560        __be32  image_length;
 561        __be32 image_crc;
 562        __be32 startup_entry;
 563} __attribute__((packed, aligned(4)));
 564
 565
 566/**
 567 * FW Flash Update status values
 568 */
 569#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT    0x00
 570#define FLASH_UPDATE_IN_PROGRESS                0x01
 571#define FLASH_UPDATE_HDR_ERR                    0x02
 572#define FLASH_UPDATE_OFFSET_ERR                 0x03
 573#define FLASH_UPDATE_CRC_ERR                    0x04
 574#define FLASH_UPDATE_LENGTH_ERR                 0x05
 575#define FLASH_UPDATE_HW_ERR                     0x06
 576#define FLASH_UPDATE_DNLD_NOT_SUPPORTED         0x10
 577#define FLASH_UPDATE_DISABLED                   0x11
 578
 579#define NCQ_READ_LOG_FLAG                       0x80000000
 580#define NCQ_ABORT_ALL_FLAG                      0x40000000
 581#define NCQ_2ND_RLE_FLAG                        0x20000000
 582
 583/* Device states */
 584#define DS_OPERATIONAL                          0x01
 585#define DS_PORT_IN_RESET                        0x02
 586#define DS_IN_RECOVERY                          0x03
 587#define DS_IN_ERROR                             0x04
 588#define DS_NON_OPERATIONAL                      0x07
 589
 590/**
 591 * brief param structure for firmware flash update.
 592 */
 593struct fw_flash_updata_info {
 594        u32                     cur_image_offset;
 595        u32                     cur_image_len;
 596        u32                     total_image_len;
 597        struct pm8001_prd       sgl;
 598};
 599
 600struct fw_control_info {
 601        u32                     retcode;/*ret code (status)*/
 602        u32                     phase;/*ret code phase*/
 603        u32                     phaseCmplt;/*percent complete for the current
 604        update phase */
 605        u32                     version;/*Hex encoded firmware version number*/
 606        u32                     offset;/*Used for downloading firmware  */
 607        u32                     len; /*len of buffer*/
 608        u32                     size;/* Used in OS VPD and Trace get size
 609        operations.*/
 610        u32                     reserved;/* padding required for 64 bit
 611        alignment */
 612        u8                      buffer[1];/* Start of buffer */
 613};
 614struct fw_control_ex {
 615        struct fw_control_info *fw_control;
 616        void                    *buffer;/* keep buffer pointer to be
 617        freed when the response comes*/
 618        void                    *virtAddr;/* keep virtual address of the data */
 619        void                    *usrAddr;/* keep virtual address of the
 620        user data */
 621        dma_addr_t              phys_addr;
 622        u32                     len; /* len of buffer  */
 623        void                    *payload; /* pointer to IOCTL Payload */
 624        u8                      inProgress;/*if 1 - the IOCTL request is in
 625        progress */
 626        void                    *param1;
 627        void                    *param2;
 628        void                    *param3;
 629};
 630
 631/* pm8001 workqueue */
 632extern struct workqueue_struct *pm8001_wq;
 633
 634/******************** function prototype *********************/
 635int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
 636void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
 637u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
 638void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
 639        struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
 640int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
 641        void *funcdata);
 642void pm8001_scan_start(struct Scsi_Host *shost);
 643int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
 644int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
 645int pm8001_abort_task(struct sas_task *task);
 646int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
 647int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
 648int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
 649int pm8001_dev_found(struct domain_device *dev);
 650void pm8001_dev_gone(struct domain_device *dev);
 651int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
 652int pm8001_I_T_nexus_reset(struct domain_device *dev);
 653int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
 654int pm8001_query_task(struct sas_task *task);
 655void pm8001_open_reject_retry(
 656        struct pm8001_hba_info *pm8001_ha,
 657        struct sas_task *task_to_close,
 658        struct pm8001_device *device_to_close);
 659int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
 660        dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
 661        u32 mem_size, u32 align);
 662
 663void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
 664int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
 665                        struct inbound_queue_table *circularQ,
 666                        u32 opCode, void *payload, u32 responseQueue);
 667int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
 668                                u16 messageSize, void **messagePtr);
 669u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
 670                        struct outbound_queue_table *circularQ, u8 bc);
 671u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
 672                        struct outbound_queue_table *circularQ,
 673                        void **messagePtr1, u8 *pBC);
 674int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
 675                        struct pm8001_device *pm8001_dev, u32 state);
 676int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
 677                                        void *payload);
 678int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
 679                                        void *fw_flash_updata_info, u32 tag);
 680int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
 681int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
 682int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
 683                                struct pm8001_ccb_info *ccb,
 684                                struct pm8001_tmf_task *tmf);
 685int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
 686                                struct pm8001_device *pm8001_dev,
 687                                u8 flag, u32 task_tag, u32 cmd_tag);
 688int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
 689void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
 690void pm8001_work_fn(struct work_struct *work);
 691int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
 692                                        void *data, int handler);
 693void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
 694                                                        void *piomb);
 695void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
 696                                                        void *piomb);
 697void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
 698                                                        void *piomb);
 699int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
 700                                                        void *piomb);
 701void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
 702void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
 703void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
 704int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 705int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 706int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
 707                                                        void *piomb);
 708int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
 709int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
 710struct sas_task *pm8001_alloc_task(void);
 711void pm8001_task_done(struct sas_task *task);
 712void pm8001_free_task(struct sas_task *task);
 713void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
 714struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
 715                                        u32 device_id);
 716int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
 717
 718int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
 719void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
 720        u32 length, u8 *buf);
 721void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
 722                u32 phy, u32 length, u32 *buf);
 723int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
 724ssize_t pm80xx_get_fatal_dump(struct device *cdev,
 725                struct device_attribute *attr, char *buf);
 726ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
 727/* ctl shared API */
 728extern struct device_attribute *pm8001_host_attrs[];
 729
 730static inline void
 731pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
 732                        struct sas_task *task, struct pm8001_ccb_info *ccb,
 733                        u32 ccb_idx)
 734{
 735        pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
 736        smp_mb(); /*in order to force CPU ordering*/
 737        spin_unlock(&pm8001_ha->lock);
 738        task->task_done(task);
 739        spin_lock(&pm8001_ha->lock);
 740}
 741
 742#endif
 743
 744