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41#ifndef _PMC8001_REG_H_
42#define _PMC8001_REG_H_
43
44#include <linux/types.h>
45#include <scsi/libsas.h>
46
47
48#define OPC_INB_ECHO 1
49#define OPC_INB_PHYSTART 4
50#define OPC_INB_PHYSTOP 5
51#define OPC_INB_SSPINIIOSTART 6
52#define OPC_INB_SSPINITMSTART 7
53
54#define OPC_INB_RSVD 8
55#define OPC_INB_DEV_HANDLE_ACCEPT 9
56#define OPC_INB_SSPTGTIOSTART 10
57#define OPC_INB_SSPTGTRSPSTART 11
58
59#define OPC_INB_SSP_ABORT 15
60#define OPC_INB_DEREG_DEV_HANDLE 16
61#define OPC_INB_GET_DEV_HANDLE 17
62#define OPC_INB_SMP_REQUEST 18
63
64#define OPC_INB_SMP_ABORT 20
65
66#define OPC_INB_RSVD1 22
67#define OPC_INB_SATA_HOST_OPSTART 23
68#define OPC_INB_SATA_ABORT 24
69#define OPC_INB_LOCAL_PHY_CONTROL 25
70
71#define OPC_INB_RSVD2 26
72#define OPC_INB_FW_FLASH_UPDATE 32
73#define OPC_INB_GPIO 34
74#define OPC_INB_SAS_DIAG_MODE_START_END 35
75#define OPC_INB_SAS_DIAG_EXECUTE 36
76
77#define OPC_INB_RSVD3 37
78#define OPC_INB_GET_TIME_STAMP 38
79#define OPC_INB_PORT_CONTROL 39
80#define OPC_INB_GET_NVMD_DATA 40
81#define OPC_INB_SET_NVMD_DATA 41
82#define OPC_INB_SET_DEVICE_STATE 42
83#define OPC_INB_GET_DEVICE_STATE 43
84#define OPC_INB_SET_DEV_INFO 44
85
86#define OPC_INB_RSVD4 45
87#define OPC_INB_SGPIO_REGISTER 46
88#define OPC_INB_PCIE_DIAG_EXEC 47
89#define OPC_INB_SET_CONTROLLER_CONFIG 48
90#define OPC_INB_GET_CONTROLLER_CONFIG 49
91#define OPC_INB_REG_DEV 50
92#define OPC_INB_SAS_HW_EVENT_ACK 51
93#define OPC_INB_GET_DEVICE_INFO 52
94#define OPC_INB_GET_PHY_PROFILE 53
95#define OPC_INB_FLASH_OP_EXT 54
96#define OPC_INB_SET_PHY_PROFILE 55
97#define OPC_INB_KEK_MANAGEMENT 256
98#define OPC_INB_DEK_MANAGEMENT 257
99#define OPC_INB_SSP_INI_DIF_ENC_IO 258
100#define OPC_INB_SATA_DIF_ENC_IO 259
101
102
103#define OPC_OUB_ECHO 1
104#define OPC_OUB_RSVD 4
105#define OPC_OUB_SSP_COMP 5
106#define OPC_OUB_SMP_COMP 6
107#define OPC_OUB_LOCAL_PHY_CNTRL 7
108#define OPC_OUB_RSVD1 10
109#define OPC_OUB_DEREG_DEV 11
110#define OPC_OUB_GET_DEV_HANDLE 12
111#define OPC_OUB_SATA_COMP 13
112#define OPC_OUB_SATA_EVENT 14
113#define OPC_OUB_SSP_EVENT 15
114#define OPC_OUB_RSVD2 16
115
116#define OPC_OUB_SSP_RECV_EVENT 18
117#define OPC_OUB_RSVD3 19
118#define OPC_OUB_FW_FLASH_UPDATE 20
119#define OPC_OUB_GPIO_RESPONSE 22
120#define OPC_OUB_GPIO_EVENT 23
121#define OPC_OUB_GENERAL_EVENT 24
122#define OPC_OUB_SSP_ABORT_RSP 26
123#define OPC_OUB_SATA_ABORT_RSP 27
124#define OPC_OUB_SAS_DIAG_MODE_START_END 28
125#define OPC_OUB_SAS_DIAG_EXECUTE 29
126#define OPC_OUB_GET_TIME_STAMP 30
127#define OPC_OUB_RSVD4 31
128#define OPC_OUB_PORT_CONTROL 32
129#define OPC_OUB_SKIP_ENTRY 33
130#define OPC_OUB_SMP_ABORT_RSP 34
131#define OPC_OUB_GET_NVMD_DATA 35
132#define OPC_OUB_SET_NVMD_DATA 36
133#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37
134#define OPC_OUB_SET_DEVICE_STATE 38
135#define OPC_OUB_GET_DEVICE_STATE 39
136#define OPC_OUB_SET_DEV_INFO 40
137#define OPC_OUB_RSVD5 41
138#define OPC_OUB_HW_EVENT 1792
139#define OPC_OUB_DEV_HANDLE_ARRIV 1824
140#define OPC_OUB_THERM_HW_EVENT 1840
141#define OPC_OUB_SGPIO_RESP 2094
142#define OPC_OUB_PCIE_DIAG_EXECUTE 2095
143#define OPC_OUB_DEV_REGIST 2098
144#define OPC_OUB_SAS_HW_EVENT_ACK 2099
145#define OPC_OUB_GET_DEVICE_INFO 2100
146
147#define OPC_OUB_PHY_START_RESP 2052
148#define OPC_OUB_PHY_STOP_RESP 2053
149#define OPC_OUB_SET_CONTROLLER_CONFIG 2096
150#define OPC_OUB_GET_CONTROLLER_CONFIG 2097
151#define OPC_OUB_GET_PHY_PROFILE 2101
152#define OPC_OUB_FLASH_OP_EXT 2102
153#define OPC_OUB_SET_PHY_PROFILE 2103
154#define OPC_OUB_KEK_MANAGEMENT_RESP 2304
155#define OPC_OUB_DEK_MANAGEMENT_RESP 2305
156#define OPC_OUB_SSP_COALESCED_COMP_RESP 2306
157
158
159#define SSC_DISABLE_15 (0x01 << 16)
160#define SSC_DISABLE_30 (0x02 << 16)
161#define SSC_DISABLE_60 (0x04 << 16)
162#define SAS_ASE (0x01 << 15)
163#define SPINHOLD_DISABLE (0x00 << 14)
164#define SPINHOLD_ENABLE (0x01 << 14)
165#define LINKMODE_SAS (0x01 << 12)
166#define LINKMODE_DSATA (0x02 << 12)
167#define LINKMODE_AUTO (0x03 << 12)
168#define LINKRATE_15 (0x01 << 8)
169#define LINKRATE_30 (0x02 << 8)
170#define LINKRATE_60 (0x04 << 8)
171#define LINKRATE_120 (0x08 << 8)
172
173
174#define SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
175#define PHY_DWORD_LENGTH 0xC
176
177
178#define THERMAL_ENABLE 0x1
179#define THERMAL_LOG_ENABLE 0x1
180#define THERMAL_PAGE_CODE_7H 0x6
181#define THERMAL_PAGE_CODE_8H 0x7
182#define LTEMPHIL 70
183#define RTEMPHIL 100
184
185
186#define SCRATCH_PAD3_ENC_DISABLED 0x00000000
187#define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001
188#define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002
189#define SCRATCH_PAD3_ENC_READY 0x00000003
190#define SCRATCH_PAD3_ENC_MASK SCRATCH_PAD3_ENC_READY
191
192#define SCRATCH_PAD3_XTS_ENABLED (1 << 14)
193#define SCRATCH_PAD3_SMA_ENABLED (1 << 4)
194#define SCRATCH_PAD3_SMB_ENABLED (1 << 5)
195#define SCRATCH_PAD3_SMF_ENABLED 0
196#define SCRATCH_PAD3_SM_MASK 0x000000F0
197#define SCRATCH_PAD3_ERR_CODE 0x00FF0000
198
199#define SEC_MODE_SMF 0x0
200#define SEC_MODE_SMA 0x100
201#define SEC_MODE_SMB 0x200
202#define CIPHER_MODE_ECB 0x00000001
203#define CIPHER_MODE_XTS 0x00000002
204#define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
205
206
207#define SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
208#define STP_MCT_TMO 32
209#define SSP_MCT_TMO 32
210#define SAS_MAX_OPEN_TIME 5
211#define SMP_MAX_CONN_TIMER 0xFF
212#define STP_FRM_TIMER 0
213#define STP_IDLE_TIME 5
214#define SAS_MFD 0
215#define SAS_OPNRJT_RTRY_INTVL 2
216#define SAS_DOPNRJT_RTRY_TMO 128
217#define SAS_COPNRJT_RTRY_TMO 128
218
219
220#define PHY_STATE_LINK_UP_SPCV 0x2
221
222
223
224
225
226#define SAS_DOPNRJT_RTRY_THR 23438
227#define SAS_COPNRJT_RTRY_THR 23438
228#define SAS_MAX_AIP 0x200000
229#define IT_NEXUS_TIMEOUT 0x7D0
230#define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30)
231
232#ifdef __LITTLE_ENDIAN_BITFIELD
233struct sas_identify_frame_local {
234
235 u8 frame_type:4;
236 u8 dev_type:3;
237 u8 _un0:1;
238
239
240 u8 _un1;
241
242
243 union {
244 struct {
245 u8 _un20:1;
246 u8 smp_iport:1;
247 u8 stp_iport:1;
248 u8 ssp_iport:1;
249 u8 _un247:4;
250 };
251 u8 initiator_bits;
252 };
253
254
255 union {
256 struct {
257 u8 _un30:1;
258 u8 smp_tport:1;
259 u8 stp_tport:1;
260 u8 ssp_tport:1;
261 u8 _un347:4;
262 };
263 u8 target_bits;
264 };
265
266
267 u8 _un4_11[8];
268
269
270 u8 sas_addr[SAS_ADDR_SIZE];
271
272
273 u8 phy_id;
274
275 u8 _un21_27[7];
276
277} __packed;
278
279#elif defined(__BIG_ENDIAN_BITFIELD)
280struct sas_identify_frame_local {
281
282 u8 _un0:1;
283 u8 dev_type:3;
284 u8 frame_type:4;
285
286
287 u8 _un1;
288
289
290 union {
291 struct {
292 u8 _un247:4;
293 u8 ssp_iport:1;
294 u8 stp_iport:1;
295 u8 smp_iport:1;
296 u8 _un20:1;
297 };
298 u8 initiator_bits;
299 };
300
301
302 union {
303 struct {
304 u8 _un347:4;
305 u8 ssp_tport:1;
306 u8 stp_tport:1;
307 u8 smp_tport:1;
308 u8 _un30:1;
309 };
310 u8 target_bits;
311 };
312
313
314 u8 _un4_11[8];
315
316
317 u8 sas_addr[SAS_ADDR_SIZE];
318
319
320 u8 phy_id;
321
322 u8 _un21_27[7];
323} __packed;
324#else
325#error "Bitfield order not defined!"
326#endif
327
328struct mpi_msg_hdr {
329 __le32 header;
330
331
332
333
334
335
336
337
338} __attribute__((packed, aligned(4)));
339
340
341
342
343
344struct phy_start_req {
345 __le32 tag;
346 __le32 ase_sh_lm_slr_phyid;
347 struct sas_identify_frame_local sas_identify;
348 __le32 spasti;
349 u32 reserved[21];
350} __attribute__((packed, aligned(4)));
351
352
353
354
355
356struct phy_stop_req {
357 __le32 tag;
358 __le32 phy_id;
359 u32 reserved[29];
360} __attribute__((packed, aligned(4)));
361
362
363struct set_dev_bits_fis {
364 u8 fis_type;
365 u8 n_i_pmport;
366
367
368
369
370 u8 status;
371 u8 error;
372 u32 _r_a;
373} __attribute__ ((packed));
374
375struct pio_setup_fis {
376 u8 fis_type;
377 u8 i_d_pmPort;
378
379
380
381
382
383
384 u8 status;
385 u8 error;
386 u8 lbal;
387 u8 lbam;
388 u8 lbah;
389 u8 device;
390 u8 lbal_exp;
391 u8 lbam_exp;
392 u8 lbah_exp;
393 u8 _r_a;
394 u8 sector_count;
395 u8 sector_count_exp;
396 u8 _r_b;
397 u8 e_status;
398 u8 _r_c[2];
399 u8 transfer_count;
400} __attribute__ ((packed));
401
402
403
404
405
406struct sata_completion_resp {
407 __le32 tag;
408 __le32 status;
409 __le32 param;
410 u32 sata_resp[12];
411} __attribute__((packed, aligned(4)));
412
413
414
415
416
417
418
419struct hw_event_resp {
420 __le32 lr_status_evt_portid;
421 __le32 evt_param;
422 __le32 phyid_npip_portstate;
423 struct sas_identify_frame sas_identify;
424 struct dev_to_host_fis sata_fis;
425} __attribute__((packed, aligned(4)));
426
427
428
429
430
431struct thermal_hw_event {
432 __le32 thermal_event;
433 __le32 rht_lht;
434} __attribute__((packed, aligned(4)));
435
436
437
438
439
440
441struct reg_dev_req {
442 __le32 tag;
443 __le32 phyid_portid;
444 __le32 dtype_dlr_mcn_ir_retry;
445 __le32 firstburstsize_ITNexustimeout;
446 u8 sas_addr[SAS_ADDR_SIZE];
447 __le32 upper_device_id;
448 u32 reserved[24];
449} __attribute__((packed, aligned(4)));
450
451
452
453
454
455
456
457struct dereg_dev_req {
458 __le32 tag;
459 __le32 device_id;
460 u32 reserved[29];
461} __attribute__((packed, aligned(4)));
462
463
464
465
466
467struct dev_reg_resp {
468 __le32 tag;
469 __le32 status;
470 __le32 device_id;
471 u32 reserved[12];
472} __attribute__((packed, aligned(4)));
473
474
475
476
477
478struct local_phy_ctl_req {
479 __le32 tag;
480 __le32 phyop_phyid;
481 u32 reserved1[29];
482} __attribute__((packed, aligned(4)));
483
484
485
486
487
488 struct local_phy_ctl_resp {
489 __le32 tag;
490 __le32 phyop_phyid;
491 __le32 status;
492 u32 reserved[12];
493} __attribute__((packed, aligned(4)));
494
495#define OP_BITS 0x0000FF00
496#define ID_BITS 0x000000FF
497
498
499
500
501
502
503struct port_ctl_req {
504 __le32 tag;
505 __le32 portop_portid;
506 __le32 param0;
507 __le32 param1;
508 u32 reserved1[27];
509} __attribute__((packed, aligned(4)));
510
511
512
513
514
515struct hw_event_ack_req {
516 __le32 tag;
517 __le32 phyid_sea_portid;
518 __le32 param0;
519 __le32 param1;
520 u32 reserved1[27];
521} __attribute__((packed, aligned(4)));
522
523
524
525
526
527struct phy_start_resp {
528 __le32 tag;
529 __le32 status;
530 __le32 phyid;
531 u32 reserved[12];
532} __attribute__((packed, aligned(4)));
533
534
535
536
537
538struct phy_stop_resp {
539 __le32 tag;
540 __le32 status;
541 __le32 phyid;
542 u32 reserved[12];
543} __attribute__((packed, aligned(4)));
544
545
546
547
548
549struct ssp_completion_resp {
550 __le32 tag;
551 __le32 status;
552 __le32 param;
553 __le32 ssptag_rescv_rescpad;
554 struct ssp_response_iu ssp_resp_iu;
555 __le32 residual_count;
556} __attribute__((packed, aligned(4)));
557
558#define SSP_RESCV_BIT 0x00010000
559
560
561
562
563
564struct sata_event_resp {
565 __le32 tag;
566 __le32 event;
567 __le32 port_id;
568 __le32 device_id;
569 u32 reserved;
570 __le32 event_param0;
571 __le32 event_param1;
572 __le32 sata_addr_h32;
573 __le32 sata_addr_l32;
574 __le32 e_udt1_udt0_crc;
575 __le32 e_udt5_udt4_udt3_udt2;
576 __le32 a_udt1_udt0_crc;
577 __le32 a_udt5_udt4_udt3_udt2;
578 __le32 hwdevid_diferr;
579 __le32 err_framelen_byteoffset;
580 __le32 err_dataframe;
581} __attribute__((packed, aligned(4)));
582
583
584
585
586
587struct ssp_event_resp {
588 __le32 tag;
589 __le32 event;
590 __le32 port_id;
591 __le32 device_id;
592 __le32 ssp_tag;
593 __le32 event_param0;
594 __le32 event_param1;
595 __le32 sas_addr_h32;
596 __le32 sas_addr_l32;
597 __le32 e_udt1_udt0_crc;
598 __le32 e_udt5_udt4_udt3_udt2;
599 __le32 a_udt1_udt0_crc;
600 __le32 a_udt5_udt4_udt3_udt2;
601 __le32 hwdevid_diferr;
602 __le32 err_framelen_byteoffset;
603 __le32 err_dataframe;
604} __attribute__((packed, aligned(4)));
605
606
607
608
609
610struct general_event_resp {
611 __le32 status;
612 __le32 inb_IOMB_payload[14];
613} __attribute__((packed, aligned(4)));
614
615#define GENERAL_EVENT_PAYLOAD 14
616#define OPCODE_BITS 0x00000fff
617
618
619
620
621
622struct smp_req {
623 __le32 tag;
624 __le32 device_id;
625 __le32 len_ip_ir;
626
627
628
629
630
631 u8 smp_req16[16];
632 union {
633 u8 smp_req[32];
634 struct {
635 __le64 long_req_addr;
636 __le32 long_req_size;
637 u32 _r_a;
638 __le64 long_resp_addr;
639 __le32 long_resp_size;
640 u32 _r_b;
641 } long_smp_req;
642 };
643 __le32 rsvd[16];
644} __attribute__((packed, aligned(4)));
645
646
647
648
649struct smp_completion_resp {
650 __le32 tag;
651 __le32 status;
652 __le32 param;
653 u8 _r_a[252];
654} __attribute__((packed, aligned(4)));
655
656
657
658
659
660struct task_abort_req {
661 __le32 tag;
662 __le32 device_id;
663 __le32 tag_to_abort;
664 __le32 abort_all;
665 u32 reserved[27];
666} __attribute__((packed, aligned(4)));
667
668
669#define ABORT_MASK 0x3
670#define ABORT_SINGLE 0x0
671#define ABORT_ALL 0x1
672
673
674
675
676
677struct task_abort_resp {
678 __le32 tag;
679 __le32 status;
680 __le32 scp;
681 u32 reserved[12];
682} __attribute__((packed, aligned(4)));
683
684
685
686
687
688struct sas_diag_start_end_req {
689 __le32 tag;
690 __le32 operation_phyid;
691 u32 reserved[29];
692} __attribute__((packed, aligned(4)));
693
694
695
696
697
698struct sas_diag_execute_req {
699 __le32 tag;
700 __le32 cmdtype_cmddesc_phyid;
701 __le32 pat1_pat2;
702 __le32 threshold;
703 __le32 codepat_errmsk;
704 __le32 pmon;
705 __le32 pERF1CTL;
706 u32 reserved[24];
707} __attribute__((packed, aligned(4)));
708
709#define SAS_DIAG_PARAM_BYTES 24
710
711
712
713
714
715struct set_dev_state_req {
716 __le32 tag;
717 __le32 device_id;
718 __le32 nds;
719 u32 reserved[28];
720} __attribute__((packed, aligned(4)));
721
722
723
724
725
726
727
728struct sata_start_req {
729 __le32 tag;
730 __le32 device_id;
731 __le32 data_len;
732 __le32 ncqtag_atap_dir_m_dad;
733 struct host_to_dev_fis sata_fis;
734 u32 reserved1;
735 u32 reserved2;
736
737 u32 addr_low;
738 u32 addr_high;
739 __le32 len;
740
741 __le32 esgl;
742 __le32 atapi_scsi_cdb[4];
743
744 __le32 key_index_mode;
745 __le32 sector_cnt_enss;
746 __le32 keytagl;
747 __le32 keytagh;
748 __le32 twk_val0;
749 __le32 twk_val1;
750 __le32 twk_val2;
751 __le32 twk_val3;
752 __le32 enc_addr_low;
753 __le32 enc_addr_high;
754 __le32 enc_len;
755 __le32 enc_esgl;
756} __attribute__((packed, aligned(4)));
757
758
759
760
761
762struct ssp_ini_tm_start_req {
763 __le32 tag;
764 __le32 device_id;
765 __le32 relate_tag;
766 __le32 tmf;
767 u8 lun[8];
768 __le32 ds_ads_m;
769 u32 reserved[24];
770} __attribute__((packed, aligned(4)));
771
772struct ssp_info_unit {
773 u8 lun[8];
774 u8 reserved1;
775 u8 efb_prio_attr;
776
777
778
779 u8 reserved2;
780 u8 additional_cdb_len;
781
782
783 u8 cdb[16];
784} __attribute__((packed, aligned(4)));
785
786
787
788
789
790
791struct ssp_ini_io_start_req {
792 __le32 tag;
793 __le32 device_id;
794 __le32 data_len;
795 __le32 dad_dir_m_tlr;
796 struct ssp_info_unit ssp_iu;
797 __le32 addr_low;
798
799 __le32 addr_high;
800
801 __le32 len;
802
803 __le32 esgl;
804
805
806 u8 udt[12];
807 __le32 sectcnt_ios;
808 __le32 key_cmode;
809 __le32 ks_enss;
810 __le32 keytagl;
811 __le32 keytagh;
812 __le32 twk_val0;
813 __le32 twk_val1;
814 __le32 twk_val2;
815 __le32 twk_val3;
816 __le32 enc_addr_low;
817 __le32 enc_addr_high;
818 __le32 enc_len;
819 __le32 enc_esgl;
820} __attribute__((packed, aligned(4)));
821
822
823
824
825
826struct ssp_dif_enc_io_req {
827 __le32 tag;
828 __le32 device_id;
829 __le32 data_len;
830 __le32 dirMTlr;
831 __le32 sspiu0;
832 __le32 sspiu1;
833 __le32 sspiu2;
834 __le32 sspiu3;
835 __le32 sspiu4;
836 __le32 sspiu5;
837 __le32 sspiu6;
838 __le32 epl_des;
839 __le32 dpl_desl_ndplr;
840 __le32 dpl_desh;
841 __le32 uum_uuv_bss_difbits;
842 u8 udt[12];
843 __le32 sectcnt_ios;
844 __le32 key_cmode;
845 __le32 ks_enss;
846 __le32 keytagl;
847 __le32 keytagh;
848 __le32 twk_val0;
849 __le32 twk_val1;
850 __le32 twk_val2;
851 __le32 twk_val3;
852 __le32 addr_low;
853 __le32 addr_high;
854 __le32 len;
855 __le32 esgl;
856} __attribute__((packed, aligned(4)));
857
858
859
860
861
862struct fw_flash_Update_req {
863 __le32 tag;
864 __le32 cur_image_offset;
865 __le32 cur_image_len;
866 __le32 total_image_len;
867 u32 reserved0[7];
868 __le32 sgl_addr_lo;
869 __le32 sgl_addr_hi;
870 __le32 len;
871 __le32 ext_reserved;
872 u32 reserved1[16];
873} __attribute__((packed, aligned(4)));
874
875#define FWFLASH_IOMB_RESERVED_LEN 0x07
876
877
878
879
880
881 struct fw_flash_Update_resp {
882 __le32 tag;
883 __le32 status;
884 u32 reserved[13];
885} __attribute__((packed, aligned(4)));
886
887
888
889
890
891struct get_nvm_data_req {
892 __le32 tag;
893 __le32 len_ir_vpdd;
894 __le32 vpd_offset;
895 u32 reserved[8];
896 __le32 resp_addr_lo;
897 __le32 resp_addr_hi;
898 __le32 resp_len;
899 u32 reserved1[17];
900} __attribute__((packed, aligned(4)));
901
902struct set_nvm_data_req {
903 __le32 tag;
904 __le32 len_ir_vpdd;
905 __le32 vpd_offset;
906 u32 reserved[8];
907 __le32 resp_addr_lo;
908 __le32 resp_addr_hi;
909 __le32 resp_len;
910 u32 reserved1[17];
911} __attribute__((packed, aligned(4)));
912
913
914
915
916
917struct set_ctrl_cfg_req {
918 __le32 tag;
919 __le32 cfg_pg[14];
920 u32 reserved[16];
921} __attribute__((packed, aligned(4)));
922
923
924
925
926
927struct get_ctrl_cfg_req {
928 __le32 tag;
929 __le32 pgcd;
930 __le32 int_vec;
931 u32 reserved[28];
932} __attribute__((packed, aligned(4)));
933
934
935
936
937
938struct kek_mgmt_req {
939 __le32 tag;
940 __le32 new_curidx_ksop;
941 u32 reserved;
942 __le32 kblob[12];
943 u32 reserved1[16];
944} __attribute__((packed, aligned(4)));
945
946
947
948
949
950struct dek_mgmt_req {
951 __le32 tag;
952 __le32 kidx_dsop;
953 __le32 dekidx;
954 __le32 addr_l;
955 __le32 addr_h;
956 __le32 nent;
957 __le32 dbf_tblsize;
958 u32 reserved[24];
959} __attribute__((packed, aligned(4)));
960
961
962
963
964
965struct set_phy_profile_req {
966 __le32 tag;
967 __le32 ppc_phyid;
968 u32 reserved[29];
969} __attribute__((packed, aligned(4)));
970
971
972
973
974
975struct get_phy_profile_req {
976 __le32 tag;
977 __le32 ppc_phyid;
978 __le32 profile[29];
979} __attribute__((packed, aligned(4)));
980
981
982
983
984
985struct ext_flash_partition_req {
986 __le32 tag;
987 __le32 cmd;
988 __le32 offset;
989 __le32 len;
990 u32 reserved[7];
991 __le32 addr_low;
992 __le32 addr_high;
993 __le32 len1;
994 __le32 ext;
995 u32 reserved1[16];
996} __attribute__((packed, aligned(4)));
997
998#define TWI_DEVICE 0x0
999#define C_SEEPROM 0x1
1000#define VPD_FLASH 0x4
1001#define AAP1_RDUMP 0x5
1002#define IOP_RDUMP 0x6
1003#define EXPAN_ROM 0x7
1004
1005#define IPMode 0x80000000
1006#define NVMD_TYPE 0x0000000F
1007#define NVMD_STAT 0x0000FFFF
1008#define NVMD_LEN 0xFF000000
1009
1010
1011
1012
1013struct get_nvm_data_resp {
1014 __le32 tag;
1015 __le32 ir_tda_bn_dps_das_nvm;
1016 __le32 dlen_status;
1017 __le32 nvm_data[12];
1018} __attribute__((packed, aligned(4)));
1019
1020
1021
1022
1023
1024
1025struct sas_diag_start_end_resp {
1026 __le32 tag;
1027 __le32 status;
1028 u32 reserved[13];
1029} __attribute__((packed, aligned(4)));
1030
1031
1032
1033
1034
1035
1036struct sas_diag_execute_resp {
1037 __le32 tag;
1038 __le32 cmdtype_cmddesc_phyid;
1039 __le32 Status;
1040 __le32 ReportData;
1041 u32 reserved[11];
1042} __attribute__((packed, aligned(4)));
1043
1044
1045
1046
1047
1048
1049struct set_dev_state_resp {
1050 __le32 tag;
1051 __le32 status;
1052 __le32 device_id;
1053 __le32 pds_nds;
1054 u32 reserved[11];
1055} __attribute__((packed, aligned(4)));
1056
1057
1058
1059
1060
1061
1062struct set_ctrl_cfg_resp {
1063 __le32 tag;
1064 __le32 status;
1065 __le32 err_qlfr_pgcd;
1066 u32 reserved[12];
1067} __attribute__((packed, aligned(4)));
1068
1069struct get_ctrl_cfg_resp {
1070 __le32 tag;
1071 __le32 status;
1072 __le32 err_qlfr;
1073 __le32 confg_page[12];
1074} __attribute__((packed, aligned(4)));
1075
1076struct kek_mgmt_resp {
1077 __le32 tag;
1078 __le32 status;
1079 __le32 kidx_new_curr_ksop;
1080 __le32 err_qlfr;
1081 u32 reserved[11];
1082} __attribute__((packed, aligned(4)));
1083
1084struct dek_mgmt_resp {
1085 __le32 tag;
1086 __le32 status;
1087 __le32 kekidx_tbls_dsop;
1088 __le32 dekidx;
1089 __le32 err_qlfr;
1090 u32 reserved[10];
1091} __attribute__((packed, aligned(4)));
1092
1093struct get_phy_profile_resp {
1094 __le32 tag;
1095 __le32 status;
1096 __le32 ppc_phyid;
1097 __le32 ppc_specific_rsp[12];
1098} __attribute__((packed, aligned(4)));
1099
1100struct flash_op_ext_resp {
1101 __le32 tag;
1102 __le32 cmd;
1103 __le32 status;
1104 __le32 epart_size;
1105 __le32 epart_sect_size;
1106 u32 reserved[10];
1107} __attribute__((packed, aligned(4)));
1108
1109struct set_phy_profile_resp {
1110 __le32 tag;
1111 __le32 status;
1112 __le32 ppc_phyid;
1113 __le32 ppc_specific_rsp[12];
1114} __attribute__((packed, aligned(4)));
1115
1116struct ssp_coalesced_comp_resp {
1117 __le32 coal_cnt;
1118 __le32 tag0;
1119 __le32 ssp_tag0;
1120 __le32 tag1;
1121 __le32 ssp_tag1;
1122 __le32 add_tag_ssp_tag[10];
1123} __attribute__((packed, aligned(4)));
1124
1125
1126
1127
1128
1129
1130struct SASProtocolTimerConfig {
1131 __le32 pageCode;
1132 __le32 MST_MSI;
1133 __le32 STP_SSP_MCT_TMO;
1134 __le32 STP_FRM_TMO;
1135 __le32 STP_IDLE_TMO;
1136 __le32 OPNRJT_RTRY_INTVL;
1137 __le32 Data_Cmd_OPNRJT_RTRY_TMO;
1138 __le32 Data_Cmd_OPNRJT_RTRY_THR;
1139 __le32 MAX_AIP;
1140} __attribute__((packed, aligned(4)));
1141
1142typedef struct SASProtocolTimerConfig SASProtocolTimerConfig_t;
1143
1144#define NDS_BITS 0x0F
1145#define PDS_BITS 0xF0
1146
1147
1148
1149
1150
1151#define HW_EVENT_RESET_START 0x01
1152#define HW_EVENT_CHIP_RESET_COMPLETE 0x02
1153#define HW_EVENT_PHY_STOP_STATUS 0x03
1154#define HW_EVENT_SAS_PHY_UP 0x04
1155#define HW_EVENT_SATA_PHY_UP 0x05
1156#define HW_EVENT_SATA_SPINUP_HOLD 0x06
1157#define HW_EVENT_PHY_DOWN 0x07
1158#define HW_EVENT_PORT_INVALID 0x08
1159#define HW_EVENT_BROADCAST_CHANGE 0x09
1160#define HW_EVENT_PHY_ERROR 0x0A
1161#define HW_EVENT_BROADCAST_SES 0x0B
1162#define HW_EVENT_INBOUND_CRC_ERROR 0x0C
1163#define HW_EVENT_HARD_RESET_RECEIVED 0x0D
1164#define HW_EVENT_MALFUNCTION 0x0E
1165#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1166#define HW_EVENT_BROADCAST_EXP 0x10
1167#define HW_EVENT_PHY_START_STATUS 0x11
1168#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
1169#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
1170#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
1171#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
1172#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
1173#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1174#define HW_EVENT_PORT_RECOVER 0x18
1175#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1176#define HW_EVENT_PORT_RESET_COMPLETE 0x20
1177#define EVENT_BROADCAST_ASYNCH_EVENT 0x21
1178
1179
1180#define PORT_NOT_ESTABLISHED 0x00
1181#define PORT_VALID 0x01
1182#define PORT_LOSTCOMM 0x02
1183#define PORT_IN_RESET 0x04
1184#define PORT_3RD_PARTY_RESET 0x07
1185#define PORT_INVALID 0x08
1186
1187
1188
1189
1190
1191#define IO_SUCCESS 0x00
1192#define IO_ABORTED 0x01
1193#define IO_OVERFLOW 0x02
1194#define IO_UNDERFLOW 0x03
1195#define IO_FAILED 0x04
1196#define IO_ABORT_RESET 0x05
1197#define IO_NOT_VALID 0x06
1198#define IO_NO_DEVICE 0x07
1199#define IO_ILLEGAL_PARAMETER 0x08
1200#define IO_LINK_FAILURE 0x09
1201#define IO_PROG_ERROR 0x0A
1202
1203#define IO_EDC_IN_ERROR 0x0B
1204#define IO_EDC_OUT_ERROR 0x0C
1205#define IO_ERROR_HW_TIMEOUT 0x0D
1206#define IO_XFER_ERROR_BREAK 0x0E
1207#define IO_XFER_ERROR_PHY_NOT_READY 0x0F
1208#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
1209#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
1210#define IO_OPEN_CNX_ERROR_BREAK 0x12
1211#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
1212#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
1213#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1214#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
1215#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
1216
1217#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
1218#define IO_XFER_ERROR_NAK_RECEIVED 0x19
1219#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
1220#define IO_XFER_ERROR_PEER_ABORTED 0x1B
1221#define IO_XFER_ERROR_RX_FRAME 0x1C
1222#define IO_XFER_ERROR_DMA 0x1D
1223#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
1224#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
1225#define IO_XFER_ERROR_SATA 0x20
1226
1227
1228#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
1229#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
1230#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
1231#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
1232
1233#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
1234#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
1235#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
1236#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
1237#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
1238
1239
1240#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
1241#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1242
1243#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
1244#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
1245#define IO_XFER_CMD_FRAME_ISSUED 0x36
1246#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
1247#define IO_PORT_IN_RESET 0x38
1248#define IO_DS_NON_OPERATIONAL 0x39
1249#define IO_DS_IN_RECOVERY 0x3A
1250#define IO_TM_TAG_NOT_FOUND 0x3B
1251#define IO_XFER_PIO_SETUP_ERROR 0x3C
1252#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
1253#define IO_DS_IN_ERROR 0x3E
1254#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
1255#define IO_ABORT_IN_PROGRESS 0x40
1256#define IO_ABORT_DELAYED 0x41
1257#define IO_INVALID_LENGTH 0x42
1258
1259
1260
1261#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43
1262#define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44
1263#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45
1264#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46
1265#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47
1266#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1267#define IO_DS_INVALID 0x49
1268
1269#define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52
1270#define IO_XFER_DMA_ACTIVATE_TIMEOUT 0x53
1271#define IO_XFER_ERROR_INTERNAL_CRC_ERROR 0x54
1272#define MPI_IO_RQE_BUSY_FULL 0x55
1273#define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56
1274#define IO_XFER_ERROR_INVALID_SSP_RSP_FRAME 0x57
1275#define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58
1276
1277#define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1278#define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024
1279
1280#define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040
1281
1282
1283
1284
1285
1286#define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041
1287#define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042
1288
1289
1290
1291
1292#define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043
1293
1294
1295#define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044
1296
1297
1298#define IO_XFR_ERROR_INTERNAL_RAM 0x2045
1299
1300
1301
1302
1303
1304#define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1305
1306
1307#define IO_XFR_ERROR_DIF_MISMATCH 0x3000
1308#define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1309#define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1310#define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1311
1312
1313#define OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1314#define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1315#define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1316#define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1317#define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1318#define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022
1319#define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023
1320
1321
1322
1323
1324
1325
1326#define IO_ERROR_UNKNOWN_GENERIC 0x2023
1327
1328
1329
1330#define SPCv_MSGU_CFG_TABLE_UPDATE 0x001
1331#define SPCv_MSGU_CFG_TABLE_RESET 0x002
1332#define SPCv_MSGU_CFG_TABLE_FREEZE 0x004
1333#define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x008
1334#define MSGU_IBDB_SET 0x00
1335#define MSGU_HOST_INT_STATUS 0x08
1336#define MSGU_HOST_INT_MASK 0x0C
1337#define MSGU_IOPIB_INT_STATUS 0x18
1338#define MSGU_IOPIB_INT_MASK 0x1C
1339#define MSGU_IBDB_CLEAR 0x20
1340
1341#define MSGU_MSGU_CONTROL 0x24
1342#define MSGU_ODR 0x20
1343#define MSGU_ODCR 0x28
1344
1345#define MSGU_ODMR 0x30
1346#define MSGU_ODMR_U 0x34
1347#define MSGU_ODMR_CLR 0x38
1348#define MSGU_ODMR_CLR_U 0x3C
1349#define MSGU_OD_RSVD 0x40
1350
1351#define MSGU_SCRATCH_PAD_0 0x44
1352#define MSGU_SCRATCH_PAD_1 0x48
1353#define MSGU_SCRATCH_PAD_2 0x4C
1354#define MSGU_SCRATCH_PAD_3 0x50
1355#define MSGU_HOST_SCRATCH_PAD_0 0x54
1356#define MSGU_HOST_SCRATCH_PAD_1 0x58
1357#define MSGU_HOST_SCRATCH_PAD_2 0x5C
1358#define MSGU_HOST_SCRATCH_PAD_3 0x60
1359#define MSGU_HOST_SCRATCH_PAD_4 0x64
1360#define MSGU_HOST_SCRATCH_PAD_5 0x68
1361#define MSGU_HOST_SCRATCH_PAD_6 0x6C
1362#define MSGU_HOST_SCRATCH_PAD_7 0x70
1363
1364
1365#define ODMR_MASK_ALL 0xFFFFFFFF
1366
1367#define ODMR_CLEAR_ALL 0
1368
1369
1370#define ODCR_CLEAR_ALL 0xFFFFFFFF
1371
1372
1373#define MSIX_TABLE_OFFSET 0x2000
1374#define MSIX_TABLE_ELEMENT_SIZE 0x10
1375#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
1376#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + \
1377 MSIX_INTERRUPT_CONTROL_OFFSET)
1378#define MSIX_INTERRUPT_DISABLE 0x1
1379#define MSIX_INTERRUPT_ENABLE 0x0
1380
1381
1382#define SCRATCH_PAD_RAAE_READY 0x3
1383#define SCRATCH_PAD_ILA_READY 0xC
1384#define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
1385#define SCRATCH_PAD_IOP0_READY 0xC00
1386#define SCRATCH_PAD_IOP1_READY 0x3000
1387
1388
1389#define SCRATCH_PAD1_BOOTSTATE_MASK 0x70
1390#define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0
1391#define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10
1392#define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20
1393#define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30
1394#define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40
1395#define SCRATCH_PAD1_BOOTSTATE_R1 0x50
1396#define SCRATCH_PAD1_BOOTSTATE_R2 0x60
1397#define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70
1398
1399
1400#define SCRATCH_PAD2_POR 0x00
1401#define SCRATCH_PAD2_SFR 0x01
1402#define SCRATCH_PAD2_ERR 0x02
1403#define SCRATCH_PAD2_RDY 0x03
1404#define SCRATCH_PAD2_FWRDY_RST 0x04
1405#define SCRATCH_PAD2_IOPRDY_RST 0x08
1406#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4
1407
1408#define SCRATCH_PAD2_RESERVED 0x000003FC
1409
1410
1411#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00
1412#define SCRATCH_PAD_STATE_MASK 0x00000003
1413
1414
1415#define MAIN_SIGNATURE_OFFSET 0x00
1416#define MAIN_INTERFACE_REVISION 0x04
1417#define MAIN_FW_REVISION 0x08
1418#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C
1419#define MAIN_MAX_SGL_OFFSET 0x10
1420#define MAIN_CNTRL_CAP_OFFSET 0x14
1421#define MAIN_GST_OFFSET 0x18
1422#define MAIN_IBQ_OFFSET 0x1C
1423#define MAIN_OBQ_OFFSET 0x20
1424#define MAIN_IQNPPD_HPPD_OFFSET 0x24
1425
1426
1427#define MAIN_EVENT_CRC_CHECK 0x48
1428#define MAIN_EVENT_LOG_ADDR_HI 0x50
1429#define MAIN_EVENT_LOG_ADDR_LO 0x54
1430#define MAIN_EVENT_LOG_BUFF_SIZE 0x58
1431#define MAIN_EVENT_LOG_OPTION 0x5C
1432#define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60
1433#define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64
1434#define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68
1435#define MAIN_PCS_EVENT_LOG_OPTION 0x6C
1436#define MAIN_FATAL_ERROR_INTERRUPT 0x70
1437#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74
1438#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78
1439#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C
1440#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80
1441#define MAIN_GPIO_LED_FLAGS_OFFSET 0x84
1442#define MAIN_ANALOG_SETUP_OFFSET 0x88
1443
1444#define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C
1445#define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90
1446#define MAIN_PORT_RECOVERY_TIMER 0x94
1447#define MAIN_INT_REASSERTION_DELAY 0x98
1448#define MAIN_MPI_ILA_RELEASE_TYPE 0xA4
1449#define MAIN_MPI_INACTIVE_FW_VERSION 0XB0
1450
1451
1452#define GST_GSTLEN_MPIS_OFFSET 0x00
1453#define GST_IQ_FREEZE_STATE0_OFFSET 0x04
1454#define GST_IQ_FREEZE_STATE1_OFFSET 0x08
1455#define GST_MSGUTCNT_OFFSET 0x0C
1456#define GST_IOPTCNT_OFFSET 0x10
1457
1458#define GST_GPIO_INPUT_VAL 0x38
1459
1460#define GST_RERRINFO_OFFSET0 0x44
1461#define GST_RERRINFO_OFFSET1 0x48
1462#define GST_RERRINFO_OFFSET2 0x4c
1463#define GST_RERRINFO_OFFSET3 0x50
1464#define GST_RERRINFO_OFFSET4 0x54
1465#define GST_RERRINFO_OFFSET5 0x58
1466#define GST_RERRINFO_OFFSET6 0x5c
1467#define GST_RERRINFO_OFFSET7 0x60
1468
1469
1470#define GST_MPI_STATE_UNINIT 0x00
1471#define GST_MPI_STATE_INIT 0x01
1472#define GST_MPI_STATE_TERMINATION 0x02
1473#define GST_MPI_STATE_ERROR 0x03
1474#define GST_MPI_STATE_MASK 0x07
1475
1476
1477
1478#define PSPA_PHYSTATE0_OFFSET 0x00
1479#define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04
1480#define PSPA_PHYSTATE1_OFFSET 0x08
1481#define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C
1482#define PSPA_PHYSTATE2_OFFSET 0x10
1483#define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14
1484#define PSPA_PHYSTATE3_OFFSET 0x18
1485#define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C
1486#define PSPA_PHYSTATE4_OFFSET 0x20
1487#define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24
1488#define PSPA_PHYSTATE5_OFFSET 0x28
1489#define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C
1490#define PSPA_PHYSTATE6_OFFSET 0x30
1491#define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34
1492#define PSPA_PHYSTATE7_OFFSET 0x38
1493#define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C
1494#define PSPA_PHYSTATE8_OFFSET 0x40
1495#define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44
1496#define PSPA_PHYSTATE9_OFFSET 0x48
1497#define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C
1498#define PSPA_PHYSTATE10_OFFSET 0x50
1499#define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54
1500#define PSPA_PHYSTATE11_OFFSET 0x58
1501#define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C
1502#define PSPA_PHYSTATE12_OFFSET 0x60
1503#define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64
1504#define PSPA_PHYSTATE13_OFFSET 0x68
1505#define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c
1506#define PSPA_PHYSTATE14_OFFSET 0x70
1507#define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74
1508#define PSPA_PHYSTATE15_OFFSET 0x78
1509#define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c
1510
1511
1512
1513#define IB_PROPERITY_OFFSET 0x00
1514#define IB_BASE_ADDR_HI_OFFSET 0x04
1515#define IB_BASE_ADDR_LO_OFFSET 0x08
1516#define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
1517#define IB_CI_BASE_ADDR_LO_OFFSET 0x10
1518#define IB_PIPCI_BAR 0x14
1519#define IB_PIPCI_BAR_OFFSET 0x18
1520#define IB_RESERVED_OFFSET 0x1C
1521
1522
1523#define OB_PROPERITY_OFFSET 0x00
1524#define OB_BASE_ADDR_HI_OFFSET 0x04
1525#define OB_BASE_ADDR_LO_OFFSET 0x08
1526#define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
1527#define OB_PI_BASE_ADDR_LO_OFFSET 0x10
1528#define OB_CIPCI_BAR 0x14
1529#define OB_CIPCI_BAR_OFFSET 0x18
1530#define OB_INTERRUPT_COALES_OFFSET 0x1C
1531#define OB_DYNAMIC_COALES_OFFSET 0x20
1532#define OB_PROPERTY_INT_ENABLE 0x40000000
1533
1534#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
1535#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
1536
1537#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
1538#define PCIE_EVENT_INTERRUPT 0x003044
1539#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
1540#define PCIE_ERROR_INTERRUPT 0x00304C
1541
1542
1543#define SPC_REG_SOFT_RESET 0x00001000
1544#define SPCv_NORMAL_RESET_VALUE 0x1
1545
1546#define SPCv_SOFT_RESET_READ_MASK 0xC0
1547#define SPCv_SOFT_RESET_NO_RESET 0x0
1548#define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40
1549#define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80
1550#define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0
1551
1552
1553#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
1554
1555
1556
1557#define SPC_REG_RESET 0x000000
1558
1559
1560#define SPC_REG_RESET_OSSP 0x00000001
1561#define SPC_REG_RESET_RAAE 0x00000002
1562#define SPC_REG_RESET_PCS_SPBC 0x00000004
1563#define SPC_REG_RESET_PCS_IOP_SS 0x00000008
1564#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
1565#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
1566#define SPC_REG_RESET_PCS_LM 0x00000040
1567#define SPC_REG_RESET_PCS 0x00000080
1568#define SPC_REG_RESET_GSM 0x00000100
1569#define SPC_REG_RESET_DDR2 0x00010000
1570#define SPC_REG_RESET_BDMA_CORE 0x00020000
1571#define SPC_REG_RESET_BDMA_SXCBI 0x00040000
1572#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
1573#define SPC_REG_RESET_PCIE_PWR 0x00100000
1574#define SPC_REG_RESET_PCIE_SFT 0x00200000
1575#define SPC_REG_RESET_PCS_SXCBI 0x00400000
1576#define SPC_REG_RESET_LMS_SXCBI 0x00800000
1577#define SPC_REG_RESET_PMIC_SXCBI 0x01000000
1578#define SPC_REG_RESET_PMIC_CORE 0x02000000
1579#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
1580#define SPC_REG_RESET_DEVICE 0x80000000
1581
1582
1583#define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010
1584
1585#define MBIC_AAP1_ADDR_BASE 0x060000
1586#define MBIC_IOP_ADDR_BASE 0x070000
1587#define GSM_ADDR_BASE 0x0700000
1588
1589#define GSM_CONFIG_RESET 0x00000000
1590#define RAM_ECC_DB_ERR 0x00000018
1591#define GSM_READ_ADDR_PARITY_INDIC 0x00000058
1592#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
1593#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
1594#define GSM_READ_ADDR_PARITY_CHECK 0x00000038
1595#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1596#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1597
1598#define RB6_ACCESS_REG 0x6A0000
1599#define HDAC_EXEC_CMD 0x0002
1600#define HDA_C_PA 0xcb
1601#define HDA_SEQ_ID_BITS 0x00ff0000
1602#define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1603#define HDA_GSM_CMD_OFFSET_BITS 0x42C0
1604#define HDA_GSM_RSP_OFFSET_BITS 0x42E0
1605
1606#define MBIC_AAP1_ADDR_BASE 0x060000
1607#define MBIC_IOP_ADDR_BASE 0x070000
1608#define GSM_ADDR_BASE 0x0700000
1609#define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1610#define GSM_CONFIG_RESET_VALUE 0x00003b00
1611#define GPIO_ADDR_BASE 0x00090000
1612#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1613
1614
1615#define SPC_RB6_OFFSET 0x80C0
1616
1617#define RB6_MAGIC_NUMBER_RST 0x1234
1618
1619
1620#define DEVREG_SUCCESS 0x00
1621#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1622#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1623#define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1624#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1625#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1626#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1627#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1628
1629
1630#define MEMBASE_II_SHIFT_REGISTER 0x1010
1631#endif
1632