LXR linux/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css

   1/*
   2 * Support for Intel Camera Imaging ISP subsystem.
   3 * Copyright (c) 2010-2016, Intel Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms and conditions of the GNU General Public License,
   7 * version 2, as published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 */
  14
  15#include <linux/kernel.h>
  16
  17#include "dma.h"
  18
  19#include "assert_support.h"
  20
  21#ifndef __INLINE_DMA__
  22#include "dma_private.h"
  23#endif /* __INLINE_DMA__ */
  24
  25void dma_get_state(const dma_ID_t ID, dma_state_t *state)
  26{
  27        int                     i;
  28        hrt_data        tmp;
  29
  30        assert(ID < N_DMA_ID);
  31        assert(state != NULL);
  32
  33        tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX);
  34        //reg  [3:0] : flags error [3], stall, run, idle [0]
  35        //reg  [9:4] : command
  36        //reg[14:10] : channel
  37        //reg [23:15] : param
  38        state->fsm_command_idle = tmp & 0x1;
  39        state->fsm_command_run = tmp & 0x2;
  40        state->fsm_command_stalling = tmp & 0x4;
  41        state->fsm_command_error    = tmp & 0x8;
  42        state->last_command_channel = (tmp>>10 & 0x1F);
  43        state->last_command_param =  (tmp>>15 & 0x0F);
  44        tmp = (tmp>>4) & 0x3F;
  45/* state->last_command = (dma_commands_t)tmp; */
  46/* if the enumerator is made non-linear */
  47        /* AM: the list below does not cover all the cases*/
  48        /*  and these are not correct */
  49        /* therefore for just dumpinmg this command*/
  50        state->last_command = tmp;
  51
  52/*
  53        if (tmp == 0)
  54                state->last_command = DMA_COMMAND_READ;
  55        if (tmp == 1)
  56                state->last_command = DMA_COMMAND_WRITE;
  57        if (tmp == 2)
  58                state->last_command = DMA_COMMAND_SET_CHANNEL;
  59        if (tmp == 3)
  60                state->last_command = DMA_COMMAND_SET_PARAM;
  61        if (tmp == 4)
  62                state->last_command = DMA_COMMAND_READ_SPECIFIC;
  63        if (tmp == 5)
  64                state->last_command = DMA_COMMAND_WRITE_SPECIFIC;
  65        if (tmp == 8)
  66                state->last_command = DMA_COMMAND_INIT;
  67        if (tmp == 12)
  68                state->last_command = DMA_COMMAND_INIT_SPECIFIC;
  69        if (tmp == 15)
  70                state->last_command = DMA_COMMAND_RST;
  71*/
  72
  73/* No sub-fields, idx = 0 */
  74        state->current_command = dma_reg_load(ID,
  75                DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_CMD_IDX));
  76        state->current_addr_a = dma_reg_load(ID,
  77                DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_A_IDX));
  78        state->current_addr_b = dma_reg_load(ID,
  79                DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_B_IDX));
  80
  81        tmp =  dma_reg_load(ID,
  82                DMA_CG_INFO_REG_IDX(
  83                _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX,
  84                _DMA_FSM_GROUP_FSM_CTRL_IDX));
  85        state->fsm_ctrl_idle = tmp & 0x1;
  86        state->fsm_ctrl_run = tmp & 0x2;
  87        state->fsm_ctrl_stalling = tmp & 0x4;
  88        state->fsm_ctrl_error = tmp & 0x8;
  89        tmp = tmp >> 4;
  90/* state->fsm_ctrl_state = (dma_ctrl_states_t)tmp; */
  91        if (tmp == 0)
  92                state->fsm_ctrl_state = DMA_CTRL_STATE_IDLE;
  93        if (tmp == 1)
  94                state->fsm_ctrl_state = DMA_CTRL_STATE_REQ_RCV;
  95        if (tmp == 2)
  96                state->fsm_ctrl_state = DMA_CTRL_STATE_RCV;
  97        if (tmp == 3)
  98                state->fsm_ctrl_state = DMA_CTRL_STATE_RCV_REQ;
  99        if (tmp == 4)
 100                state->fsm_ctrl_state = DMA_CTRL_STATE_INIT;
 101        state->fsm_ctrl_source_dev = dma_reg_load(ID,
 102                DMA_CG_INFO_REG_IDX(
 103                _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX,
 104                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 105        state->fsm_ctrl_source_addr = dma_reg_load(ID,
 106                DMA_CG_INFO_REG_IDX(
 107                _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX,
 108                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 109        state->fsm_ctrl_source_stride = dma_reg_load(ID,
 110                DMA_CG_INFO_REG_IDX(
 111                _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX,
 112                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 113        state->fsm_ctrl_source_width = dma_reg_load(ID,
 114                DMA_CG_INFO_REG_IDX(
 115                _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX,
 116                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 117        state->fsm_ctrl_source_height = dma_reg_load(ID,
 118                DMA_CG_INFO_REG_IDX(
 119                _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX,
 120                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 121        state->fsm_ctrl_pack_source_dev = dma_reg_load(ID,
 122                DMA_CG_INFO_REG_IDX(
 123                _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX,
 124                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 125        state->fsm_ctrl_pack_dest_dev = dma_reg_load(ID,
 126                DMA_CG_INFO_REG_IDX(
 127                _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX,
 128                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 129        state->fsm_ctrl_dest_addr = dma_reg_load(ID,
 130                DMA_CG_INFO_REG_IDX(
 131                _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX,
 132                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 133        state->fsm_ctrl_dest_stride = dma_reg_load(ID,
 134                DMA_CG_INFO_REG_IDX(
 135                _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX,
 136                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 137        state->fsm_ctrl_pack_source_width = dma_reg_load(ID,
 138                DMA_CG_INFO_REG_IDX(
 139                _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX,
 140                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 141        state->fsm_ctrl_pack_dest_height = dma_reg_load(ID,
 142                DMA_CG_INFO_REG_IDX(
 143                _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX,
 144                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 145        state->fsm_ctrl_pack_dest_width = dma_reg_load(ID,
 146                DMA_CG_INFO_REG_IDX(
 147                _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX,
 148                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 149        state->fsm_ctrl_pack_source_elems = dma_reg_load(ID,
 150                DMA_CG_INFO_REG_IDX(
 151                _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX,
 152                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 153        state->fsm_ctrl_pack_dest_elems = dma_reg_load(ID,
 154                DMA_CG_INFO_REG_IDX(
 155                _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX,
 156                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 157        state->fsm_ctrl_pack_extension = dma_reg_load(ID,
 158                DMA_CG_INFO_REG_IDX(
 159                _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX,
 160                _DMA_FSM_GROUP_FSM_CTRL_IDX));
 161
 162        tmp = dma_reg_load(ID,
 163                DMA_CG_INFO_REG_IDX(
 164                _DMA_FSM_GROUP_FSM_PACK_STATE_IDX,
 165                _DMA_FSM_GROUP_FSM_PACK_IDX));
 166        state->pack_idle     = tmp & 0x1;
 167        state->pack_run      = tmp & 0x2;
 168        state->pack_stalling = tmp & 0x4;
 169        state->pack_error    = tmp & 0x8;
 170        state->pack_cnt_height = dma_reg_load(ID,
 171                DMA_CG_INFO_REG_IDX(
 172                _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX,
 173                _DMA_FSM_GROUP_FSM_PACK_IDX));
 174        state->pack_src_cnt_width = dma_reg_load(ID,
 175                DMA_CG_INFO_REG_IDX(
 176                _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX,
 177                _DMA_FSM_GROUP_FSM_PACK_IDX));
 178        state->pack_dest_cnt_width = dma_reg_load(ID,
 179                DMA_CG_INFO_REG_IDX(
 180                _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX,
 181                _DMA_FSM_GROUP_FSM_PACK_IDX));
 182
 183        tmp = dma_reg_load(ID,
 184                DMA_CG_INFO_REG_IDX(
 185                _DMA_FSM_GROUP_FSM_REQ_STATE_IDX,
 186                _DMA_FSM_GROUP_FSM_REQ_IDX));
 187/* state->read_state = (dma_rw_states_t)tmp; */
 188        if (tmp == 0)
 189                state->read_state = DMA_RW_STATE_IDLE;
 190        if (tmp == 1)
 191                state->read_state = DMA_RW_STATE_REQ;
 192        if (tmp == 2)
 193                state->read_state = DMA_RW_STATE_NEXT_LINE;
 194        if (tmp == 3)
 195                state->read_state = DMA_RW_STATE_UNLOCK_CHANNEL;
 196        state->read_cnt_height = dma_reg_load(ID,
 197                DMA_CG_INFO_REG_IDX(
 198                _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX,
 199                _DMA_FSM_GROUP_FSM_REQ_IDX));
 200        state->read_cnt_width = dma_reg_load(ID,
 201                DMA_CG_INFO_REG_IDX(
 202                _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX,
 203                _DMA_FSM_GROUP_FSM_REQ_IDX));
 204
 205        tmp = dma_reg_load(ID,
 206                DMA_CG_INFO_REG_IDX(
 207                _DMA_FSM_GROUP_FSM_WR_STATE_IDX,
 208                _DMA_FSM_GROUP_FSM_WR_IDX));
 209/* state->write_state = (dma_rw_states_t)tmp; */
 210        if (tmp == 0)
 211                state->write_state = DMA_RW_STATE_IDLE;
 212        if (tmp == 1)
 213                state->write_state = DMA_RW_STATE_REQ;
 214        if (tmp == 2)
 215                state->write_state = DMA_RW_STATE_NEXT_LINE;
 216        if (tmp == 3)
 217                state->write_state = DMA_RW_STATE_UNLOCK_CHANNEL;
 218        state->write_height = dma_reg_load(ID,
 219                DMA_CG_INFO_REG_IDX(
 220                _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX,
 221                _DMA_FSM_GROUP_FSM_WR_IDX));
 222        state->write_width = dma_reg_load(ID,
 223                DMA_CG_INFO_REG_IDX(
 224                _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX,
 225                _DMA_FSM_GROUP_FSM_WR_IDX));
 226
 227        for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
 228                dma_port_state_t *port = &(state->port_states[i]);
 229
 230                tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(0, i));
 231                port->req_cs   = ((tmp & 0x1) != 0);
 232                port->req_we_n = ((tmp & 0x2) != 0);
 233                port->req_run  = ((tmp & 0x4) != 0);
 234                port->req_ack  = ((tmp & 0x8) != 0);
 235
 236                tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(1, i));
 237                port->send_cs   = ((tmp & 0x1) != 0);
 238                port->send_we_n = ((tmp & 0x2) != 0);
 239                port->send_run  = ((tmp & 0x4) != 0);
 240                port->send_ack  = ((tmp & 0x8) != 0);
 241
 242                tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(2, i));
 243                if (tmp & 0x1)
 244                        port->fifo_state = DMA_FIFO_STATE_WILL_BE_FULL;
 245                if (tmp & 0x2)
 246                        port->fifo_state = DMA_FIFO_STATE_FULL;
 247                if (tmp & 0x4)
 248                        port->fifo_state = DMA_FIFO_STATE_EMPTY;
 249                port->fifo_counter = tmp >> 3;
 250        }
 251
 252        for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
 253                dma_channel_state_t *ch = &(state->channel_states[i]);
 254
 255                ch->connection = DMA_GET_CONNECTION(dma_reg_load(ID,
 256                        DMA_CHANNEL_PARAM_REG_IDX(i,
 257                        _DMA_PACKING_SETUP_PARAM)));
 258                ch->sign_extend = DMA_GET_EXTENSION(dma_reg_load(ID,
 259                        DMA_CHANNEL_PARAM_REG_IDX(i,
 260                        _DMA_PACKING_SETUP_PARAM)));
 261                ch->height = dma_reg_load(ID,
 262                        DMA_CHANNEL_PARAM_REG_IDX(i,
 263                        _DMA_HEIGHT_PARAM));
 264                ch->stride_a = dma_reg_load(ID,
 265                        DMA_CHANNEL_PARAM_REG_IDX(i,
 266                        _DMA_STRIDE_A_PARAM));
 267                ch->elems_a = DMA_GET_ELEMENTS(dma_reg_load(ID,
 268                        DMA_CHANNEL_PARAM_REG_IDX(i,
 269                        _DMA_ELEM_CROPPING_A_PARAM)));
 270                ch->cropping_a = DMA_GET_CROPPING(dma_reg_load(ID,
 271                        DMA_CHANNEL_PARAM_REG_IDX(i,
 272                        _DMA_ELEM_CROPPING_A_PARAM)));
 273                ch->width_a = dma_reg_load(ID,
 274                        DMA_CHANNEL_PARAM_REG_IDX(i,
 275                        _DMA_WIDTH_A_PARAM));
 276                ch->stride_b = dma_reg_load(ID,
 277                        DMA_CHANNEL_PARAM_REG_IDX(i,
 278                        _DMA_STRIDE_B_PARAM));
 279                ch->elems_b = DMA_GET_ELEMENTS(dma_reg_load(ID,
 280                        DMA_CHANNEL_PARAM_REG_IDX(i,
 281                        _DMA_ELEM_CROPPING_B_PARAM)));
 282                ch->cropping_b = DMA_GET_CROPPING(dma_reg_load(ID,
 283                        DMA_CHANNEL_PARAM_REG_IDX(i,
 284                        _DMA_ELEM_CROPPING_B_PARAM)));
 285                ch->width_b = dma_reg_load(ID,
 286                        DMA_CHANNEL_PARAM_REG_IDX(i,
 287                        _DMA_WIDTH_B_PARAM));
 288        }
 289}
 290
 291void
 292dma_set_max_burst_size(const dma_ID_t ID, dma_connection conn,
 293                       uint32_t max_burst_size)
 294{
 295        assert(ID < N_DMA_ID);
 296        assert(max_burst_size > 0);
 297        dma_reg_store(ID, DMA_DEV_INFO_REG_IDX(_DMA_DEV_INTERF_MAX_BURST_IDX, conn),
 298                      max_burst_size - 1);
 299}
 300