LXR linux/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor

   1/*
   2 * Support for Intel Camera Imaging ISP subsystem.
   3 * Copyright (c) 2010-2015, Intel Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms and conditions of the GNU General Public License,
   7 * version 2, as published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 */
  14
  15#ifndef __FIFO_MONITOR_LOCAL_H_INCLUDED__
  16#define __FIFO_MONITOR_LOCAL_H_INCLUDED__
  17
  18#include <type_support.h>
  19#include "fifo_monitor_global.h"
  20
  21#include "hive_isp_css_defs.h"  /* ISP_STR_MON_PORT_SND_SP, ... */
  22
  23#define _hive_str_mon_valid_offset   0
  24#define _hive_str_mon_accept_offset  1
  25
  26#define FIFO_CHANNEL_SP_VALID_MASK              0x55555555
  27#define FIFO_CHANNEL_SP_VALID_B_MASK    0x00000055
  28#define FIFO_CHANNEL_ISP_VALID_MASK             0x15555555
  29#define FIFO_CHANNEL_MOD_VALID_MASK             0x55555555
  30
  31typedef enum fifo_switch {
  32        FIFO_SWITCH_IF,
  33        FIFO_SWITCH_GDC0,
  34        FIFO_SWITCH_GDC1,
  35        N_FIFO_SWITCH
  36} fifo_switch_t;
  37
  38typedef enum fifo_channel {
  39        FIFO_CHANNEL_ISP0_TO_SP0,
  40        FIFO_CHANNEL_SP0_TO_ISP0,
  41        FIFO_CHANNEL_ISP0_TO_IF0,
  42        FIFO_CHANNEL_IF0_TO_ISP0,
  43        FIFO_CHANNEL_ISP0_TO_IF1,
  44        FIFO_CHANNEL_IF1_TO_ISP0,
  45        FIFO_CHANNEL_ISP0_TO_DMA0,
  46        FIFO_CHANNEL_DMA0_TO_ISP0,
  47        FIFO_CHANNEL_ISP0_TO_GDC0,
  48        FIFO_CHANNEL_GDC0_TO_ISP0,
  49        FIFO_CHANNEL_ISP0_TO_GDC1,
  50        FIFO_CHANNEL_GDC1_TO_ISP0,
  51        FIFO_CHANNEL_ISP0_TO_HOST0,
  52        FIFO_CHANNEL_HOST0_TO_ISP0,
  53        FIFO_CHANNEL_SP0_TO_IF0,
  54        FIFO_CHANNEL_IF0_TO_SP0,
  55        FIFO_CHANNEL_SP0_TO_IF1,
  56        FIFO_CHANNEL_IF1_TO_SP0,
  57        FIFO_CHANNEL_SP0_TO_IF2,
  58        FIFO_CHANNEL_IF2_TO_SP0,
  59        FIFO_CHANNEL_SP0_TO_DMA0,
  60        FIFO_CHANNEL_DMA0_TO_SP0,
  61        FIFO_CHANNEL_SP0_TO_GDC0,
  62        FIFO_CHANNEL_GDC0_TO_SP0,
  63        FIFO_CHANNEL_SP0_TO_GDC1,
  64        FIFO_CHANNEL_GDC1_TO_SP0,
  65        FIFO_CHANNEL_SP0_TO_HOST0,
  66        FIFO_CHANNEL_HOST0_TO_SP0,
  67        FIFO_CHANNEL_SP0_TO_STREAM2MEM0,
  68        FIFO_CHANNEL_STREAM2MEM0_TO_SP0,
  69        FIFO_CHANNEL_SP0_TO_INPUT_SYSTEM0,
  70        FIFO_CHANNEL_INPUT_SYSTEM0_TO_SP0,
  71/*
  72 * No clue what this is
  73 *
  74        FIFO_CHANNEL_SP0_TO_IRQ0,
  75        FIFO_CHANNEL_IRQ0_TO_SP0,
  76 */
  77        N_FIFO_CHANNEL
  78} fifo_channel_t;
  79
  80struct fifo_channel_state_s {
  81        bool    src_valid;
  82        bool    fifo_accept;
  83        bool    fifo_valid;
  84        bool    sink_accept;
  85};
  86
  87/* The switch is tri-state */
  88struct fifo_switch_state_s {
  89        bool    is_none;
  90        bool    is_isp;
  91        bool    is_sp;
  92};
  93
  94struct fifo_monitor_state_s {
  95        struct fifo_channel_state_s     fifo_channels[N_FIFO_CHANNEL];
  96        struct fifo_switch_state_s      fifo_switches[N_FIFO_SWITCH];
  97};
  98
  99#endif /* __FIFO_MONITOR_LOCAL_H_INCLUDED__ */
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