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15#ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__
16#define __INPUT_SYSTEM_LOCAL_H_INCLUDED__
17
18#include <type_support.h>
19
20#include "input_system_global.h"
21
22#include "input_system_defs.h"
23#include "css_receiver_2400_defs.h"
24#if defined(IS_ISP_2400_MAMOIADA_SYSTEM)
25#include "isp_capture_defs.h"
26#elif defined(IS_ISP_2401_MAMOIADA_SYSTEM)
27
28#include "isp_capture_defs.h"
29#else
30#error "input_system_local.h: 2400_SYSTEM must be one of {2400, 2401 }"
31#endif
32#include "isp_acquisition_defs.h"
33#include "input_system_ctrl_defs.h"
34
35
36typedef enum {
37 INPUT_SYSTEM_ERR_NO_ERROR = 0,
38 INPUT_SYSTEM_ERR_GENERIC,
39 INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET,
40 INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE,
41 INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED,
42 N_INPUT_SYSTEM_ERR
43} input_system_error_t;
44
45typedef enum {
46 INPUT_SYSTEM_PORT_A = 0,
47 INPUT_SYSTEM_PORT_B,
48 INPUT_SYSTEM_PORT_C,
49 N_INPUT_SYSTEM_PORTS
50} input_system_csi_port_t;
51
52typedef struct ctrl_unit_cfg_s ctrl_unit_cfg_t;
53typedef struct input_system_network_cfg_s input_system_network_cfg_t;
54typedef struct target_cfg2400_s target_cfg2400_t;
55typedef struct channel_cfg_s channel_cfg_t;
56typedef struct backend_channel_cfg_s backend_channel_cfg_t;
57typedef struct input_system_cfg2400_s input_system_cfg2400_t;
58typedef struct mipi_port_state_s mipi_port_state_t;
59typedef struct rx_channel_state_s rx_channel_state_t;
60typedef struct input_switch_cfg_channel_s input_switch_cfg_channel_t;
61typedef struct input_switch_cfg_s input_switch_cfg_t;
62
63struct ctrl_unit_cfg_s {
64 ib_buffer_t buffer_mipi[N_CAPTURE_UNIT_ID];
65 ib_buffer_t buffer_acquire[N_ACQUISITION_UNIT_ID];
66};
67
68struct input_system_network_cfg_s {
69 input_system_connection_t multicast_cfg[N_CAPTURE_UNIT_ID];
70 input_system_multiplex_t mux_cfg;
71 ctrl_unit_cfg_t ctrl_unit_cfg[N_CTRL_UNIT_ID];
72};
73
74typedef struct {
75
76 uint32_t dummy_parameter;
77} target_isp_cfg_t;
78
79
80typedef struct {
81
82 uint32_t dummy_parameter;
83} target_sp_cfg_t;
84
85
86typedef struct {
87
88 uint32_t dummy_parameter;
89} target_strm2mem_cfg_t;
90
91struct input_switch_cfg_channel_s {
92 uint32_t hsync_data_reg[2];
93 uint32_t vsync_data_reg;
94};
95
96struct target_cfg2400_s {
97 input_switch_cfg_channel_t input_switch_channel_cfg;
98 target_isp_cfg_t target_isp_cfg;
99 target_sp_cfg_t target_sp_cfg;
100 target_strm2mem_cfg_t target_strm2mem_cfg;
101};
102
103struct backend_channel_cfg_s {
104 uint32_t fmt_control_word_1;
105 uint32_t fmt_control_word_2;
106 uint32_t no_side_band;
107};
108
109typedef union {
110 csi_cfg_t csi_cfg;
111 tpg_cfg_t tpg_cfg;
112 prbs_cfg_t prbs_cfg;
113 gpfifo_cfg_t gpfifo_cfg;
114} source_cfg_t;
115
116
117struct input_switch_cfg_s {
118 uint32_t hsync_data_reg[N_RX_CHANNEL_ID * 2];
119 uint32_t vsync_data_reg;
120};
121
122
123struct channel_cfg_s {
124 uint32_t ch_id;
125 backend_channel_cfg_t backend_ch;
126 input_system_source_t source_type;
127 source_cfg_t source_cfg;
128 target_cfg2400_t target_cfg;
129};
130
131
132
133struct input_system_cfg2400_s {
134
135 input_system_source_t source_type; input_system_config_flags_t source_type_flags;
136
137 input_system_config_flags_t ch_flags[N_CHANNELS];
138
139 csi_cfg_t csi_value[N_CSI_PORTS]; input_system_config_flags_t csi_flags[N_CSI_PORTS];
140
141
142
143 ib_buffer_t csi_buffer[N_CSI_PORTS]; input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS];
144 ib_buffer_t acquisition_buffer_unique; input_system_config_flags_t acquisition_buffer_unique_flags;
145 uint32_t unallocated_ib_mem_words;
146
147
148 input_system_connection_t multicast[N_CSI_PORTS];
149 input_system_multiplex_t multiplexer; input_system_config_flags_t multiplexer_flags;
150
151
152 tpg_cfg_t tpg_value; input_system_config_flags_t tpg_flags;
153 prbs_cfg_t prbs_value; input_system_config_flags_t prbs_flags;
154 gpfifo_cfg_t gpfifo_value; input_system_config_flags_t gpfifo_flags;
155
156
157 input_switch_cfg_t input_switch_cfg;
158
159
160 target_isp_cfg_t target_isp [N_CHANNELS]; input_system_config_flags_t target_isp_flags [N_CHANNELS];
161 target_sp_cfg_t target_sp [N_CHANNELS]; input_system_config_flags_t target_sp_flags [N_CHANNELS];
162 target_strm2mem_cfg_t target_strm2mem [N_CHANNELS]; input_system_config_flags_t target_strm2mem_flags [N_CHANNELS];
163
164 input_system_config_flags_t session_flags;
165
166};
167
168
169
170
171#define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX
172#define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX
173#define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX
174#define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX
175#define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX
176
177#define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX
178#define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX
179#define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX
180
181
182
183#define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX
184#define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX
185#define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX
186#define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX
187#define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX
188#define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX
189#define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX
190#define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX
191#define _HRT_CSS_RECEIVER_RAW18_REG_IDX _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX
192#define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX
193#define _HRT_CSS_RECEIVER_RAW16_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX
194
195
196#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX
197#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX
198#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX
199#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX
200#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX
201#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX
202#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX
203#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX
204
205
206#define _HRT_CSS_BE_OFFSET 448
207#define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET)
208#define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET)
209#define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET)
210#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET)
211#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET)
212#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET)
213#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET)
214#define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET)
215#define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET)
216#define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET)
217#define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET)
218#define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET)
219#define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET)
220
221
222#define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT
223#define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT
224#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT
225#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT
226#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT
227#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT
228#define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT
229#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT
230#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT
231#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT
232#define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT
233#define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT
234#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT
235#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT
236#define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT
237#define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT
238#define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT
239
240#define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX
241#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX
242#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS
243
244typedef struct capture_unit_state_s capture_unit_state_t;
245typedef struct acquisition_unit_state_s acquisition_unit_state_t;
246typedef struct ctrl_unit_state_s ctrl_unit_state_t;
247
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257
258
259typedef enum {
260 MONO_4L_1L_0L = 0,
261 MONO_3L_1L_0L,
262 MONO_2L_1L_0L,
263 MONO_1L_1L_0L,
264 STEREO_2L_1L_2L,
265 STEREO_3L_1L_1L,
266 STEREO_2L_1L_1L,
267 STEREO_1L_1L_1L,
268 N_RX_MODE
269} rx_mode_t;
270
271typedef enum {
272 MIPI_PREDICTOR_NONE = 0,
273 MIPI_PREDICTOR_TYPE1,
274 MIPI_PREDICTOR_TYPE2,
275 N_MIPI_PREDICTOR_TYPES
276} mipi_predictor_t;
277
278typedef enum {
279 MIPI_COMPRESSOR_NONE = 0,
280 MIPI_COMPRESSOR_10_6_10,
281 MIPI_COMPRESSOR_10_7_10,
282 MIPI_COMPRESSOR_10_8_10,
283 MIPI_COMPRESSOR_12_6_12,
284 MIPI_COMPRESSOR_12_7_12,
285 MIPI_COMPRESSOR_12_8_12,
286 N_MIPI_COMPRESSOR_METHODS
287} mipi_compressor_t;
288
289typedef enum {
290 MIPI_FORMAT_RGB888 = 0,
291 MIPI_FORMAT_RGB555,
292 MIPI_FORMAT_RGB444,
293 MIPI_FORMAT_RGB565,
294 MIPI_FORMAT_RGB666,
295 MIPI_FORMAT_RAW8,
296 MIPI_FORMAT_RAW10,
297 MIPI_FORMAT_RAW6,
298 MIPI_FORMAT_RAW7,
299 MIPI_FORMAT_RAW12,
300 MIPI_FORMAT_RAW14,
301 MIPI_FORMAT_YUV420_8,
302 MIPI_FORMAT_YUV420_10,
303 MIPI_FORMAT_YUV422_8,
304 MIPI_FORMAT_YUV422_10,
305 MIPI_FORMAT_CUSTOM0,
306 MIPI_FORMAT_YUV420_8_LEGACY,
307 MIPI_FORMAT_EMBEDDED,
308 MIPI_FORMAT_CUSTOM1,
309 MIPI_FORMAT_CUSTOM2,
310 MIPI_FORMAT_CUSTOM3,
311 MIPI_FORMAT_CUSTOM4,
312 MIPI_FORMAT_CUSTOM5,
313 MIPI_FORMAT_CUSTOM6,
314 MIPI_FORMAT_CUSTOM7,
315 MIPI_FORMAT_YUV420_8_SHIFT,
316 MIPI_FORMAT_YUV420_10_SHIFT,
317 MIPI_FORMAT_RAW16,
318 MIPI_FORMAT_RAW18,
319 N_MIPI_FORMAT,
320} mipi_format_t;
321
322#define MIPI_FORMAT_JPEG MIPI_FORMAT_CUSTOM0
323#define MIPI_FORMAT_BINARY_8 MIPI_FORMAT_CUSTOM0
324#define N_MIPI_FORMAT_CUSTOM 8
325
326
327#define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM)
328
329typedef enum {
330 RX_IRQ_INFO_BUFFER_OVERRUN = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT,
331 RX_IRQ_INFO_INIT_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT,
332 RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT,
333 RX_IRQ_INFO_EXIT_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT,
334 RX_IRQ_INFO_ECC_CORRECTED = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT,
335 RX_IRQ_INFO_ERR_SOT = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT,
336 RX_IRQ_INFO_ERR_SOT_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT,
337 RX_IRQ_INFO_ERR_CONTROL = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT,
338 RX_IRQ_INFO_ERR_ECC_DOUBLE = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT,
339
340 RX_IRQ_INFO_ERR_CRC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT,
341 RX_IRQ_INFO_ERR_UNKNOWN_ID = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT,
342 RX_IRQ_INFO_ERR_FRAME_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT,
343 RX_IRQ_INFO_ERR_FRAME_DATA = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT,
344 RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT,
345 RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT,
346 RX_IRQ_INFO_ERR_LINE_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT,
347} rx_irq_info_t;
348
349typedef struct rx_cfg_s rx_cfg_t;
350
351
352
353
354struct rx_cfg_s {
355 rx_mode_t mode;
356 enum mipi_port_id port;
357 unsigned int timeout;
358 unsigned int initcount;
359 unsigned int synccount;
360 unsigned int rxcount;
361 mipi_predictor_t comp;
362 bool is_two_ppc;
363};
364
365
366static const hrt_address MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = {
367 0x00000000UL,
368 0x00000100UL,
369 0x00000200UL};
370
371static const mipi_lane_cfg_t MIPI_PORT_MAXLANES[N_MIPI_PORT_ID] = {
372 MIPI_4LANE_CFG,
373 MIPI_1LANE_CFG,
374 MIPI_2LANE_CFG};
375
376static const bool MIPI_PORT_ACTIVE[N_RX_MODE][N_MIPI_PORT_ID] = {
377 {true, true, false},
378 {true, true, false},
379 {true, true, false},
380 {true, true, false},
381 {true, true, true},
382 {true, true, true},
383 {true, true, true},
384 {true, true, true}};
385
386static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = {
387 {MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},
388 {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},
389 {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},
390 {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},
391 {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG},
392 {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG},
393 {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG},
394 {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}};
395
396static const hrt_address SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = {
397 0x00001000UL,
398 0x00002000UL,
399 0x00003000UL,
400 0x00004000UL,
401 0x00005000UL,
402 0x00009000UL,
403 0x0000A000UL,
404 0x0000B000UL,
405 0x0000C000UL};
406
407struct capture_unit_state_s {
408 int Packet_Length;
409 int Received_Length;
410 int Received_Short_Packets;
411 int Received_Long_Packets;
412 int Last_Command;
413 int Next_Command;
414 int Last_Acknowledge;
415 int Next_Acknowledge;
416 int FSM_State_Info;
417 int StartMode;
418 int Start_Addr;
419 int Mem_Region_Size;
420 int Num_Mem_Regions;
421
422
423
424};
425
426struct acquisition_unit_state_s {
427
428 int Received_Short_Packets;
429 int Received_Long_Packets;
430 int Last_Command;
431 int Next_Command;
432 int Last_Acknowledge;
433 int Next_Acknowledge;
434 int FSM_State_Info;
435 int Int_Cntr_Info;
436 int Start_Addr;
437 int Mem_Region_Size;
438 int Num_Mem_Regions;
439};
440
441struct ctrl_unit_state_s {
442 int last_cmd;
443 int next_cmd;
444 int last_ack;
445 int next_ack;
446 int top_fsm_state;
447 int captA_fsm_state;
448 int captB_fsm_state;
449 int captC_fsm_state;
450 int acq_fsm_state;
451 int captA_start_addr;
452 int captB_start_addr;
453 int captC_start_addr;
454 int captA_mem_region_size;
455 int captB_mem_region_size;
456 int captC_mem_region_size;
457 int captA_num_mem_regions;
458 int captB_num_mem_regions;
459 int captC_num_mem_regions;
460 int acq_start_addr;
461 int acq_mem_region_size;
462 int acq_num_mem_regions;
463
464 int capt_reserve_one_mem_region;
465};
466
467struct input_system_state_s {
468 int str_multicastA_sel;
469 int str_multicastB_sel;
470 int str_multicastC_sel;
471 int str_mux_sel;
472 int str_mon_status;
473 int str_mon_irq_cond;
474 int str_mon_irq_en;
475 int isys_srst;
476 int isys_slv_reg_srst;
477 int str_deint_portA_cnt;
478 int str_deint_portB_cnt;
479 struct capture_unit_state_s capture_unit[N_CAPTURE_UNIT_ID];
480 struct acquisition_unit_state_s acquisition_unit[N_ACQUISITION_UNIT_ID];
481 struct ctrl_unit_state_s ctrl_unit_state[N_CTRL_UNIT_ID];
482};
483
484struct mipi_port_state_s {
485 int device_ready;
486 int irq_status;
487 int irq_enable;
488 uint32_t timeout_count;
489 uint16_t init_count;
490 uint16_t raw16_18;
491 uint32_t sync_count;
492 uint32_t rx_count;
493 uint8_t lane_sync_count[MIPI_4LANE_CFG];
494 uint8_t lane_rx_count[MIPI_4LANE_CFG];
495};
496
497struct rx_channel_state_s {
498 uint32_t comp_scheme0;
499 uint32_t comp_scheme1;
500 mipi_predictor_t pred[N_MIPI_FORMAT_CUSTOM];
501 mipi_compressor_t comp[N_MIPI_FORMAT_CUSTOM];
502};
503
504struct receiver_state_s {
505 uint8_t fs_to_ls_delay;
506 uint8_t ls_to_data_delay;
507 uint8_t data_to_le_delay;
508 uint8_t le_to_fe_delay;
509 uint8_t fe_to_fs_delay;
510 uint8_t le_to_fs_delay;
511 bool is_two_ppc;
512 int backend_rst;
513 uint16_t raw18;
514 bool force_raw8;
515 uint16_t raw16;
516 struct mipi_port_state_s mipi_port_state[N_MIPI_PORT_ID];
517 struct rx_channel_state_s rx_channel_state[N_RX_CHANNEL_ID];
518 int be_gsp_acc_ovl;
519 int be_srst;
520 int be_is_two_ppc;
521 int be_comp_format0;
522 int be_comp_format1;
523 int be_comp_format2;
524 int be_comp_format3;
525 int be_sel;
526 int be_raw16_config;
527 int be_raw18_config;
528 int be_force_raw8;
529 int be_irq_status;
530 int be_irq_clear;
531};
532
533#endif
534
