1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#ifndef _DAVINCI_VPFE_DM365_RESIZER_H
23#define _DAVINCI_VPFE_DM365_RESIZER_H
24
25enum resizer_oper_mode {
26 RESIZER_MODE_CONTINIOUS = 0,
27 RESIZER_MODE_ONE_SHOT = 1,
28};
29
30struct f_div_pass {
31 unsigned int o_hsz;
32 unsigned int i_hps;
33 unsigned int h_phs;
34 unsigned int src_hps;
35 unsigned int src_hsz;
36};
37
38#define MAX_PASSES 2
39
40struct f_div_param {
41 unsigned char en;
42 unsigned int num_passes;
43 struct f_div_pass pass[MAX_PASSES];
44};
45
46
47struct resizer_scale_param {
48 bool h_flip;
49 bool v_flip;
50 bool cen;
51 bool yen;
52 unsigned short i_vps;
53 unsigned short i_hps;
54 unsigned short o_vsz;
55 unsigned short o_hsz;
56 unsigned short v_phs_y;
57 unsigned short v_phs_c;
58 unsigned short v_dif;
59
60 enum vpfe_rsz_intp_t v_typ_y;
61
62 enum vpfe_rsz_intp_t v_typ_c;
63
64 unsigned char v_lpf_int_y;
65
66 unsigned char v_lpf_int_c;
67 unsigned short h_phs;
68 unsigned short h_dif;
69
70 enum vpfe_rsz_intp_t h_typ_y;
71
72 enum vpfe_rsz_intp_t h_typ_c;
73
74 unsigned char h_lpf_int_y;
75
76 unsigned char h_lpf_int_c;
77 bool dscale_en;
78 enum vpfe_rsz_down_scale_ave_sz h_dscale_ave_sz;
79 enum vpfe_rsz_down_scale_ave_sz v_dscale_ave_sz;
80
81 struct f_div_param f_div;
82};
83
84enum resizer_rgb_t {
85 OUTPUT_32BIT,
86 OUTPUT_16BIT
87};
88
89enum resizer_rgb_msk_t {
90 NOMASK = 0,
91 MASKLAST2 = 1,
92};
93
94
95struct resizer_rgb {
96 bool rgb_en;
97 enum resizer_rgb_t rgb_typ;
98 enum resizer_rgb_msk_t rgb_msk0;
99 enum resizer_rgb_msk_t rgb_msk1;
100 unsigned int rgb_alpha_val;
101};
102
103
104struct rsz_ext_mem_param {
105 unsigned int rsz_sdr_oft_y;
106 unsigned int rsz_sdr_ptr_s_y;
107 unsigned int rsz_sdr_ptr_e_y;
108 unsigned int rsz_sdr_oft_c;
109 unsigned int rsz_sdr_ptr_s_c;
110 unsigned int rsz_sdr_ptr_e_c;
111
112 unsigned int flip_ofst_y;
113
114 unsigned int flip_ofst_c;
115
116 unsigned int c_offset;
117
118 unsigned int user_y_ofst;
119
120 unsigned int user_c_ofst;
121};
122
123enum rsz_data_source {
124 IPIPE_DATA,
125 IPIPEIF_DATA
126};
127
128enum rsz_src_img_fmt {
129 RSZ_IMG_422,
130 RSZ_IMG_420
131};
132
133enum rsz_dpaths_bypass_t {
134 BYPASS_OFF = 0,
135 BYPASS_ON = 1,
136};
137
138struct rsz_common_params {
139 unsigned int vps;
140 unsigned int vsz;
141 unsigned int hps;
142 unsigned int hsz;
143
144 enum rsz_src_img_fmt src_img_fmt;
145
146 unsigned char y_c;
147
148 unsigned char raw_flip;
149
150 enum rsz_data_source source;
151 enum rsz_dpaths_bypass_t passthrough;
152 unsigned char yuv_y_min;
153 unsigned char yuv_y_max;
154 unsigned char yuv_c_min;
155 unsigned char yuv_c_max;
156 bool rsz_seq_crv;
157 enum vpfe_chr_pos out_chr_pos;
158};
159
160struct resizer_params {
161 enum resizer_oper_mode oper_mode;
162 struct rsz_common_params rsz_common;
163 struct resizer_scale_param rsz_rsc_param[2];
164 struct resizer_rgb rsz2rgb[2];
165 struct rsz_ext_mem_param ext_mem_param[2];
166 bool rsz_en[2];
167 struct vpfe_rsz_config_params user_config;
168};
169
170#define ENABLE 1
171#define DISABLE (!ENABLE)
172
173#define RESIZER_CROP_PAD_SINK 0
174#define RESIZER_CROP_PAD_SOURCE 1
175#define RESIZER_CROP_PAD_SOURCE2 2
176
177#define RESIZER_CROP_PADS_NUM 3
178
179enum resizer_crop_input_entity {
180 RESIZER_CROP_INPUT_NONE = 0,
181 RESIZER_CROP_INPUT_IPIPEIF = 1,
182 RESIZER_CROP_INPUT_IPIPE = 2,
183};
184
185enum resizer_crop_output_entity {
186 RESIZER_CROP_OUTPUT_NONE,
187 RESIZER_A,
188 RESIZER_B,
189};
190
191struct dm365_crop_resizer_device {
192 struct v4l2_subdev subdev;
193 struct media_pad pads[RESIZER_CROP_PADS_NUM];
194 struct v4l2_mbus_framefmt formats[RESIZER_CROP_PADS_NUM];
195 enum resizer_crop_input_entity input;
196 enum resizer_crop_output_entity output;
197 enum resizer_crop_output_entity output2;
198 struct vpfe_resizer_device *rsz_device;
199};
200
201#define RESIZER_PAD_SINK 0
202#define RESIZER_PAD_SOURCE 1
203
204#define RESIZER_PADS_NUM 2
205
206enum resizer_input_entity {
207 RESIZER_INPUT_NONE = 0,
208 RESIZER_INPUT_CROP_RESIZER = 1,
209};
210
211enum resizer_output_entity {
212 RESIZER_OUTPUT_NONE = 0,
213 RESIZER_OUTPUT_MEMORY = 1,
214};
215
216struct dm365_resizer_device {
217 struct v4l2_subdev subdev;
218 struct media_pad pads[RESIZER_PADS_NUM];
219 struct v4l2_mbus_framefmt formats[RESIZER_PADS_NUM];
220 enum resizer_input_entity input;
221 enum resizer_output_entity output;
222 struct vpfe_video_device video_out;
223 struct vpfe_resizer_device *rsz_device;
224};
225
226struct vpfe_resizer_device {
227 struct dm365_crop_resizer_device crop_resizer;
228 struct dm365_resizer_device resizer_a;
229 struct dm365_resizer_device resizer_b;
230 struct resizer_params config;
231 void __iomem *base_addr;
232};
233
234int vpfe_resizer_init(struct vpfe_resizer_device *vpfe_rsz,
235 struct platform_device *pdev);
236int vpfe_resizer_register_entities(struct vpfe_resizer_device *vpfe_rsz,
237 struct v4l2_device *v4l2_dev);
238void vpfe_resizer_unregister_entities(struct vpfe_resizer_device *vpfe_rsz);
239void vpfe_resizer_cleanup(struct vpfe_resizer_device *vpfe_rsz,
240 struct platform_device *pdev);
241void vpfe_resizer_buffer_isr(struct vpfe_resizer_device *resizer);
242void vpfe_resizer_dma_isr(struct vpfe_resizer_device *resizer);
243
244#endif
245
