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15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/dma-mapping.h>
19#include <linux/init.h>
20#include <linux/skbuff.h>
21#include <linux/etherdevice.h>
22#include <linux/ethtool.h>
23#include <linux/platform_device.h>
24#include <linux/of_device.h>
25#include <linux/mfd/syscon.h>
26#include <linux/clk.h>
27#include <linux/of_net.h>
28#include <linux/of_mdio.h>
29#include <linux/if_vlan.h>
30#include <linux/reset.h>
31#include <linux/tcp.h>
32#include <linux/io.h>
33#include <linux/bug.h>
34#include <linux/regmap.h>
35
36#include "mtk_eth_soc.h"
37#include "mdio.h"
38#include "ethtool.h"
39
40#define MAX_RX_LENGTH 1536
41#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
42#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
43#define DMA_DUMMY_DESC 0xffffffff
44#define MTK_DEFAULT_MSG_ENABLE \
45 (NETIF_MSG_DRV | \
46 NETIF_MSG_PROBE | \
47 NETIF_MSG_LINK | \
48 NETIF_MSG_TIMER | \
49 NETIF_MSG_IFDOWN | \
50 NETIF_MSG_IFUP | \
51 NETIF_MSG_RX_ERR | \
52 NETIF_MSG_TX_ERR)
53
54#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
55#define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
56#define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
57
58#define SYSC_REG_RSTCTRL 0x34
59
60static int mtk_msg_level = -1;
61module_param_named(msg_level, mtk_msg_level, int, 0);
62MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
63
64static const u16 mtk_reg_table_default[MTK_REG_COUNT] = {
65 [MTK_REG_PDMA_GLO_CFG] = MTK_PDMA_GLO_CFG,
66 [MTK_REG_PDMA_RST_CFG] = MTK_PDMA_RST_CFG,
67 [MTK_REG_DLY_INT_CFG] = MTK_DLY_INT_CFG,
68 [MTK_REG_TX_BASE_PTR0] = MTK_TX_BASE_PTR0,
69 [MTK_REG_TX_MAX_CNT0] = MTK_TX_MAX_CNT0,
70 [MTK_REG_TX_CTX_IDX0] = MTK_TX_CTX_IDX0,
71 [MTK_REG_TX_DTX_IDX0] = MTK_TX_DTX_IDX0,
72 [MTK_REG_RX_BASE_PTR0] = MTK_RX_BASE_PTR0,
73 [MTK_REG_RX_MAX_CNT0] = MTK_RX_MAX_CNT0,
74 [MTK_REG_RX_CALC_IDX0] = MTK_RX_CALC_IDX0,
75 [MTK_REG_RX_DRX_IDX0] = MTK_RX_DRX_IDX0,
76 [MTK_REG_MTK_INT_ENABLE] = MTK_INT_ENABLE,
77 [MTK_REG_MTK_INT_STATUS] = MTK_INT_STATUS,
78 [MTK_REG_MTK_DMA_VID_BASE] = MTK_DMA_VID0,
79 [MTK_REG_MTK_COUNTER_BASE] = MTK_GDMA1_TX_GBCNT,
80 [MTK_REG_MTK_RST_GL] = MTK_RST_GL,
81};
82
83static const u16 *mtk_reg_table = mtk_reg_table_default;
84
85void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
86{
87 __raw_writel(val, eth->base + reg);
88}
89
90u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
91{
92 return __raw_readl(eth->base + reg);
93}
94
95static void mtk_reg_w32(struct mtk_eth *eth, u32 val, enum mtk_reg reg)
96{
97 mtk_w32(eth, val, mtk_reg_table[reg]);
98}
99
100static u32 mtk_reg_r32(struct mtk_eth *eth, enum mtk_reg reg)
101{
102 return mtk_r32(eth, mtk_reg_table[reg]);
103}
104
105
106
107
108
109
110void mtk_reset(struct mtk_eth *eth, u32 reset_bits)
111{
112 u32 val;
113
114 regmap_read(eth->ethsys, SYSC_REG_RSTCTRL, &val);
115 val |= reset_bits;
116 regmap_write(eth->ethsys, SYSC_REG_RSTCTRL, val);
117 usleep_range(10, 20);
118 val &= ~reset_bits;
119 regmap_write(eth->ethsys, SYSC_REG_RSTCTRL, val);
120 usleep_range(10, 20);
121}
122EXPORT_SYMBOL(mtk_reset);
123
124static inline void mtk_irq_ack(struct mtk_eth *eth, u32 mask)
125{
126 if (eth->soc->dma_type & MTK_PDMA)
127 mtk_reg_w32(eth, mask, MTK_REG_MTK_INT_STATUS);
128 if (eth->soc->dma_type & MTK_QDMA)
129 mtk_w32(eth, mask, MTK_QMTK_INT_STATUS);
130}
131
132static inline u32 mtk_irq_pending(struct mtk_eth *eth)
133{
134 u32 status = 0;
135
136 if (eth->soc->dma_type & MTK_PDMA)
137 status |= mtk_reg_r32(eth, MTK_REG_MTK_INT_STATUS);
138 if (eth->soc->dma_type & MTK_QDMA)
139 status |= mtk_r32(eth, MTK_QMTK_INT_STATUS);
140
141 return status;
142}
143
144static void mtk_irq_ack_status(struct mtk_eth *eth, u32 mask)
145{
146 u32 status_reg = MTK_REG_MTK_INT_STATUS;
147
148 if (mtk_reg_table[MTK_REG_MTK_INT_STATUS2])
149 status_reg = MTK_REG_MTK_INT_STATUS2;
150
151 mtk_reg_w32(eth, mask, status_reg);
152}
153
154static u32 mtk_irq_pending_status(struct mtk_eth *eth)
155{
156 u32 status_reg = MTK_REG_MTK_INT_STATUS;
157
158 if (mtk_reg_table[MTK_REG_MTK_INT_STATUS2])
159 status_reg = MTK_REG_MTK_INT_STATUS2;
160
161 return mtk_reg_r32(eth, status_reg);
162}
163
164static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
165{
166 u32 val;
167
168 if (eth->soc->dma_type & MTK_PDMA) {
169 val = mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
170 mtk_reg_w32(eth, val & ~mask, MTK_REG_MTK_INT_ENABLE);
171
172 mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
173 }
174 if (eth->soc->dma_type & MTK_QDMA) {
175 val = mtk_r32(eth, MTK_QMTK_INT_ENABLE);
176 mtk_w32(eth, val & ~mask, MTK_QMTK_INT_ENABLE);
177
178 mtk_r32(eth, MTK_QMTK_INT_ENABLE);
179 }
180}
181
182static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
183{
184 u32 val;
185
186 if (eth->soc->dma_type & MTK_PDMA) {
187 val = mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
188 mtk_reg_w32(eth, val | mask, MTK_REG_MTK_INT_ENABLE);
189
190 mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
191 }
192 if (eth->soc->dma_type & MTK_QDMA) {
193 val = mtk_r32(eth, MTK_QMTK_INT_ENABLE);
194 mtk_w32(eth, val | mask, MTK_QMTK_INT_ENABLE);
195
196 mtk_r32(eth, MTK_QMTK_INT_ENABLE);
197 }
198}
199
200static inline u32 mtk_irq_enabled(struct mtk_eth *eth)
201{
202 u32 enabled = 0;
203
204 if (eth->soc->dma_type & MTK_PDMA)
205 enabled |= mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
206 if (eth->soc->dma_type & MTK_QDMA)
207 enabled |= mtk_r32(eth, MTK_QMTK_INT_ENABLE);
208
209 return enabled;
210}
211
212static inline void mtk_hw_set_macaddr(struct mtk_mac *mac,
213 unsigned char *macaddr)
214{
215 unsigned long flags;
216
217 spin_lock_irqsave(&mac->hw->page_lock, flags);
218 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], MTK_GDMA1_MAC_ADRH);
219 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
220 (macaddr[4] << 8) | macaddr[5],
221 MTK_GDMA1_MAC_ADRL);
222 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
223}
224
225static int mtk_set_mac_address(struct net_device *dev, void *p)
226{
227 int ret = eth_mac_addr(dev, p);
228 struct mtk_mac *mac = netdev_priv(dev);
229 struct mtk_eth *eth = mac->hw;
230
231 if (ret)
232 return ret;
233
234 if (eth->soc->set_mac)
235 eth->soc->set_mac(mac, dev->dev_addr);
236 else
237 mtk_hw_set_macaddr(mac, p);
238
239 return 0;
240}
241
242static inline int mtk_max_frag_size(int mtu)
243{
244
245 if (mtu + MTK_RX_ETH_HLEN < MAX_RX_LENGTH)
246 mtu = MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
247
248 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
249 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
250}
251
252static inline int mtk_max_buf_size(int frag_size)
253{
254 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
255 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
256
257 WARN_ON(buf_size < MAX_RX_LENGTH);
258
259 return buf_size;
260}
261
262static inline void mtk_get_rxd(struct mtk_rx_dma *rxd,
263 struct mtk_rx_dma *dma_rxd)
264{
265 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
266 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
267 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
268 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
269}
270
271static inline void mtk_set_txd_pdma(struct mtk_tx_dma *txd,
272 struct mtk_tx_dma *dma_txd)
273{
274 WRITE_ONCE(dma_txd->txd1, txd->txd1);
275 WRITE_ONCE(dma_txd->txd3, txd->txd3);
276 WRITE_ONCE(dma_txd->txd4, txd->txd4);
277
278 WRITE_ONCE(dma_txd->txd2, txd->txd2);
279}
280
281static void mtk_clean_rx(struct mtk_eth *eth, struct mtk_rx_ring *ring)
282{
283 int i;
284
285 if (ring->rx_data && ring->rx_dma) {
286 for (i = 0; i < ring->rx_ring_size; i++) {
287 if (!ring->rx_data[i])
288 continue;
289 if (!ring->rx_dma[i].rxd1)
290 continue;
291 dma_unmap_single(eth->dev,
292 ring->rx_dma[i].rxd1,
293 ring->rx_buf_size,
294 DMA_FROM_DEVICE);
295 skb_free_frag(ring->rx_data[i]);
296 }
297 kfree(ring->rx_data);
298 ring->rx_data = NULL;
299 }
300
301 if (ring->rx_dma) {
302 dma_free_coherent(eth->dev,
303 ring->rx_ring_size * sizeof(*ring->rx_dma),
304 ring->rx_dma,
305 ring->rx_phys);
306 ring->rx_dma = NULL;
307 }
308}
309
310static int mtk_dma_rx_alloc(struct mtk_eth *eth, struct mtk_rx_ring *ring)
311{
312 int i, pad = 0;
313
314 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
315 ring->rx_buf_size = mtk_max_buf_size(ring->frag_size);
316 ring->rx_ring_size = eth->soc->dma_ring_size;
317 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
318 GFP_KERNEL);
319 if (!ring->rx_data)
320 goto no_rx_mem;
321
322 for (i = 0; i < ring->rx_ring_size; i++) {
323 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
324 if (!ring->rx_data[i])
325 goto no_rx_mem;
326 }
327
328 ring->rx_dma = dma_alloc_coherent(eth->dev,
329 ring->rx_ring_size * sizeof(*ring->rx_dma),
330 &ring->rx_phys,
331 GFP_ATOMIC | __GFP_ZERO);
332 if (!ring->rx_dma)
333 goto no_rx_mem;
334
335 if (!eth->soc->rx_2b_offset)
336 pad = NET_IP_ALIGN;
337
338 for (i = 0; i < ring->rx_ring_size; i++) {
339 dma_addr_t dma_addr = dma_map_single(eth->dev,
340 ring->rx_data[i] + NET_SKB_PAD + pad,
341 ring->rx_buf_size,
342 DMA_FROM_DEVICE);
343 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
344 goto no_rx_mem;
345 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
346
347 if (eth->soc->rx_sg_dma)
348 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
349 else
350 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
351 }
352 ring->rx_calc_idx = ring->rx_ring_size - 1;
353
354
355
356 wmb();
357
358 return 0;
359
360no_rx_mem:
361 return -ENOMEM;
362}
363
364static void mtk_txd_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
365{
366 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
367 dma_unmap_single(dev,
368 dma_unmap_addr(tx_buf, dma_addr0),
369 dma_unmap_len(tx_buf, dma_len0),
370 DMA_TO_DEVICE);
371 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
372 dma_unmap_page(dev,
373 dma_unmap_addr(tx_buf, dma_addr0),
374 dma_unmap_len(tx_buf, dma_len0),
375 DMA_TO_DEVICE);
376 }
377 if (tx_buf->flags & MTK_TX_FLAGS_PAGE1)
378 dma_unmap_page(dev,
379 dma_unmap_addr(tx_buf, dma_addr1),
380 dma_unmap_len(tx_buf, dma_len1),
381 DMA_TO_DEVICE);
382
383 tx_buf->flags = 0;
384 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
385 dev_kfree_skb_any(tx_buf->skb);
386 tx_buf->skb = NULL;
387}
388
389static void mtk_pdma_tx_clean(struct mtk_eth *eth)
390{
391 struct mtk_tx_ring *ring = ð->tx_ring;
392 int i;
393
394 if (ring->tx_buf) {
395 for (i = 0; i < ring->tx_ring_size; i++)
396 mtk_txd_unmap(eth->dev, &ring->tx_buf[i]);
397 kfree(ring->tx_buf);
398 ring->tx_buf = NULL;
399 }
400
401 if (ring->tx_dma) {
402 dma_free_coherent(eth->dev,
403 ring->tx_ring_size * sizeof(*ring->tx_dma),
404 ring->tx_dma,
405 ring->tx_phys);
406 ring->tx_dma = NULL;
407 }
408}
409
410static void mtk_qdma_tx_clean(struct mtk_eth *eth)
411{
412 struct mtk_tx_ring *ring = ð->tx_ring;
413 int i;
414
415 if (ring->tx_buf) {
416 for (i = 0; i < ring->tx_ring_size; i++)
417 mtk_txd_unmap(eth->dev, &ring->tx_buf[i]);
418 kfree(ring->tx_buf);
419 ring->tx_buf = NULL;
420 }
421
422 if (ring->tx_dma) {
423 dma_free_coherent(eth->dev,
424 ring->tx_ring_size * sizeof(*ring->tx_dma),
425 ring->tx_dma,
426 ring->tx_phys);
427 ring->tx_dma = NULL;
428 }
429}
430
431void mtk_stats_update_mac(struct mtk_mac *mac)
432{
433 struct mtk_hw_stats *hw_stats = mac->hw_stats;
434 unsigned int base = mtk_reg_table[MTK_REG_MTK_COUNTER_BASE];
435 u64 stats;
436
437 base += hw_stats->reg_offset;
438
439 u64_stats_update_begin(&hw_stats->syncp);
440
441 if (mac->hw->soc->new_stats) {
442 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
443 stats = mtk_r32(mac->hw, base + 0x04);
444 if (stats)
445 hw_stats->rx_bytes += (stats << 32);
446 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
447 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
448 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
449 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
450 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
451 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
452 hw_stats->rx_flow_control_packets +=
453 mtk_r32(mac->hw, base + 0x24);
454 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
455 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
456 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
457 stats = mtk_r32(mac->hw, base + 0x34);
458 if (stats)
459 hw_stats->tx_bytes += (stats << 32);
460 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
461 } else {
462 hw_stats->tx_bytes += mtk_r32(mac->hw, base);
463 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x04);
464 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x08);
465 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x0c);
466 hw_stats->rx_bytes += mtk_r32(mac->hw, base + 0x20);
467 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x24);
468 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x28);
469 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x2c);
470 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x30);
471 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x34);
472 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x38);
473 hw_stats->rx_flow_control_packets +=
474 mtk_r32(mac->hw, base + 0x3c);
475 }
476
477 u64_stats_update_end(&hw_stats->syncp);
478}
479
480static void mtk_get_stats64(struct net_device *dev,
481 struct rtnl_link_stats64 *storage)
482{
483 struct mtk_mac *mac = netdev_priv(dev);
484 struct mtk_hw_stats *hw_stats = mac->hw_stats;
485 unsigned int base = mtk_reg_table[MTK_REG_MTK_COUNTER_BASE];
486 unsigned int start;
487
488 if (!base) {
489 netdev_stats_to_stats64(storage, &dev->stats);
490 return;
491 }
492
493 if (netif_running(dev) && netif_device_present(dev)) {
494 if (spin_trylock(&hw_stats->stats_lock)) {
495 mtk_stats_update_mac(mac);
496 spin_unlock(&hw_stats->stats_lock);
497 }
498 }
499
500 do {
501 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
502 storage->rx_packets = hw_stats->rx_packets;
503 storage->tx_packets = hw_stats->tx_packets;
504 storage->rx_bytes = hw_stats->rx_bytes;
505 storage->tx_bytes = hw_stats->tx_bytes;
506 storage->collisions = hw_stats->tx_collisions;
507 storage->rx_length_errors = hw_stats->rx_short_errors +
508 hw_stats->rx_long_errors;
509 storage->rx_over_errors = hw_stats->rx_overflow;
510 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
511 storage->rx_errors = hw_stats->rx_checksum_errors;
512 storage->tx_aborted_errors = hw_stats->tx_skip;
513 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
514
515 storage->tx_errors = dev->stats.tx_errors;
516 storage->rx_dropped = dev->stats.rx_dropped;
517 storage->tx_dropped = dev->stats.tx_dropped;
518}
519
520static int mtk_vlan_rx_add_vid(struct net_device *dev,
521 __be16 proto, u16 vid)
522{
523 struct mtk_mac *mac = netdev_priv(dev);
524 struct mtk_eth *eth = mac->hw;
525 u32 idx = (vid & 0xf);
526 u32 vlan_cfg;
527
528 if (!((mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE]) &&
529 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
530 return 0;
531
532 if (test_bit(idx, ð->vlan_map)) {
533 netdev_warn(dev, "disable tx vlan offload\n");
534 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
535 netdev_update_features(dev);
536 } else {
537 vlan_cfg = mtk_r32(eth,
538 mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
539 ((idx >> 1) << 2));
540 if (idx & 0x1) {
541 vlan_cfg &= 0xffff;
542 vlan_cfg |= (vid << 16);
543 } else {
544 vlan_cfg &= 0xffff0000;
545 vlan_cfg |= vid;
546 }
547 mtk_w32(eth,
548 vlan_cfg, mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
549 ((idx >> 1) << 2));
550 set_bit(idx, ð->vlan_map);
551 }
552
553 return 0;
554}
555
556static int mtk_vlan_rx_kill_vid(struct net_device *dev,
557 __be16 proto, u16 vid)
558{
559 struct mtk_mac *mac = netdev_priv(dev);
560 struct mtk_eth *eth = mac->hw;
561 u32 idx = (vid & 0xf);
562
563 if (!((mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE]) &&
564 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
565 return 0;
566
567 clear_bit(idx, ð->vlan_map);
568
569 return 0;
570}
571
572static inline u32 mtk_pdma_empty_txd(struct mtk_tx_ring *ring)
573{
574 barrier();
575 return (u32)(ring->tx_ring_size -
576 ((ring->tx_next_idx - ring->tx_free_idx) &
577 (ring->tx_ring_size - 1)));
578}
579
580static int mtk_skb_padto(struct sk_buff *skb, struct mtk_eth *eth)
581{
582 unsigned int len;
583 int ret;
584
585 if (unlikely(skb->len >= VLAN_ETH_ZLEN))
586 return 0;
587
588 if (eth->soc->padding_64b && !eth->soc->padding_bug)
589 return 0;
590
591 if (skb_vlan_tag_present(skb))
592 len = ETH_ZLEN;
593 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
594 len = VLAN_ETH_ZLEN;
595 else if (!eth->soc->padding_64b)
596 len = ETH_ZLEN;
597 else
598 return 0;
599
600 if (skb->len >= len)
601 return 0;
602
603 ret = skb_pad(skb, len - skb->len);
604 if (ret < 0)
605 return ret;
606 skb->len = len;
607 skb_set_tail_pointer(skb, len);
608
609 return ret;
610}
611
612static int mtk_pdma_tx_map(struct sk_buff *skb, struct net_device *dev,
613 int tx_num, struct mtk_tx_ring *ring, bool gso)
614{
615 struct mtk_mac *mac = netdev_priv(dev);
616 struct mtk_eth *eth = mac->hw;
617 struct skb_frag_struct *frag;
618 struct mtk_tx_dma txd, *ptxd;
619 struct mtk_tx_buf *tx_buf;
620 int i, j, k, frag_size, frag_map_size, offset;
621 dma_addr_t mapped_addr;
622 unsigned int nr_frags;
623 u32 def_txd4;
624
625 if (mtk_skb_padto(skb, eth)) {
626 netif_warn(eth, tx_err, dev, "tx padding failed!\n");
627 return -1;
628 }
629
630 tx_buf = &ring->tx_buf[ring->tx_next_idx];
631 memset(tx_buf, 0, sizeof(*tx_buf));
632 memset(&txd, 0, sizeof(txd));
633 nr_frags = skb_shinfo(skb)->nr_frags;
634
635
636 def_txd4 = eth->soc->txd4;
637 txd.txd4 = def_txd4;
638
639 if (eth->soc->mac_count > 1)
640 txd.txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
641
642 if (gso)
643 txd.txd4 |= TX_DMA_TSO;
644
645
646 if (skb->ip_summed == CHECKSUM_PARTIAL)
647 txd.txd4 |= TX_DMA_CHKSUM;
648
649
650 if (skb_vlan_tag_present(skb)) {
651 u16 tag = skb_vlan_tag_get(skb);
652
653 txd.txd4 |= TX_DMA_INS_VLAN |
654 ((tag >> VLAN_PRIO_SHIFT) << 4) |
655 (tag & 0xF);
656 }
657
658 mapped_addr = dma_map_single(&dev->dev, skb->data,
659 skb_headlen(skb), DMA_TO_DEVICE);
660 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
661 return -1;
662
663 txd.txd1 = mapped_addr;
664 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
665
666 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
667 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
668 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
669
670
671 j = ring->tx_next_idx;
672 k = 0;
673 for (i = 0; i < nr_frags; i++) {
674 offset = 0;
675 frag = &skb_shinfo(skb)->frags[i];
676 frag_size = skb_frag_size(frag);
677
678 while (frag_size > 0) {
679 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
680 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
681 frag_map_size,
682 DMA_TO_DEVICE);
683 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
684 goto err_dma;
685
686 if (k & 0x1) {
687 j = NEXT_TX_DESP_IDX(j);
688 txd.txd1 = mapped_addr;
689 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
690 txd.txd4 = def_txd4;
691
692 tx_buf = &ring->tx_buf[j];
693 memset(tx_buf, 0, sizeof(*tx_buf));
694
695 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
696 dma_unmap_addr_set(tx_buf, dma_addr0,
697 mapped_addr);
698 dma_unmap_len_set(tx_buf, dma_len0,
699 frag_map_size);
700 } else {
701 txd.txd3 = mapped_addr;
702 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
703
704 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
705 tx_buf->flags |= MTK_TX_FLAGS_PAGE1;
706 dma_unmap_addr_set(tx_buf, dma_addr1,
707 mapped_addr);
708 dma_unmap_len_set(tx_buf, dma_len1,
709 frag_map_size);
710
711 if (!((i == (nr_frags - 1)) &&
712 (frag_map_size == frag_size))) {
713 mtk_set_txd_pdma(&txd,
714 &ring->tx_dma[j]);
715 memset(&txd, 0, sizeof(txd));
716 }
717 }
718 frag_size -= frag_map_size;
719 offset += frag_map_size;
720 k++;
721 }
722 }
723
724
725 if (k & 0x1)
726 txd.txd2 |= TX_DMA_LS1;
727 else
728 txd.txd2 |= TX_DMA_LS0;
729 mtk_set_txd_pdma(&txd, &ring->tx_dma[j]);
730
731
732 tx_buf->skb = skb;
733
734 netdev_sent_queue(dev, skb->len);
735 skb_tx_timestamp(skb);
736
737 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
738
739
740
741 wmb();
742 atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
743
744 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
745 mtk_reg_w32(eth, ring->tx_next_idx, MTK_REG_TX_CTX_IDX0);
746
747 return 0;
748
749err_dma:
750 j = ring->tx_next_idx;
751 for (i = 0; i < tx_num; i++) {
752 ptxd = &ring->tx_dma[j];
753 tx_buf = &ring->tx_buf[j];
754
755
756 mtk_txd_unmap(&dev->dev, tx_buf);
757
758 ptxd->txd2 = TX_DMA_DESP2_DEF;
759 j = NEXT_TX_DESP_IDX(j);
760 }
761
762
763
764 wmb();
765 return -1;
766}
767
768
769static int mtk_init_fq_dma(struct mtk_eth *eth)
770{
771 unsigned int phy_ring_head, phy_ring_tail;
772 int cnt = eth->soc->dma_ring_size;
773 dma_addr_t dma_addr;
774 int i;
775
776 eth->scratch_ring = dma_alloc_coherent(eth->dev,
777 cnt * sizeof(struct mtk_tx_dma),
778 &phy_ring_head,
779 GFP_ATOMIC | __GFP_ZERO);
780 if (unlikely(!eth->scratch_ring))
781 return -ENOMEM;
782
783 eth->scratch_head = kcalloc(cnt, QDMA_PAGE_SIZE,
784 GFP_KERNEL);
785 dma_addr = dma_map_single(eth->dev,
786 eth->scratch_head, cnt * QDMA_PAGE_SIZE,
787 DMA_FROM_DEVICE);
788 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
789 return -ENOMEM;
790
791 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
792 phy_ring_tail = phy_ring_head + (sizeof(struct mtk_tx_dma) * (cnt - 1));
793
794 for (i = 0; i < cnt; i++) {
795 eth->scratch_ring[i].txd1 = (dma_addr + (i * QDMA_PAGE_SIZE));
796 if (i < cnt - 1)
797 eth->scratch_ring[i].txd2 = (phy_ring_head +
798 ((i + 1) * sizeof(struct mtk_tx_dma)));
799 eth->scratch_ring[i].txd3 = TX_QDMA_SDL(QDMA_PAGE_SIZE);
800 }
801
802 mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
803 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
804 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
805 mtk_w32(eth, QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
806
807 return 0;
808}
809
810static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
811{
812 void *ret = ring->tx_dma;
813
814 return ret + (desc - ring->tx_phys);
815}
816
817static struct mtk_tx_dma *mtk_tx_next_qdma(struct mtk_tx_ring *ring,
818 struct mtk_tx_dma *txd)
819{
820 return mtk_qdma_phys_to_virt(ring, txd->txd2);
821}
822
823static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
824 struct mtk_tx_dma *txd)
825{
826 int idx = txd - ring->tx_dma;
827
828 return &ring->tx_buf[idx];
829}
830
831static int mtk_qdma_tx_map(struct sk_buff *skb, struct net_device *dev,
832 int tx_num, struct mtk_tx_ring *ring, bool gso)
833{
834 struct mtk_mac *mac = netdev_priv(dev);
835 struct mtk_eth *eth = mac->hw;
836 struct mtk_tx_dma *itxd, *txd;
837 struct mtk_tx_buf *tx_buf;
838 dma_addr_t mapped_addr;
839 unsigned int nr_frags;
840 int i, n_desc = 1;
841 u32 txd4 = eth->soc->txd4;
842
843 itxd = ring->tx_next_free;
844 if (itxd == ring->tx_last_free)
845 return -ENOMEM;
846
847 if (eth->soc->mac_count > 1)
848 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
849
850 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
851 memset(tx_buf, 0, sizeof(*tx_buf));
852
853 if (gso)
854 txd4 |= TX_DMA_TSO;
855
856
857 if (skb->ip_summed == CHECKSUM_PARTIAL)
858 txd4 |= TX_DMA_CHKSUM;
859
860
861 if (skb_vlan_tag_present(skb))
862 txd4 |= TX_DMA_INS_VLAN_MT7621 | skb_vlan_tag_get(skb);
863
864 mapped_addr = dma_map_single(&dev->dev, skb->data,
865 skb_headlen(skb), DMA_TO_DEVICE);
866 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
867 return -ENOMEM;
868
869 WRITE_ONCE(itxd->txd1, mapped_addr);
870 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
871 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
872 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
873
874
875 txd = itxd;
876 nr_frags = skb_shinfo(skb)->nr_frags;
877 for (i = 0; i < nr_frags; i++) {
878 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
879 unsigned int offset = 0;
880 int frag_size = skb_frag_size(frag);
881
882 while (frag_size) {
883 bool last_frag = false;
884 unsigned int frag_map_size;
885
886 txd = mtk_tx_next_qdma(ring, txd);
887 if (txd == ring->tx_last_free)
888 goto err_dma;
889
890 n_desc++;
891 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
892 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
893 frag_map_size,
894 DMA_TO_DEVICE);
895 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
896 goto err_dma;
897
898 if (i == nr_frags - 1 &&
899 (frag_size - frag_map_size) == 0)
900 last_frag = true;
901
902 WRITE_ONCE(txd->txd1, mapped_addr);
903 WRITE_ONCE(txd->txd3, (QDMA_TX_SWC |
904 TX_DMA_PLEN0(frag_map_size) |
905 last_frag * TX_DMA_LS0) |
906 mac->id);
907 WRITE_ONCE(txd->txd4, 0);
908
909 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
910 tx_buf = mtk_desc_to_tx_buf(ring, txd);
911 memset(tx_buf, 0, sizeof(*tx_buf));
912
913 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
914 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
915 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
916 frag_size -= frag_map_size;
917 offset += frag_map_size;
918 }
919 }
920
921
922 tx_buf->skb = skb;
923
924 WRITE_ONCE(itxd->txd4, txd4);
925 WRITE_ONCE(itxd->txd3, (QDMA_TX_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
926 (!nr_frags * TX_DMA_LS0)));
927
928 netdev_sent_queue(dev, skb->len);
929 skb_tx_timestamp(skb);
930
931 ring->tx_next_free = mtk_tx_next_qdma(ring, txd);
932 atomic_sub(n_desc, &ring->tx_free_count);
933
934
935
936
937 wmb();
938
939 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
940 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
941
942 return 0;
943
944err_dma:
945 do {
946 tx_buf = mtk_desc_to_tx_buf(ring, txd);
947
948
949 mtk_txd_unmap(&dev->dev, tx_buf);
950
951 itxd->txd3 = TX_DMA_DESP2_DEF;
952 itxd = mtk_tx_next_qdma(ring, itxd);
953 } while (itxd != txd);
954
955 return -ENOMEM;
956}
957
958static inline int mtk_cal_txd_req(struct sk_buff *skb)
959{
960 int i, nfrags;
961 struct skb_frag_struct *frag;
962
963 nfrags = 1;
964 if (skb_is_gso(skb)) {
965 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
966 frag = &skb_shinfo(skb)->frags[i];
967 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
968 }
969 } else {
970 nfrags += skb_shinfo(skb)->nr_frags;
971 }
972
973 return DIV_ROUND_UP(nfrags, 2);
974}
975
976static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
977{
978 struct mtk_mac *mac = netdev_priv(dev);
979 struct mtk_eth *eth = mac->hw;
980 struct mtk_tx_ring *ring = ð->tx_ring;
981 struct net_device_stats *stats = &dev->stats;
982 int tx_num;
983 int len = skb->len;
984 bool gso = false;
985
986 tx_num = mtk_cal_txd_req(skb);
987 if (unlikely(atomic_read(&ring->tx_free_count) <= tx_num)) {
988 netif_stop_queue(dev);
989 netif_err(eth, tx_queued, dev,
990 "Tx Ring full when queue awake!\n");
991 return NETDEV_TX_BUSY;
992 }
993
994
995 if (skb_is_gso(skb)) {
996 if (skb_cow_head(skb, 0)) {
997 netif_warn(eth, tx_err, dev,
998 "GSO expand head fail.\n");
999 goto drop;
1000 }
1001
1002 if (skb_shinfo(skb)->gso_type &
1003 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1004 gso = true;
1005 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1006 }
1007 }
1008
1009 if (ring->tx_map(skb, dev, tx_num, ring, gso) < 0)
1010 goto drop;
1011
1012 stats->tx_packets++;
1013 stats->tx_bytes += len;
1014
1015 if (unlikely(atomic_read(&ring->tx_free_count) <= ring->tx_thresh)) {
1016 netif_stop_queue(dev);
1017 smp_mb();
1018 if (unlikely(atomic_read(&ring->tx_free_count) >
1019 ring->tx_thresh))
1020 netif_wake_queue(dev);
1021 }
1022
1023 return NETDEV_TX_OK;
1024
1025drop:
1026 stats->tx_dropped++;
1027 dev_kfree_skb(skb);
1028 return NETDEV_TX_OK;
1029}
1030
1031static int mtk_poll_rx(struct napi_struct *napi, int budget,
1032 struct mtk_eth *eth, u32 rx_intr)
1033{
1034 struct mtk_soc_data *soc = eth->soc;
1035 struct mtk_rx_ring *ring = ð->rx_ring[0];
1036 int idx = ring->rx_calc_idx;
1037 u32 checksum_bit;
1038 struct sk_buff *skb;
1039 u8 *data, *new_data;
1040 struct mtk_rx_dma *rxd, trxd;
1041 int done = 0, pad;
1042
1043 if (eth->soc->hw_features & NETIF_F_RXCSUM)
1044 checksum_bit = soc->checksum_bit;
1045 else
1046 checksum_bit = 0;
1047
1048 if (eth->soc->rx_2b_offset)
1049 pad = 0;
1050 else
1051 pad = NET_IP_ALIGN;
1052
1053 while (done < budget) {
1054 struct net_device *netdev;
1055 unsigned int pktlen;
1056 dma_addr_t dma_addr;
1057 int mac = 0;
1058
1059 idx = NEXT_RX_DESP_IDX(idx);
1060 rxd = &ring->rx_dma[idx];
1061 data = ring->rx_data[idx];
1062
1063 mtk_get_rxd(&trxd, rxd);
1064 if (!(trxd.rxd2 & RX_DMA_DONE))
1065 break;
1066
1067
1068 if (eth->soc->mac_count > 1) {
1069 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
1070 RX_DMA_FPORT_MASK;
1071 mac--;
1072 if (mac < 0 || mac >= eth->soc->mac_count)
1073 goto release_desc;
1074 }
1075
1076 netdev = eth->netdev[mac];
1077
1078
1079 new_data = napi_alloc_frag(ring->frag_size);
1080 if (unlikely(!new_data || !netdev)) {
1081 netdev->stats.rx_dropped++;
1082 goto release_desc;
1083 }
1084 dma_addr = dma_map_single(&netdev->dev,
1085 new_data + NET_SKB_PAD + pad,
1086 ring->rx_buf_size,
1087 DMA_FROM_DEVICE);
1088 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
1089 skb_free_frag(new_data);
1090 goto release_desc;
1091 }
1092
1093
1094 skb = build_skb(data, ring->frag_size);
1095 if (unlikely(!skb)) {
1096 put_page(virt_to_head_page(new_data));
1097 goto release_desc;
1098 }
1099 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1100
1101 dma_unmap_single(&netdev->dev, trxd.rxd1,
1102 ring->rx_buf_size, DMA_FROM_DEVICE);
1103 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1104 skb->dev = netdev;
1105 skb_put(skb, pktlen);
1106 if (trxd.rxd4 & checksum_bit)
1107 skb->ip_summed = CHECKSUM_UNNECESSARY;
1108 else
1109 skb_checksum_none_assert(skb);
1110 skb->protocol = eth_type_trans(skb, netdev);
1111
1112 netdev->stats.rx_packets++;
1113 netdev->stats.rx_bytes += pktlen;
1114
1115 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1116 RX_DMA_VID(trxd.rxd3))
1117 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1118 RX_DMA_VID(trxd.rxd3));
1119 napi_gro_receive(napi, skb);
1120
1121 ring->rx_data[idx] = new_data;
1122 rxd->rxd1 = (unsigned int)dma_addr;
1123
1124release_desc:
1125 if (eth->soc->rx_sg_dma)
1126 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
1127 else
1128 rxd->rxd2 = RX_DMA_LSO;
1129
1130 ring->rx_calc_idx = idx;
1131
1132
1133
1134 wmb();
1135 if (eth->soc->dma_type == MTK_QDMA)
1136 mtk_w32(eth, ring->rx_calc_idx, MTK_QRX_CRX_IDX0);
1137 else
1138 mtk_reg_w32(eth, ring->rx_calc_idx,
1139 MTK_REG_RX_CALC_IDX0);
1140 done++;
1141 }
1142
1143 if (done < budget)
1144 mtk_irq_ack(eth, rx_intr);
1145
1146 return done;
1147}
1148
1149static int mtk_pdma_tx_poll(struct mtk_eth *eth, int budget, bool *tx_again)
1150{
1151 struct sk_buff *skb;
1152 struct mtk_tx_buf *tx_buf;
1153 int done = 0;
1154 u32 idx, hwidx;
1155 struct mtk_tx_ring *ring = ð->tx_ring;
1156 unsigned int bytes = 0;
1157
1158 idx = ring->tx_free_idx;
1159 hwidx = mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0);
1160
1161 while ((idx != hwidx) && budget) {
1162 tx_buf = &ring->tx_buf[idx];
1163 skb = tx_buf->skb;
1164
1165 if (!skb)
1166 break;
1167
1168 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
1169 bytes += skb->len;
1170 done++;
1171 budget--;
1172 }
1173 mtk_txd_unmap(eth->dev, tx_buf);
1174 idx = NEXT_TX_DESP_IDX(idx);
1175 }
1176 ring->tx_free_idx = idx;
1177 atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
1178
1179
1180 if (idx != hwidx || idx != mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0))
1181 *tx_again = 1;
1182
1183 if (done)
1184 netdev_completed_queue(*eth->netdev, done, bytes);
1185
1186 return done;
1187}
1188
1189static int mtk_qdma_tx_poll(struct mtk_eth *eth, int budget, bool *tx_again)
1190{
1191 struct mtk_tx_ring *ring = ð->tx_ring;
1192 struct mtk_tx_dma *desc;
1193 struct sk_buff *skb;
1194 struct mtk_tx_buf *tx_buf;
1195 int total = 0, done[MTK_MAX_DEVS];
1196 unsigned int bytes[MTK_MAX_DEVS];
1197 u32 cpu, dma;
1198 static int condition;
1199 int i;
1200
1201 memset(done, 0, sizeof(done));
1202 memset(bytes, 0, sizeof(bytes));
1203
1204 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1205 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1206
1207 desc = mtk_qdma_phys_to_virt(ring, cpu);
1208
1209 while ((cpu != dma) && budget) {
1210 u32 next_cpu = desc->txd2;
1211 int mac;
1212
1213 desc = mtk_tx_next_qdma(ring, desc);
1214 if ((desc->txd3 & QDMA_TX_OWNER_CPU) == 0)
1215 break;
1216
1217 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
1218 TX_DMA_FPORT_MASK;
1219 mac--;
1220
1221 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1222 skb = tx_buf->skb;
1223 if (!skb) {
1224 condition = 1;
1225 break;
1226 }
1227
1228 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
1229 bytes[mac] += skb->len;
1230 done[mac]++;
1231 budget--;
1232 }
1233 mtk_txd_unmap(eth->dev, tx_buf);
1234
1235 ring->tx_last_free->txd2 = next_cpu;
1236 ring->tx_last_free = desc;
1237 atomic_inc(&ring->tx_free_count);
1238
1239 cpu = next_cpu;
1240 }
1241
1242 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1243
1244
1245 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
1246 *tx_again = true;
1247
1248 for (i = 0; i < eth->soc->mac_count; i++) {
1249 if (!done[i])
1250 continue;
1251 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1252 total += done[i];
1253 }
1254
1255 return total;
1256}
1257
1258static int mtk_poll_tx(struct mtk_eth *eth, int budget, u32 tx_intr,
1259 bool *tx_again)
1260{
1261 struct mtk_tx_ring *ring = ð->tx_ring;
1262 struct net_device *netdev = eth->netdev[0];
1263 int done;
1264
1265 done = eth->tx_ring.tx_poll(eth, budget, tx_again);
1266 if (!*tx_again)
1267 mtk_irq_ack(eth, tx_intr);
1268
1269 if (!done)
1270 return 0;
1271
1272 smp_mb();
1273 if (unlikely(!netif_queue_stopped(netdev)))
1274 return done;
1275
1276 if (atomic_read(&ring->tx_free_count) > ring->tx_thresh)
1277 netif_wake_queue(netdev);
1278
1279 return done;
1280}
1281
1282static void mtk_stats_update(struct mtk_eth *eth)
1283{
1284 int i;
1285
1286 for (i = 0; i < eth->soc->mac_count; i++) {
1287 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
1288 continue;
1289 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
1290 mtk_stats_update_mac(eth->mac[i]);
1291 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
1292 }
1293 }
1294}
1295
1296static int mtk_poll(struct napi_struct *napi, int budget)
1297{
1298 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1299 u32 status, mtk_status, mask, tx_intr, rx_intr, status_intr;
1300 int tx_done, rx_done;
1301 bool tx_again = false;
1302
1303 status = mtk_irq_pending(eth);
1304 mtk_status = mtk_irq_pending_status(eth);
1305 tx_intr = eth->soc->tx_int;
1306 rx_intr = eth->soc->rx_int;
1307 status_intr = eth->soc->status_int;
1308 tx_done = 0;
1309 rx_done = 0;
1310 tx_again = 0;
1311
1312 if (status & tx_intr)
1313 tx_done = mtk_poll_tx(eth, budget, tx_intr, &tx_again);
1314
1315 if (status & rx_intr)
1316 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
1317
1318 if (unlikely(mtk_status & status_intr)) {
1319 mtk_stats_update(eth);
1320 mtk_irq_ack_status(eth, status_intr);
1321 }
1322
1323 if (unlikely(netif_msg_intr(eth))) {
1324 mask = mtk_irq_enabled(eth);
1325 netdev_info(eth->netdev[0],
1326 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1327 tx_done, rx_done, status, mask);
1328 }
1329
1330 if (tx_again || rx_done == budget)
1331 return budget;
1332
1333 status = mtk_irq_pending(eth);
1334 if (status & (tx_intr | rx_intr))
1335 return budget;
1336
1337 napi_complete(napi);
1338 mtk_irq_enable(eth, tx_intr | rx_intr);
1339
1340 return rx_done;
1341}
1342
1343static int mtk_pdma_tx_alloc(struct mtk_eth *eth)
1344{
1345 int i;
1346 struct mtk_tx_ring *ring = ð->tx_ring;
1347
1348 ring->tx_ring_size = eth->soc->dma_ring_size;
1349 ring->tx_free_idx = 0;
1350 ring->tx_next_idx = 0;
1351 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
1352 MAX_SKB_FRAGS);
1353
1354 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
1355 GFP_KERNEL);
1356 if (!ring->tx_buf)
1357 goto no_tx_mem;
1358
1359 ring->tx_dma = dma_alloc_coherent(eth->dev,
1360 ring->tx_ring_size * sizeof(*ring->tx_dma),
1361 &ring->tx_phys,
1362 GFP_ATOMIC | __GFP_ZERO);
1363 if (!ring->tx_dma)
1364 goto no_tx_mem;
1365
1366 for (i = 0; i < ring->tx_ring_size; i++) {
1367 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
1368 ring->tx_dma[i].txd4 = eth->soc->txd4;
1369 }
1370
1371 atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
1372 ring->tx_map = mtk_pdma_tx_map;
1373 ring->tx_poll = mtk_pdma_tx_poll;
1374 ring->tx_clean = mtk_pdma_tx_clean;
1375
1376
1377
1378
1379 wmb();
1380
1381 mtk_reg_w32(eth, ring->tx_phys, MTK_REG_TX_BASE_PTR0);
1382 mtk_reg_w32(eth, ring->tx_ring_size, MTK_REG_TX_MAX_CNT0);
1383 mtk_reg_w32(eth, 0, MTK_REG_TX_CTX_IDX0);
1384 mtk_reg_w32(eth, MTK_PST_DTX_IDX0, MTK_REG_PDMA_RST_CFG);
1385
1386 return 0;
1387
1388no_tx_mem:
1389 return -ENOMEM;
1390}
1391
1392static int mtk_qdma_tx_alloc_tx(struct mtk_eth *eth)
1393{
1394 struct mtk_tx_ring *ring = ð->tx_ring;
1395 int i, sz = sizeof(*ring->tx_dma);
1396
1397 ring->tx_ring_size = eth->soc->dma_ring_size;
1398 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
1399 GFP_KERNEL);
1400 if (!ring->tx_buf)
1401 goto no_tx_mem;
1402
1403 ring->tx_dma = dma_alloc_coherent(eth->dev,
1404 ring->tx_ring_size * sz,
1405 &ring->tx_phys,
1406 GFP_ATOMIC | __GFP_ZERO);
1407 if (!ring->tx_dma)
1408 goto no_tx_mem;
1409
1410 memset(ring->tx_dma, 0, ring->tx_ring_size * sz);
1411 for (i = 0; i < ring->tx_ring_size; i++) {
1412 int next = (i + 1) % ring->tx_ring_size;
1413 u32 next_ptr = ring->tx_phys + next * sz;
1414
1415 ring->tx_dma[i].txd2 = next_ptr;
1416 ring->tx_dma[i].txd3 = TX_DMA_DESP2_DEF;
1417 }
1418
1419 atomic_set(&ring->tx_free_count, ring->tx_ring_size - 2);
1420 ring->tx_next_free = &ring->tx_dma[0];
1421 ring->tx_last_free = &ring->tx_dma[ring->tx_ring_size - 2];
1422 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
1423 MAX_SKB_FRAGS);
1424
1425 ring->tx_map = mtk_qdma_tx_map;
1426 ring->tx_poll = mtk_qdma_tx_poll;
1427 ring->tx_clean = mtk_qdma_tx_clean;
1428
1429
1430
1431
1432 wmb();
1433
1434 mtk_w32(eth, ring->tx_phys, MTK_QTX_CTX_PTR);
1435 mtk_w32(eth, ring->tx_phys, MTK_QTX_DTX_PTR);
1436 mtk_w32(eth,
1437 ring->tx_phys + ((ring->tx_ring_size - 1) * sz),
1438 MTK_QTX_CRX_PTR);
1439 mtk_w32(eth,
1440 ring->tx_phys + ((ring->tx_ring_size - 1) * sz),
1441 MTK_QTX_DRX_PTR);
1442
1443 return 0;
1444
1445no_tx_mem:
1446 return -ENOMEM;
1447}
1448
1449static int mtk_qdma_init(struct mtk_eth *eth, int ring)
1450{
1451 int err;
1452
1453 err = mtk_init_fq_dma(eth);
1454 if (err)
1455 return err;
1456
1457 err = mtk_qdma_tx_alloc_tx(eth);
1458 if (err)
1459 return err;
1460
1461 err = mtk_dma_rx_alloc(eth, ð->rx_ring[ring]);
1462 if (err)
1463 return err;
1464
1465 mtk_w32(eth, eth->rx_ring[ring].rx_phys, MTK_QRX_BASE_PTR0);
1466 mtk_w32(eth, eth->rx_ring[ring].rx_ring_size, MTK_QRX_MAX_CNT0);
1467 mtk_w32(eth, eth->rx_ring[ring].rx_calc_idx, MTK_QRX_CRX_IDX0);
1468 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1469 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1470
1471
1472 mtk_w32(eth, 0x174444, MTK_QDMA_FC_THRES);
1473 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1474
1475 return 0;
1476}
1477
1478static int mtk_pdma_qdma_init(struct mtk_eth *eth)
1479{
1480 int err = mtk_qdma_init(eth, 1);
1481
1482 if (err)
1483 return err;
1484
1485 err = mtk_dma_rx_alloc(eth, ð->rx_ring[0]);
1486 if (err)
1487 return err;
1488
1489 mtk_reg_w32(eth, eth->rx_ring[0].rx_phys, MTK_REG_RX_BASE_PTR0);
1490 mtk_reg_w32(eth, eth->rx_ring[0].rx_ring_size, MTK_REG_RX_MAX_CNT0);
1491 mtk_reg_w32(eth, eth->rx_ring[0].rx_calc_idx, MTK_REG_RX_CALC_IDX0);
1492 mtk_reg_w32(eth, MTK_PST_DRX_IDX0, MTK_REG_PDMA_RST_CFG);
1493
1494 return 0;
1495}
1496
1497static int mtk_pdma_init(struct mtk_eth *eth)
1498{
1499 struct mtk_rx_ring *ring = ð->rx_ring[0];
1500 int err;
1501
1502 err = mtk_pdma_tx_alloc(eth);
1503 if (err)
1504 return err;
1505
1506 err = mtk_dma_rx_alloc(eth, ring);
1507 if (err)
1508 return err;
1509
1510 mtk_reg_w32(eth, ring->rx_phys, MTK_REG_RX_BASE_PTR0);
1511 mtk_reg_w32(eth, ring->rx_ring_size, MTK_REG_RX_MAX_CNT0);
1512 mtk_reg_w32(eth, ring->rx_calc_idx, MTK_REG_RX_CALC_IDX0);
1513 mtk_reg_w32(eth, MTK_PST_DRX_IDX0, MTK_REG_PDMA_RST_CFG);
1514
1515 return 0;
1516}
1517
1518static void mtk_dma_free(struct mtk_eth *eth)
1519{
1520 int i;
1521
1522 for (i = 0; i < eth->soc->mac_count; i++)
1523 if (eth->netdev[i])
1524 netdev_reset_queue(eth->netdev[i]);
1525 eth->tx_ring.tx_clean(eth);
1526 mtk_clean_rx(eth, ð->rx_ring[0]);
1527 mtk_clean_rx(eth, ð->rx_ring[1]);
1528 kfree(eth->scratch_head);
1529}
1530
1531static void mtk_tx_timeout(struct net_device *dev)
1532{
1533 struct mtk_mac *mac = netdev_priv(dev);
1534 struct mtk_eth *eth = mac->hw;
1535 struct mtk_tx_ring *ring = ð->tx_ring;
1536
1537 eth->netdev[mac->id]->stats.tx_errors++;
1538 netif_err(eth, tx_err, dev,
1539 "transmit timed out\n");
1540 if (eth->soc->dma_type & MTK_PDMA) {
1541 netif_info(eth, drv, dev, "pdma_cfg:%08x\n",
1542 mtk_reg_r32(eth, MTK_REG_PDMA_GLO_CFG));
1543 netif_info(eth, drv, dev, "tx_ring=%d, "
1544 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1545 0, mtk_reg_r32(eth, MTK_REG_TX_BASE_PTR0),
1546 mtk_reg_r32(eth, MTK_REG_TX_MAX_CNT0),
1547 mtk_reg_r32(eth, MTK_REG_TX_CTX_IDX0),
1548 mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0),
1549 ring->tx_free_idx,
1550 ring->tx_next_idx);
1551 }
1552 if (eth->soc->dma_type & MTK_QDMA) {
1553 netif_info(eth, drv, dev, "qdma_cfg:%08x\n",
1554 mtk_r32(eth, MTK_QDMA_GLO_CFG));
1555 netif_info(eth, drv, dev, "tx_ring=%d, "
1556 "ctx=%08x, dtx=%08x, crx=%08x, drx=%08x, free=%hu\n",
1557 0, mtk_r32(eth, MTK_QTX_CTX_PTR),
1558 mtk_r32(eth, MTK_QTX_DTX_PTR),
1559 mtk_r32(eth, MTK_QTX_CRX_PTR),
1560 mtk_r32(eth, MTK_QTX_DRX_PTR),
1561 atomic_read(&ring->tx_free_count));
1562 }
1563 netif_info(eth, drv, dev,
1564 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1565 0, mtk_reg_r32(eth, MTK_REG_RX_BASE_PTR0),
1566 mtk_reg_r32(eth, MTK_REG_RX_MAX_CNT0),
1567 mtk_reg_r32(eth, MTK_REG_RX_CALC_IDX0),
1568 mtk_reg_r32(eth, MTK_REG_RX_DRX_IDX0));
1569
1570 schedule_work(&mac->pending_work);
1571}
1572
1573static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1574{
1575 struct mtk_eth *eth = _eth;
1576 u32 status, int_mask;
1577
1578 status = mtk_irq_pending(eth);
1579 if (unlikely(!status))
1580 return IRQ_NONE;
1581
1582 int_mask = (eth->soc->rx_int | eth->soc->tx_int);
1583 if (likely(status & int_mask)) {
1584 if (likely(napi_schedule_prep(ð->rx_napi)))
1585 __napi_schedule(ð->rx_napi);
1586 } else {
1587 mtk_irq_ack(eth, status);
1588 }
1589 mtk_irq_disable(eth, int_mask);
1590
1591 return IRQ_HANDLED;
1592}
1593
1594#ifdef CONFIG_NET_POLL_CONTROLLER
1595static void mtk_poll_controller(struct net_device *dev)
1596{
1597 struct mtk_mac *mac = netdev_priv(dev);
1598 struct mtk_eth *eth = mac->hw;
1599 u32 int_mask = eth->soc->tx_int | eth->soc->rx_int;
1600
1601 mtk_irq_disable(eth, int_mask);
1602 mtk_handle_irq(dev->irq, dev);
1603 mtk_irq_enable(eth, int_mask);
1604}
1605#endif
1606
1607int mtk_set_clock_cycle(struct mtk_eth *eth)
1608{
1609 unsigned long sysclk = eth->sysclk;
1610
1611 sysclk /= MTK_US_CYC_CNT_DIVISOR;
1612 sysclk <<= MTK_US_CYC_CNT_SHIFT;
1613
1614 mtk_w32(eth, (mtk_r32(eth, MTK_GLO_CFG) &
1615 ~(MTK_US_CYC_CNT_MASK << MTK_US_CYC_CNT_SHIFT)) |
1616 sysclk,
1617 MTK_GLO_CFG);
1618 return 0;
1619}
1620
1621void mtk_fwd_config(struct mtk_eth *eth)
1622{
1623 u32 fwd_cfg;
1624
1625 fwd_cfg = mtk_r32(eth, MTK_GDMA1_FWD_CFG);
1626
1627
1628 if (eth->soc->jumbo_frame)
1629 fwd_cfg &= ~MTK_GDM1_JMB_EN;
1630
1631
1632 fwd_cfg &= ~0xffff;
1633
1634 mtk_w32(eth, fwd_cfg, MTK_GDMA1_FWD_CFG);
1635}
1636
1637void mtk_csum_config(struct mtk_eth *eth)
1638{
1639 if (eth->soc->hw_features & NETIF_F_RXCSUM)
1640 mtk_w32(eth, mtk_r32(eth, MTK_GDMA1_FWD_CFG) |
1641 (MTK_GDM1_ICS_EN | MTK_GDM1_TCS_EN | MTK_GDM1_UCS_EN),
1642 MTK_GDMA1_FWD_CFG);
1643 else
1644 mtk_w32(eth, mtk_r32(eth, MTK_GDMA1_FWD_CFG) &
1645 ~(MTK_GDM1_ICS_EN | MTK_GDM1_TCS_EN | MTK_GDM1_UCS_EN),
1646 MTK_GDMA1_FWD_CFG);
1647 if (eth->soc->hw_features & NETIF_F_IP_CSUM)
1648 mtk_w32(eth, mtk_r32(eth, MTK_CDMA_CSG_CFG) |
1649 (MTK_ICS_GEN_EN | MTK_TCS_GEN_EN | MTK_UCS_GEN_EN),
1650 MTK_CDMA_CSG_CFG);
1651 else
1652 mtk_w32(eth, mtk_r32(eth, MTK_CDMA_CSG_CFG) &
1653 ~(MTK_ICS_GEN_EN | MTK_TCS_GEN_EN | MTK_UCS_GEN_EN),
1654 MTK_CDMA_CSG_CFG);
1655}
1656
1657static int mtk_start_dma(struct mtk_eth *eth)
1658{
1659 unsigned long flags;
1660 u32 val;
1661 int err;
1662
1663 if (eth->soc->dma_type == MTK_PDMA)
1664 err = mtk_pdma_init(eth);
1665 else if (eth->soc->dma_type == MTK_QDMA)
1666 err = mtk_qdma_init(eth, 0);
1667 else
1668 err = mtk_pdma_qdma_init(eth);
1669 if (err) {
1670 mtk_dma_free(eth);
1671 return err;
1672 }
1673
1674 spin_lock_irqsave(ð->page_lock, flags);
1675
1676 val = MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN;
1677 if (eth->soc->rx_2b_offset)
1678 val |= MTK_RX_2B_OFFSET;
1679 val |= eth->soc->pdma_glo_cfg;
1680
1681 if (eth->soc->dma_type & MTK_PDMA)
1682 mtk_reg_w32(eth, val, MTK_REG_PDMA_GLO_CFG);
1683
1684 if (eth->soc->dma_type & MTK_QDMA)
1685 mtk_w32(eth, val, MTK_QDMA_GLO_CFG);
1686
1687 spin_unlock_irqrestore(ð->page_lock, flags);
1688
1689 return 0;
1690}
1691
1692static int mtk_open(struct net_device *dev)
1693{
1694 struct mtk_mac *mac = netdev_priv(dev);
1695 struct mtk_eth *eth = mac->hw;
1696
1697 if (!atomic_read(ð->dma_refcnt)) {
1698 int err = mtk_start_dma(eth);
1699
1700 if (err)
1701 return err;
1702
1703 napi_enable(ð->rx_napi);
1704 mtk_irq_enable(eth, eth->soc->tx_int | eth->soc->rx_int);
1705 }
1706 atomic_inc(ð->dma_refcnt);
1707
1708 if (eth->phy)
1709 eth->phy->start(mac);
1710
1711 if (eth->soc->has_carrier && eth->soc->has_carrier(eth))
1712 netif_carrier_on(dev);
1713
1714 netif_start_queue(dev);
1715 eth->soc->fwd_config(eth);
1716
1717 return 0;
1718}
1719
1720static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1721{
1722 unsigned long flags;
1723 u32 val;
1724 int i;
1725
1726
1727 spin_lock_irqsave(ð->page_lock, flags);
1728 val = mtk_r32(eth, glo_cfg);
1729 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1730 glo_cfg);
1731 spin_unlock_irqrestore(ð->page_lock, flags);
1732
1733
1734 for (i = 0; i < 10; i++) {
1735 val = mtk_r32(eth, glo_cfg);
1736 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1737 msleep(20);
1738 continue;
1739 }
1740 break;
1741 }
1742}
1743
1744static int mtk_stop(struct net_device *dev)
1745{
1746 struct mtk_mac *mac = netdev_priv(dev);
1747 struct mtk_eth *eth = mac->hw;
1748
1749 netif_tx_disable(dev);
1750 if (eth->phy)
1751 eth->phy->stop(mac);
1752
1753 if (!atomic_dec_and_test(ð->dma_refcnt))
1754 return 0;
1755
1756 mtk_irq_disable(eth, eth->soc->tx_int | eth->soc->rx_int);
1757 napi_disable(ð->rx_napi);
1758
1759 if (eth->soc->dma_type & MTK_PDMA)
1760 mtk_stop_dma(eth, mtk_reg_table[MTK_REG_PDMA_GLO_CFG]);
1761
1762 if (eth->soc->dma_type & MTK_QDMA)
1763 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1764
1765 mtk_dma_free(eth);
1766
1767 return 0;
1768}
1769
1770static int __init mtk_init_hw(struct mtk_eth *eth)
1771{
1772 int i, err;
1773
1774 eth->soc->reset_fe(eth);
1775
1776 if (eth->soc->switch_init)
1777 if (eth->soc->switch_init(eth)) {
1778 dev_err(eth->dev, "failed to initialize switch core\n");
1779 return -ENODEV;
1780 }
1781
1782 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1783 dev_name(eth->dev), eth);
1784 if (err)
1785 return err;
1786
1787 err = mtk_mdio_init(eth);
1788 if (err)
1789 return err;
1790
1791
1792 mtk_reg_w32(eth, 0, MTK_REG_DLY_INT_CFG);
1793 if (eth->soc->dma_type & MTK_QDMA)
1794 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1795 mtk_irq_disable(eth, eth->soc->tx_int | eth->soc->rx_int);
1796
1797
1798 if (mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE])
1799 for (i = 0; i < 16; i += 2)
1800 mtk_w32(eth, ((i + 1) << 16) + i,
1801 mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
1802 (i * 2));
1803
1804 if (eth->soc->fwd_config(eth))
1805 dev_err(eth->dev, "unable to get clock\n");
1806
1807 if (mtk_reg_table[MTK_REG_MTK_RST_GL]) {
1808 mtk_reg_w32(eth, 1, MTK_REG_MTK_RST_GL);
1809 mtk_reg_w32(eth, 0, MTK_REG_MTK_RST_GL);
1810 }
1811
1812 return 0;
1813}
1814
1815static int __init mtk_init(struct net_device *dev)
1816{
1817 struct mtk_mac *mac = netdev_priv(dev);
1818 struct mtk_eth *eth = mac->hw;
1819 struct device_node *port;
1820 const char *mac_addr;
1821 int err;
1822
1823 mac_addr = of_get_mac_address(mac->of_node);
1824 if (mac_addr)
1825 ether_addr_copy(dev->dev_addr, mac_addr);
1826
1827
1828 if (!is_valid_ether_addr(dev->dev_addr)) {
1829 random_ether_addr(dev->dev_addr);
1830 dev_err(eth->dev, "generated random MAC address %pM\n",
1831 dev->dev_addr);
1832 dev->addr_assign_type = NET_ADDR_RANDOM;
1833 }
1834 mac->hw->soc->set_mac(mac, dev->dev_addr);
1835
1836 if (eth->soc->port_init)
1837 for_each_child_of_node(mac->of_node, port)
1838 if (of_device_is_compatible(port,
1839 "mediatek,eth-port") &&
1840 of_device_is_available(port))
1841 eth->soc->port_init(eth, mac, port);
1842
1843 if (eth->phy) {
1844 err = eth->phy->connect(mac);
1845 if (err)
1846 return err;
1847 }
1848
1849 return 0;
1850}
1851
1852static void mtk_uninit(struct net_device *dev)
1853{
1854 struct mtk_mac *mac = netdev_priv(dev);
1855 struct mtk_eth *eth = mac->hw;
1856
1857 if (eth->phy)
1858 eth->phy->disconnect(mac);
1859 mtk_mdio_cleanup(eth);
1860
1861 mtk_irq_disable(eth, ~0);
1862 free_irq(dev->irq, dev);
1863}
1864
1865static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1866{
1867 struct mtk_mac *mac = netdev_priv(dev);
1868
1869 if (!mac->phy_dev)
1870 return -ENODEV;
1871
1872 switch (cmd) {
1873 case SIOCGMIIPHY:
1874 case SIOCGMIIREG:
1875 case SIOCSMIIREG:
1876 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1877 default:
1878 break;
1879 }
1880
1881 return -EOPNOTSUPP;
1882}
1883
1884static int mtk_change_mtu(struct net_device *dev, int new_mtu)
1885{
1886 struct mtk_mac *mac = netdev_priv(dev);
1887 struct mtk_eth *eth = mac->hw;
1888 int frag_size, old_mtu;
1889 u32 fwd_cfg;
1890
1891 if (!eth->soc->jumbo_frame)
1892 return eth_change_mtu(dev, new_mtu);
1893
1894 frag_size = mtk_max_frag_size(new_mtu);
1895 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1896 return -EINVAL;
1897
1898 old_mtu = dev->mtu;
1899 dev->mtu = new_mtu;
1900
1901
1902 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1903 return 0;
1904 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1905 return 0;
1906
1907 if (new_mtu <= ETH_DATA_LEN)
1908 eth->rx_ring[0].frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1909 else
1910 eth->rx_ring[0].frag_size = PAGE_SIZE;
1911 eth->rx_ring[0].rx_buf_size =
1912 mtk_max_buf_size(eth->rx_ring[0].frag_size);
1913
1914 if (!netif_running(dev))
1915 return 0;
1916
1917 mtk_stop(dev);
1918 fwd_cfg = mtk_r32(eth, MTK_GDMA1_FWD_CFG);
1919 if (new_mtu <= ETH_DATA_LEN) {
1920 fwd_cfg &= ~MTK_GDM1_JMB_EN;
1921 } else {
1922 fwd_cfg &= ~(MTK_GDM1_JMB_LEN_MASK << MTK_GDM1_JMB_LEN_SHIFT);
1923 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1924 MTK_GDM1_JMB_LEN_SHIFT) | MTK_GDM1_JMB_EN;
1925 }
1926 mtk_w32(eth, fwd_cfg, MTK_GDMA1_FWD_CFG);
1927
1928 return mtk_open(dev);
1929}
1930
1931static void mtk_pending_work(struct work_struct *work)
1932{
1933 struct mtk_mac *mac = container_of(work, struct mtk_mac, pending_work);
1934 struct mtk_eth *eth = mac->hw;
1935 struct net_device *dev = eth->netdev[mac->id];
1936 int err;
1937
1938 rtnl_lock();
1939 mtk_stop(dev);
1940
1941 err = mtk_open(dev);
1942 if (err) {
1943 netif_alert(eth, ifup, dev,
1944 "Driver up/down cycle failed, closing device.\n");
1945 dev_close(dev);
1946 }
1947 rtnl_unlock();
1948}
1949
1950static int mtk_cleanup(struct mtk_eth *eth)
1951{
1952 int i;
1953
1954 for (i = 0; i < eth->soc->mac_count; i++) {
1955 struct mtk_mac *mac = netdev_priv(eth->netdev[i]);
1956
1957 if (!eth->netdev[i])
1958 continue;
1959
1960 unregister_netdev(eth->netdev[i]);
1961 free_netdev(eth->netdev[i]);
1962 cancel_work_sync(&mac->pending_work);
1963 }
1964
1965 return 0;
1966}
1967
1968static const struct net_device_ops mtk_netdev_ops = {
1969 .ndo_init = mtk_init,
1970 .ndo_uninit = mtk_uninit,
1971 .ndo_open = mtk_open,
1972 .ndo_stop = mtk_stop,
1973 .ndo_start_xmit = mtk_start_xmit,
1974 .ndo_set_mac_address = mtk_set_mac_address,
1975 .ndo_validate_addr = eth_validate_addr,
1976 .ndo_do_ioctl = mtk_do_ioctl,
1977 .ndo_change_mtu = mtk_change_mtu,
1978 .ndo_tx_timeout = mtk_tx_timeout,
1979 .ndo_get_stats64 = mtk_get_stats64,
1980 .ndo_vlan_rx_add_vid = mtk_vlan_rx_add_vid,
1981 .ndo_vlan_rx_kill_vid = mtk_vlan_rx_kill_vid,
1982#ifdef CONFIG_NET_POLL_CONTROLLER
1983 .ndo_poll_controller = mtk_poll_controller,
1984#endif
1985};
1986
1987static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1988{
1989 struct mtk_mac *mac;
1990 const __be32 *_id = of_get_property(np, "reg", NULL);
1991 int id, err;
1992
1993 if (!_id) {
1994 dev_err(eth->dev, "missing mac id\n");
1995 return -EINVAL;
1996 }
1997 id = be32_to_cpup(_id);
1998 if (id >= eth->soc->mac_count || eth->netdev[id]) {
1999 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2000 return -EINVAL;
2001 }
2002
2003 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2004 if (!eth->netdev[id]) {
2005 dev_err(eth->dev, "alloc_etherdev failed\n");
2006 return -ENOMEM;
2007 }
2008 mac = netdev_priv(eth->netdev[id]);
2009 eth->mac[id] = mac;
2010 mac->id = id;
2011 mac->hw = eth;
2012 mac->of_node = np;
2013 INIT_WORK(&mac->pending_work, mtk_pending_work);
2014
2015 if (mtk_reg_table[MTK_REG_MTK_COUNTER_BASE]) {
2016 mac->hw_stats = devm_kzalloc(eth->dev,
2017 sizeof(*mac->hw_stats),
2018 GFP_KERNEL);
2019 if (!mac->hw_stats)
2020 return -ENOMEM;
2021 spin_lock_init(&mac->hw_stats->stats_lock);
2022 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2023 }
2024
2025 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2026 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2027 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2028
2029 if (eth->soc->init_data)
2030 eth->soc->init_data(eth->soc, eth->netdev[id]);
2031
2032 eth->netdev[id]->vlan_features = eth->soc->hw_features &
2033 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2034 eth->netdev[id]->features |= eth->soc->hw_features;
2035
2036 if (mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE])
2037 eth->netdev[id]->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2038
2039 mtk_set_ethtool_ops(eth->netdev[id]);
2040
2041 err = register_netdev(eth->netdev[id]);
2042 if (err) {
2043 dev_err(eth->dev, "error bringing up device\n");
2044 return err;
2045 }
2046 eth->netdev[id]->irq = eth->irq;
2047 netif_info(eth, probe, eth->netdev[id],
2048 "mediatek frame engine at 0x%08lx, irq %d\n",
2049 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
2050
2051 return 0;
2052}
2053
2054static int mtk_probe(struct platform_device *pdev)
2055{
2056 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2057 const struct of_device_id *match;
2058 struct device_node *mac_np;
2059 struct mtk_soc_data *soc;
2060 struct mtk_eth *eth;
2061 struct clk *sysclk;
2062 int err;
2063
2064 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2065 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
2066
2067 device_reset(&pdev->dev);
2068
2069 match = of_match_device(of_mtk_match, &pdev->dev);
2070 soc = (struct mtk_soc_data *)match->data;
2071
2072 if (soc->reg_table)
2073 mtk_reg_table = soc->reg_table;
2074
2075 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2076 if (!eth)
2077 return -ENOMEM;
2078
2079 eth->base = devm_ioremap_resource(&pdev->dev, res);
2080 if (IS_ERR(eth->base))
2081 return PTR_ERR(eth->base);
2082
2083 spin_lock_init(ð->page_lock);
2084
2085 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2086 "mediatek,ethsys");
2087 if (IS_ERR(eth->ethsys))
2088 return PTR_ERR(eth->ethsys);
2089
2090 eth->irq = platform_get_irq(pdev, 0);
2091 if (eth->irq < 0) {
2092 dev_err(&pdev->dev, "no IRQ resource found\n");
2093 return -ENXIO;
2094 }
2095
2096 sysclk = devm_clk_get(&pdev->dev, NULL);
2097 if (IS_ERR(sysclk)) {
2098 dev_err(&pdev->dev,
2099 "the clock is not defined in the devicetree\n");
2100 return -ENXIO;
2101 }
2102 eth->sysclk = clk_get_rate(sysclk);
2103
2104 eth->switch_np = of_parse_phandle(pdev->dev.of_node,
2105 "mediatek,switch", 0);
2106 if (soc->has_switch && !eth->switch_np) {
2107 dev_err(&pdev->dev, "failed to read switch phandle\n");
2108 return -ENODEV;
2109 }
2110
2111 eth->dev = &pdev->dev;
2112 eth->soc = soc;
2113 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2114
2115 err = mtk_init_hw(eth);
2116 if (err)
2117 return err;
2118
2119 if (eth->soc->mac_count > 1) {
2120 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2121 if (!of_device_is_compatible(mac_np,
2122 "mediatek,eth-mac"))
2123 continue;
2124
2125 if (!of_device_is_available(mac_np))
2126 continue;
2127
2128 err = mtk_add_mac(eth, mac_np);
2129 if (err)
2130 goto err_free_dev;
2131 }
2132
2133 init_dummy_netdev(ð->dummy_dev);
2134 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_poll,
2135 soc->napi_weight);
2136 } else {
2137 err = mtk_add_mac(eth, pdev->dev.of_node);
2138 if (err)
2139 goto err_free_dev;
2140 netif_napi_add(eth->netdev[0], ð->rx_napi, mtk_poll,
2141 soc->napi_weight);
2142 }
2143
2144 platform_set_drvdata(pdev, eth);
2145
2146 return 0;
2147
2148err_free_dev:
2149 mtk_cleanup(eth);
2150 return err;
2151}
2152
2153static int mtk_remove(struct platform_device *pdev)
2154{
2155 struct mtk_eth *eth = platform_get_drvdata(pdev);
2156
2157 netif_napi_del(ð->rx_napi);
2158 mtk_cleanup(eth);
2159 platform_set_drvdata(pdev, NULL);
2160
2161 return 0;
2162}
2163
2164static struct platform_driver mtk_driver = {
2165 .probe = mtk_probe,
2166 .remove = mtk_remove,
2167 .driver = {
2168 .name = "mtk_soc_eth",
2169 .owner = THIS_MODULE,
2170 .of_match_table = of_mtk_match,
2171 },
2172};
2173
2174module_platform_driver(mtk_driver);
2175
2176MODULE_LICENSE("GPL");
2177MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2178MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
2179
