LXR linux/drivers/staging/mt7621-pci/pci-mt7621.c

   1/**************************************************************************
   2 *
   3 *  BRIEF MODULE DESCRIPTION
   4 *     PCI init for Ralink RT2880 solution
   5 *
   6 *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
   7 *
   8 *  This program is free software; you can redistribute  it and/or modify it
   9 *  under  the terms of  the GNU General  Public License as published by the
  10 *  Free Software Foundation;  either version 2 of the  License, or (at your
  11 *  option) any later version.
  12 *
  13 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23 *
  24 *  You should have received a copy of the  GNU General Public License along
  25 *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26 *  675 Mass Ave, Cambridge, MA 02139, USA.
  27 *
  28 *
  29 **************************************************************************
  30 * May 2007 Bruce Chang
  31 * Initial Release
  32 *
  33 * May 2009 Bruce Chang
  34 * support RT2880/RT3883 PCIe
  35 *
  36 * May 2011 Bruce Chang
  37 * support RT6855/MT7620 PCIe
  38 *
  39 **************************************************************************
  40 */
  41
  42#include <linux/types.h>
  43#include <linux/pci.h>
  44#include <linux/kernel.h>
  45#include <linux/slab.h>
  46#include <linux/version.h>
  47#include <asm/pci.h>
  48#include <asm/io.h>
  49#include <asm/mips-cm.h>
  50#include <linux/init.h>
  51#include <linux/module.h>
  52#include <linux/delay.h>
  53#include <linux/of.h>
  54#include <linux/of_pci.h>
  55#include <linux/platform_device.h>
  56
  57#include <ralink_regs.h>
  58
  59extern void pcie_phy_init(void);
  60extern void chk_phy_pll(void);
  61
  62/*
  63 * These functions and structures provide the BIOS scan and mapping of the PCI
  64 * devices.
  65 */
  66
  67#define CONFIG_PCIE_PORT0
  68#define CONFIG_PCIE_PORT1
  69#define CONFIG_PCIE_PORT2
  70#define RALINK_PCIE0_CLK_EN             (1<<24)
  71#define RALINK_PCIE1_CLK_EN             (1<<25)
  72#define RALINK_PCIE2_CLK_EN             (1<<26)
  73
  74#define RALINK_PCI_CONFIG_ADDR                         0x20
  75#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
  76#define SURFBOARDINT_PCIE0       11      /* PCIE0 */
  77#define RALINK_INT_PCIE0         SURFBOARDINT_PCIE0
  78#define RALINK_INT_PCIE1         SURFBOARDINT_PCIE1
  79#define RALINK_INT_PCIE2         SURFBOARDINT_PCIE2
  80#define SURFBOARDINT_PCIE1       31     /* PCIE1 */
  81#define SURFBOARDINT_PCIE2       32     /* PCIE2 */
  82#define RALINK_PCI_MEMBASE              *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
  83#define RALINK_PCI_IOBASE               *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
  84#define RALINK_PCIE0_RST                (1<<24)
  85#define RALINK_PCIE1_RST                (1<<25)
  86#define RALINK_PCIE2_RST                (1<<26)
  87#define RALINK_SYSCTL_BASE              0xBE000000
  88
  89#define RALINK_PCI_PCICFG_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
  90#define RALINK_PCI_PCIMSK_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
  91#define RALINK_PCI_BASE                 0xBE140000
  92
  93#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
  94#define RT6855_PCIE0_OFFSET     0x2000
  95#define RT6855_PCIE1_OFFSET     0x3000
  96#define RT6855_PCIE2_OFFSET     0x4000
  97
  98#define RALINK_PCI0_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
  99#define RALINK_PCI0_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
 100#define RALINK_PCI0_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
 101#define RALINK_PCI0_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
 102#define RALINK_PCI0_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
 103#define RALINK_PCI0_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
 104#define RALINK_PCI0_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
 105#define RALINK_PCI0_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
 106
 107#define RALINK_PCI1_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
 108#define RALINK_PCI1_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
 109#define RALINK_PCI1_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
 110#define RALINK_PCI1_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
 111#define RALINK_PCI1_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
 112#define RALINK_PCI1_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
 113#define RALINK_PCI1_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
 114#define RALINK_PCI1_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
 115
 116#define RALINK_PCI2_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
 117#define RALINK_PCI2_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
 118#define RALINK_PCI2_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
 119#define RALINK_PCI2_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
 120#define RALINK_PCI2_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
 121#define RALINK_PCI2_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
 122#define RALINK_PCI2_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
 123#define RALINK_PCI2_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
 124
 125#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
 126#define RALINK_PCIEPHY_P2_CTL_OFFSET    (RALINK_PCI_BASE + 0xA000)
 127
 128
 129#define MV_WRITE(ofs, data)  \
 130        *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
 131#define MV_READ(ofs, data)   \
 132                *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 133#define MV_READ_DATA(ofs)    \
 134                        le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
 135
 136#define MV_WRITE_16(ofs, data)  \
 137        *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
 138#define MV_READ_16(ofs, data)   \
 139                *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
 140
 141#define MV_WRITE_8(ofs, data)  \
 142        *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
 143#define MV_READ_8(ofs, data)   \
 144                *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
 145
 146
 147
 148#define RALINK_PCI_MM_MAP_BASE  0x60000000
 149#define RALINK_PCI_IO_MAP_BASE  0x1e160000
 150
 151#define RALINK_SYSTEM_CONTROL_BASE      0xbe000000
 152#define GPIO_PERST
 153#define ASSERT_SYSRST_PCIE(val)         do {    \
 154                                                if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 155                                                        RALINK_RSTCTRL |= val;  \
 156                                                else    \
 157                                                        RALINK_RSTCTRL &= ~val; \
 158                                        } while(0)
 159#define DEASSERT_SYSRST_PCIE(val)       do {    \
 160                                                if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
 161                                                        RALINK_RSTCTRL &= ~val; \
 162                                                else    \
 163                                                        RALINK_RSTCTRL |= val;  \
 164                                        } while(0)
 165#define RALINK_SYSCFG1                  *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
 166#define RALINK_CLKCFG1                  *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
 167#define RALINK_RSTCTRL                  *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
 168#define RALINK_GPIOMODE                 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
 169#define RALINK_PCIE_CLK_GEN             *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
 170#define RALINK_PCIE_CLK_GEN1            *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
 171#define PPLL_CFG1                       *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
 172#define PPLL_DRV                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
 173//RALINK_SYSCFG1 bit
 174#define RALINK_PCI_HOST_MODE_EN         (1<<7)
 175#define RALINK_PCIE_RC_MODE_EN          (1<<8)
 176//RALINK_RSTCTRL bit
 177#define RALINK_PCIE_RST                 (1<<23)
 178#define RALINK_PCI_RST                  (1<<24)
 179//RALINK_CLKCFG1 bit
 180#define RALINK_PCI_CLK_EN               (1<<19)
 181#define RALINK_PCIE_CLK_EN              (1<<21)
 182//RALINK_GPIOMODE bit
 183#define PCI_SLOTx2                      (1<<11)
 184#define PCI_SLOTx1                      (2<<11)
 185//MTK PCIE PLL bit
 186#define PDRV_SW_SET                     (1<<31)
 187#define LC_CKDRVPD_                     (1<<19)
 188
 189#define MEMORY_BASE 0x0
 190static int pcie_link_status = 0;
 191
 192#define PCI_ACCESS_READ_1  0
 193#define PCI_ACCESS_READ_2  1
 194#define PCI_ACCESS_READ_4  2
 195#define PCI_ACCESS_WRITE_1 3
 196#define PCI_ACCESS_WRITE_2 4
 197#define PCI_ACCESS_WRITE_4 5
 198
 199static int config_access(unsigned char access_type, struct pci_bus *bus,
 200                        unsigned int devfn, unsigned int where, u32 * data)
 201{
 202        unsigned int slot = PCI_SLOT(devfn);
 203        u8 func = PCI_FUNC(devfn);
 204        uint32_t address_reg, data_reg;
 205        unsigned int address;
 206
 207        address_reg = RALINK_PCI_CONFIG_ADDR;
 208        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 209
 210        address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 211        MV_WRITE(address_reg, address);
 212
 213        switch(access_type) {
 214        case PCI_ACCESS_WRITE_1:
 215                MV_WRITE_8(data_reg+(where&0x3), *data);
 216                break;
 217        case PCI_ACCESS_WRITE_2:
 218                MV_WRITE_16(data_reg+(where&0x3), *data);
 219                break;
 220        case PCI_ACCESS_WRITE_4:
 221                MV_WRITE(data_reg, *data);
 222                break;
 223        case PCI_ACCESS_READ_1:
 224                MV_READ_8( data_reg+(where&0x3), data);
 225                break;
 226        case PCI_ACCESS_READ_2:
 227                MV_READ_16(data_reg+(where&0x3), data);
 228                break;
 229        case PCI_ACCESS_READ_4:
 230                MV_READ(data_reg, data);
 231                break;
 232        default:
 233                printk("no specify access type\n");
 234                break;
 235        }
 236        return 0;
 237}
 238
 239static int
 240read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
 241{
 242        return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
 243}
 244
 245static int
 246read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
 247{
 248        return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
 249}
 250
 251static int
 252read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
 253{
 254        return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
 255}
 256
 257static int
 258write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
 259{
 260        if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
 261                return -1;
 262
 263        return PCIBIOS_SUCCESSFUL;
 264}
 265
 266static int
 267write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
 268{
 269        if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
 270                return -1;
 271
 272        return PCIBIOS_SUCCESSFUL;
 273}
 274
 275static int
 276write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
 277{
 278        if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
 279                return -1;
 280
 281        return PCIBIOS_SUCCESSFUL;
 282}
 283
 284
 285static int
 286pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 287{
 288        switch (size) {
 289        case 1:
 290                return read_config_byte(bus, devfn, where, (u8 *) val);
 291        case 2:
 292                return read_config_word(bus, devfn, where, (u16 *) val);
 293        default:
 294                return read_config_dword(bus, devfn, where, val);
 295        }
 296}
 297
 298static int
 299pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 300{
 301        switch (size) {
 302        case 1:
 303                return write_config_byte(bus, devfn, where, (u8) val);
 304        case 2:
 305                return write_config_word(bus, devfn, where, (u16) val);
 306        default:
 307                return write_config_dword(bus, devfn, where, val);
 308        }
 309}
 310
 311struct pci_ops mt7621_pci_ops= {
 312        .read           =  pci_config_read,
 313        .write          = pci_config_write,
 314};
 315
 316static struct resource mt7621_res_pci_mem1 = {
 317        .name           = "PCI MEM1",
 318        .start          = RALINK_PCI_MM_MAP_BASE,
 319        .end            = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
 320        .flags          = IORESOURCE_MEM,
 321};
 322static struct resource mt7621_res_pci_io1 = {
 323        .name           = "PCI I/O1",
 324        .start          = RALINK_PCI_IO_MAP_BASE,
 325        .end            = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
 326        .flags          = IORESOURCE_IO,
 327};
 328
 329static struct pci_controller mt7621_controller = {
 330        .pci_ops        = &mt7621_pci_ops,
 331        .mem_resource   = &mt7621_res_pci_mem1,
 332        .io_resource    = &mt7621_res_pci_io1,
 333        .mem_offset     = 0x00000000UL,
 334        .io_offset      = 0x00000000UL,
 335        .io_map_base    = 0xa0000000,
 336};
 337
 338static void
 339read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
 340{
 341        unsigned int address_reg, data_reg, address;
 342
 343        address_reg = RALINK_PCI_CONFIG_ADDR;
 344        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 345        address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 346        MV_WRITE(address_reg, address);
 347        MV_READ(data_reg, val);
 348        return;
 349}
 350
 351static void
 352write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
 353{
 354        unsigned int address_reg, data_reg, address;
 355
 356        address_reg = RALINK_PCI_CONFIG_ADDR;
 357        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 358        address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
 359        MV_WRITE(address_reg, address);
 360        MV_WRITE(data_reg, val);
 361        return;
 362}
 363
 364
 365int
 366pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 367{
 368        u16 cmd;
 369        u32 val;
 370        int irq = 0;
 371
 372        if ((dev->bus->number == 0) && (slot == 0)) {
 373                write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 374                read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 375                printk("BAR0 at slot 0 = %x\n", val);
 376                printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 377        } else if((dev->bus->number == 0) && (slot == 0x1)) {
 378                write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 379                read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 380                printk("BAR0 at slot 1 = %x\n", val);
 381                printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 382        } else if((dev->bus->number == 0) && (slot == 0x2)) {
 383                write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 384                read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 385                printk("BAR0 at slot 2 = %x\n", val);
 386                printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 387        } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 388                switch (pcie_link_status) {
 389                case 2:
 390                case 6:
 391                        irq = RALINK_INT_PCIE1;
 392                        break;
 393                case 4:
 394                        irq = RALINK_INT_PCIE2;
 395                        break;
 396                default:
 397                        irq = RALINK_INT_PCIE0;
 398                }
 399                printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 400        } else if ((dev->bus->number == 2) && (slot == 0x0)) {
 401                switch (pcie_link_status) {
 402                case 5:
 403                case 6:
 404                        irq = RALINK_INT_PCIE2;
 405                        break;
 406                default:
 407                        irq = RALINK_INT_PCIE1;
 408                }
 409                printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 410        } else if ((dev->bus->number == 2) && (slot == 0x1)) {
 411                switch (pcie_link_status) {
 412                case 5:
 413                case 6:
 414                        irq = RALINK_INT_PCIE2;
 415                        break;
 416                default:
 417                        irq = RALINK_INT_PCIE1;
 418                }
 419                printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 420        } else if ((dev->bus->number ==3) && (slot == 0x0)) {
 421                irq = RALINK_INT_PCIE2;
 422                printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 423        } else if ((dev->bus->number ==3) && (slot == 0x1)) {
 424                irq = RALINK_INT_PCIE2;
 425                printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 426        } else if ((dev->bus->number ==3) && (slot == 0x2)) {
 427                irq = RALINK_INT_PCIE2;
 428                printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
 429        } else {
 430                printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
 431                return 0;
 432        }
 433
 434        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 435        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 436        pci_read_config_word(dev, PCI_COMMAND, &cmd);
 437        cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 438        pci_write_config_word(dev, PCI_COMMAND, cmd);
 439        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 440#ifdef  CONFIG_DTB_GNUBEE1
 441        /*
 442         * 'irq' here is a hwirq, but a virq is needed.  Until we know how and where
 443         * to convert one to the other, we have this hack for the GNUBEE1
 444         */
 445        return irq == 11 ? 22 : irq;
 446#else
 447        return irq;
 448#endif
 449}
 450
 451void
 452set_pcie_phy(u32 *addr, int start_b, int bits, int val)
 453{
 454//      printk("0x%p:", addr);
 455//      printk(" %x", *addr);
 456        *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
 457        *(unsigned int *)(addr) |= val << start_b;
 458//      printk(" -> %x\n", *addr);
 459}
 460
 461void
 462bypass_pipe_rst(void)
 463{
 464#if defined (CONFIG_PCIE_PORT0)
 465        /* PCIe Port 0 */
 466        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 467        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 468#endif
 469#if defined (CONFIG_PCIE_PORT1)
 470        /* PCIe Port 1 */
 471        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);     // rg_pe1_pipe_rst_b
 472        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);     // rg_pe1_pipe_cmd_frc[4]
 473#endif
 474#if defined (CONFIG_PCIE_PORT2)
 475        /* PCIe Port 2 */
 476        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);       // rg_pe1_pipe_rst_b
 477        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);       // rg_pe1_pipe_cmd_frc[4]
 478#endif
 479}
 480
 481void
 482set_phy_for_ssc(void)
 483{
 484        unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
 485
 486        reg = (reg >> 6) & 0x7;
 487#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
 488        /* Set PCIe Port0 & Port1 PHY to disable SSC */
 489        /* Debug Xtal Type */
 490        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);     // rg_pe1_frc_h_xtal_type
 491        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);     // rg_pe1_h_xtal_type
 492        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 0 enable control
 493        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);     // rg_pe1_frc_phy_en               //Force Port 1 enable control
 494        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 0 disable
 495        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);     // rg_pe1_phy_en                   //Port 1 disable
 496        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 497                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 498                printk("***** Xtal 40MHz *****\n");
 499        } else {                        // 25MHz | 20MHz Xtal
 500                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);     // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 501                if (reg >= 6) {         
 502                        printk("***** Xtal 25MHz *****\n");
 503                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);     // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 504                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0,31, 0x18000000);       // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 505                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0,16, 0x18d);    // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 506                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 507                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 508                } else {
 509                        printk("***** Xtal 20MHz *****\n");
 510                }
 511        }
 512        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);     // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 513        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);     // RG_PE1_H_PLL_BC                 
 514        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);     // RG_PE1_H_PLL_BP                 
 515        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);     // RG_PE1_H_PLL_IR                 
 516        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);     // RG_PE1_H_PLL_IC                 
 517        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);     // RG_PE1_H_PLL_BR                 
 518        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);     // RG_PE1_PLL_DIVEN                
 519        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 520                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);     // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 521                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);     // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv      
 522        }
 523        /* Enable PHY and disable force mode */
 524        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 0 enable
 525        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);     // rg_pe1_phy_en                   //Port 1 enable
 526        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 0 disable control
 527        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);     // rg_pe1_frc_phy_en               //Force Port 1 disable control
 528#endif
 529#if defined (CONFIG_PCIE_PORT2)
 530        /* Set PCIe Port2 PHY to disable SSC */
 531        /* Debug Xtal Type */
 532        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);       // rg_pe1_frc_h_xtal_type
 533        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);       // rg_pe1_h_xtal_type
 534        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);       // rg_pe1_frc_phy_en               //Force Port 0 enable control
 535        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);       // rg_pe1_phy_en                   //Port 0 disable
 536        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 537                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 538        } else {                        // 25MHz | 20MHz Xtal
 539                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);       // RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
 540                if (reg >= 6) {         // 25MHz Xtal
 541                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);       // RG_PE1_H_PLL_FBKSEL             //Feedback clock select
 542                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
 543                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0,16, 0x18d);      // RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
 544                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
 545                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
 546                }
 547        }
 548        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);       // RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
 549        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);       // RG_PE1_H_PLL_BC                 
 550        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);       // RG_PE1_H_PLL_BP                 
 551        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);       // RG_PE1_H_PLL_IR                 
 552        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);       // RG_PE1_H_PLL_IC                 
 553        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);       // RG_PE1_H_PLL_BR                 
 554        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);       // RG_PE1_PLL_DIVEN                
 555        if(reg <= 5 && reg >= 3) {      // 40MHz Xtal
 556                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);       // rg_pe1_mstckdiv              //value of da_pe1_mstckdiv when force mode enable
 557                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);       // rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv      
 558        }
 559        /* Enable PHY and disable force mode */
 560        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);       // rg_pe1_phy_en                   //Port 0 enable
 561        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);       // rg_pe1_frc_phy_en               //Force Port 0 disable control
 562#endif
 563}
 564
 565void setup_cm_memory_region(struct resource *mem_resource)
 566{
 567        resource_size_t mask;
 568        if (mips_cps_numiocu(0)) {
 569                /* FIXME: hardware doesn't accept mask values with 1s after
 570                   0s (e.g. 0xffef), so it would be great to warn if that's
 571                   about to happen */
 572                mask = ~(mem_resource->end - mem_resource->start);
 573
 574                write_gcr_reg1_base(mem_resource->start);
 575                write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
 576                printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
 577                       (unsigned long long)read_gcr_reg1_base(),
 578                       (unsigned long long)read_gcr_reg1_mask());
 579        }
 580}
 581
 582static int mt7621_pci_probe(struct platform_device *pdev)
 583{
 584        unsigned long val = 0;
 585
 586        iomem_resource.start = 0;
 587        iomem_resource.end= ~0;
 588        ioport_resource.start= 0;
 589        ioport_resource.end = ~0;
 590
 591#if defined (CONFIG_PCIE_PORT0)
 592        val = RALINK_PCIE0_RST;
 593#endif
 594#if defined (CONFIG_PCIE_PORT1)
 595        val |= RALINK_PCIE1_RST;
 596#endif
 597#if defined (CONFIG_PCIE_PORT2)
 598        val |= RALINK_PCIE2_RST;
 599#endif
 600        ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 601        printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 602#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
 603        *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
 604        *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
 605        mdelay(100);
 606        *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
 607        mdelay(100);
 608        *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);          // clear DATA
 609
 610        mdelay(100);
 611#else
 612        *(unsigned int *)(0xbe000060) &= ~0x00000c00;
 613#endif
 614#if defined (CONFIG_PCIE_PORT0)
 615        val = RALINK_PCIE0_RST;
 616#endif
 617#if defined (CONFIG_PCIE_PORT1)
 618        val |= RALINK_PCIE1_RST;
 619#endif
 620#if defined (CONFIG_PCIE_PORT2)
 621        val |= RALINK_PCIE2_RST;
 622#endif
 623        DEASSERT_SYSRST_PCIE(val);
 624        printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 625
 626        if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
 627                bypass_pipe_rst();
 628        set_phy_for_ssc();
 629        printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
 630
 631#if defined (CONFIG_PCIE_PORT0)
 632        read_config(0, 0, 0, 0x70c, &val);
 633        printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 634#endif
 635#if defined (CONFIG_PCIE_PORT1)
 636        read_config(0, 1, 0, 0x70c, &val);
 637        printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 638#endif
 639#if defined (CONFIG_PCIE_PORT2)
 640        read_config(0, 2, 0, 0x70c, &val);
 641        printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 642#endif
 643
 644        RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
 645        RALINK_SYSCFG1 &= ~(0x30);
 646        RALINK_SYSCFG1 |= (2<<4);
 647        RALINK_PCIE_CLK_GEN &= 0x7fffffff;
 648        RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
 649        RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
 650        RALINK_PCIE_CLK_GEN |= 0x80000000;
 651        mdelay(50);
 652        RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
 653        
 654
 655#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/
 656        *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;             // set DATA
 657        mdelay(100);
 658#else
 659        RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
 660#endif
 661        mdelay(500);
 662
 663
 664        mdelay(500);
 665#if defined (CONFIG_PCIE_PORT0)
 666        if(( RALINK_PCI0_STATUS & 0x1) == 0)
 667        {
 668                printk("PCIE0 no card, disable it(RST&CLK)\n");
 669                ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 670                RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
 671                pcie_link_status &= ~(1<<0);
 672        } else {
 673                pcie_link_status |= 1<<0;
 674                RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 675        }
 676#endif
 677#if defined (CONFIG_PCIE_PORT1)
 678        if(( RALINK_PCI1_STATUS & 0x1) == 0)
 679        {
 680                printk("PCIE1 no card, disable it(RST&CLK)\n");
 681                ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 682                RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
 683                pcie_link_status &= ~(1<<1);
 684        } else {
 685                pcie_link_status |= 1<<1;
 686                RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 687        }
 688#endif
 689#if defined (CONFIG_PCIE_PORT2)
 690        if (( RALINK_PCI2_STATUS & 0x1) == 0) {
 691                printk("PCIE2 no card, disable it(RST&CLK)\n");
 692                ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 693                RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
 694                pcie_link_status &= ~(1<<2);
 695        } else {
 696                pcie_link_status |= 1<<2;
 697                RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
 698        }
 699#endif
 700        if (pcie_link_status == 0)
 701                return 0;
 702
 703/*
 704pcie(2/1/0) link status pcie2_num       pcie1_num       pcie0_num
 7053'b000                  x               x               x
 7063'b001                  x               x               0
 7073'b010                  x               0               x
 7083'b011                  x               1               0
 7093'b100                  0               x               x
 7103'b101                  1               x               0
 7113'b110                  1               0               x
 7123'b111                  2               1               0
 713*/
 714        switch(pcie_link_status) {
 715        case 2:
 716                RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
 717                RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 718                RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 719                break;
 720        case 4:
 721                RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 722                RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;    //port0
 723                RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 724                RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;    //port2
 725                break;
 726        case 5:
 727                RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 728                RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;    //port0
 729                RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;    //port1
 730                RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 731                break;
 732        case 6:
 733                RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
 734                RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;    //port0
 735                RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;    //port1
 736                RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;    //port2
 737                break;
 738        }
 739        printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
 740        //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
 741
 742/*
 743        ioport_resource.start = mt7621_res_pci_io1.start;
 744        ioport_resource.end = mt7621_res_pci_io1.end;
 745*/
 746
 747        RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
 748        RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
 749
 750#if defined (CONFIG_PCIE_PORT0)
 751        //PCIe0
 752        if((pcie_link_status & 0x1) != 0) {
 753                RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 754                RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
 755                RALINK_PCI0_CLASS = 0x06040001;
 756                printk("PCIE0 enabled\n");
 757        }
 758#endif
 759#if defined (CONFIG_PCIE_PORT1)
 760        //PCIe1
 761        if ((pcie_link_status & 0x2) != 0) {
 762                RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 763                RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
 764                RALINK_PCI1_CLASS = 0x06040001;
 765                printk("PCIE1 enabled\n");
 766        }
 767#endif
 768#if defined (CONFIG_PCIE_PORT2)
 769        //PCIe2
 770        if ((pcie_link_status & 0x4) != 0) {
 771                RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;        //open 7FFF:2G; ENABLE
 772                RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
 773                RALINK_PCI2_CLASS = 0x06040001;
 774                printk("PCIE2 enabled\n");
 775        }
 776#endif
 777
 778
 779        switch(pcie_link_status) {
 780        case 7:
 781                read_config(0, 2, 0, 0x4, &val);
 782                write_config(0, 2, 0, 0x4, val|0x4);
 783                // write_config(0, 1, 0, 0x4, val|0x7);
 784                read_config(0, 2, 0, 0x70c, &val);
 785                val &= ~(0xff)<<8;
 786                val |= 0x50<<8;
 787                write_config(0, 2, 0, 0x70c, val);
 788        case 3:
 789        case 5:
 790        case 6:
 791                read_config(0, 1, 0, 0x4, &val);
 792                write_config(0, 1, 0, 0x4, val|0x4);
 793                // write_config(0, 1, 0, 0x4, val|0x7);
 794                read_config(0, 1, 0, 0x70c, &val);
 795                val &= ~(0xff)<<8;
 796                val |= 0x50<<8;
 797                write_config(0, 1, 0, 0x70c, val);
 798        default:
 799                read_config(0, 0, 0, 0x4, &val);
 800                write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
 801                // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
 802                read_config(0, 0, 0, 0x70c, &val);
 803                val &= ~(0xff)<<8;
 804                val |= 0x50<<8;
 805                write_config(0, 0, 0, 0x70c, val);
 806        }
 807
 808        pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
 809        setup_cm_memory_region(mt7621_controller.mem_resource);
 810        register_pci_controller(&mt7621_controller);
 811        return 0;
 812
 813}
 814
 815int pcibios_plat_dev_init(struct pci_dev *dev)
 816{
 817        return 0;
 818}
 819
 820static const struct of_device_id mt7621_pci_ids[] = {
 821        { .compatible = "mediatek,mt7621-pci" },
 822        {},
 823};
 824MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
 825
 826static struct platform_driver mt7621_pci_driver = {
 827        .probe = mt7621_pci_probe,
 828        .driver = {
 829                .name = "mt7621-pci",
 830                .owner = THIS_MODULE,
 831                .of_match_table = of_match_ptr(mt7621_pci_ids),
 832        },
 833};
 834
 835static int __init mt7621_pci_init(void)
 836{
 837        return platform_driver_register(&mt7621_pci_driver);
 838}
 839
 840arch_initcall(mt7621_pci_init);
 841