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15#ifndef __RTL8188E_XMIT_H__
16#define __RTL8188E_XMIT_H__
17
18#define MAX_TX_AGG_PACKET_NUMBER 0xFF
19
20
21
22#define QSLT_BK 0x2
23#define QSLT_BE 0x0
24#define QSLT_VI 0x5
25#define QSLT_VO 0x7
26#define QSLT_BEACON 0x10
27#define QSLT_HIGH 0x11
28#define QSLT_MGNT 0x12
29#define QSLT_CMD 0x13
30
31
32#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) \
33 SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
34#define SET_EARLYMODE_LEN0(__pAddr, __Value) \
35 SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
36#define SET_EARLYMODE_LEN1(__pAddr, __Value) \
37 SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
38#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) \
39 SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
40#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) \
41 SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
42#define SET_EARLYMODE_LEN3(__pAddr, __Value) \
43 SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
44#define SET_EARLYMODE_LEN4(__pAddr, __Value) \
45 SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
46
47
48
49
50
51#define MAX_TID (15)
52
53
54#define OFFSET_SZ 0
55#define OFFSET_SHT 16
56#define BMC BIT(24)
57#define LSG BIT(26)
58#define FSG BIT(27)
59#define OWN BIT(31)
60
61
62
63#define PKT_OFFSET_SZ 0
64#define QSEL_SHT 8
65#define RATE_ID_SHT 16
66#define NAVUSEHDR BIT(20)
67#define SEC_TYPE_SHT 22
68#define PKT_OFFSET_SHT 26
69
70
71#define AGG_EN BIT(12)
72#define AGG_BK BIT(16)
73#define AMPDU_DENSITY_SHT 20
74#define ANTSEL_A BIT(24)
75#define ANTSEL_B BIT(25)
76#define TX_ANT_CCK_SHT 26
77#define TX_ANTL_SHT 28
78#define TX_ANT_HT_SHT 30
79
80
81#define SEQ_SHT 16
82#define EN_HWSEQ BIT(31)
83
84
85#define QOS BIT(6)
86#define HW_SSN BIT(7)
87#define USERATE BIT(8)
88#define DISDATAFB BIT(10)
89#define CTS_2_SELF BIT(11)
90#define RTS_EN BIT(12)
91#define HW_RTS_EN BIT(13)
92#define DATA_SHORT BIT(24)
93#define PWR_STATUS_SHT 15
94#define DATA_SC_SHT 20
95#define DATA_BW BIT(25)
96
97
98#define RTY_LMT_EN BIT(17)
99
100enum TXDESC_SC {
101 SC_DONT_CARE = 0x00,
102 SC_UPPER = 0x01,
103 SC_LOWER = 0x02,
104 SC_DUPLICATE = 0x03
105};
106
107#define SGI BIT(6)
108#define USB_TXAGG_NUM_SHT 24
109
110#define txdesc_set_ccx_sw_88e(txdesc, value) \
111 do { \
112 ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
113 ((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
114 } while (0)
115
116struct txrpt_ccx_88e {
117
118 u8 tag1:1;
119 u8 pkt_num:3;
120 u8 txdma_underflow:1;
121 u8 int_bt:1;
122 u8 int_tri:1;
123 u8 int_ccx:1;
124
125
126 u8 mac_id:6;
127 u8 pkt_ok:1;
128 u8 bmc:1;
129
130
131 u8 retry_cnt:6;
132 u8 lifetime_over:1;
133 u8 retry_over:1;
134
135
136 u8 ccx_qtime0;
137 u8 ccx_qtime1;
138
139
140 u8 final_data_rate;
141
142
143 u8 sw1:4;
144 u8 qsel:4;
145
146
147 u8 sw0;
148};
149
150#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
151#define txrpt_ccx_qtime_88e(txrpt_ccx) \
152 ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
153
154void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc,
155 u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
156s32 rtl8188eu_init_xmit_priv(struct adapter *padapter);
157s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter);
158#define hal_xmit_handler rtl8188eu_xmit_buf_handler
159void rtl8188eu_xmit_tasklet(void *priv);
160s32 rtl8188eu_xmitframe_complete(struct adapter *padapter,
161 struct xmit_priv *pxmitpriv);
162
163void dump_txrpt_ccx_88e(void *buf);
164void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf);
165
166void _dbg_dump_tx_info(struct adapter *padapter, int frame_tag,
167 struct tx_desc *ptxdesc);
168
169#endif
170