1/* SPDX-License-Identifier: GPL-2.0 */ 2/***************************************************************************** 3 *Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. 4 * 5 * Module: __INC_HAL8723BREG_H 6 * 7 * 8 * Note: 1. Define Mac register address and corresponding bit mask map 9 * 10 * 11 * Export: Constants, macro, functions(API), global variables(None). 12 * 13 * Abbrev: 14 * 15 * History: 16 * Data Who Remark 17 * 18 *****************************************************************************/ 19#ifndef __INC_HAL8723BREG_H 20#define __INC_HAL8723BREG_H 21 22 23 24/* */ 25/* */ 26/* */ 27 28/* */ 29/* */ 30/* 0x0000h ~ 0x00FFh System Configuration */ 31/* */ 32/* */ 33#define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */ 34#define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */ 35#define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */ 36#define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */ 37#define REG_9346CR_8723B 0x000A /* 2 Byte */ 38#define REG_EE_VPD_8723B 0x000C /* 2 Byte */ 39#define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */ 40#define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */ 41#define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */ 42#define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ 43#define REG_RF_CTRL_8723B 0x001F /* 1 Byte */ 44#define REG_LPLDO_CTRL_8723B 0x0023 /* 1 Byte */ 45#define REG_AFE_XTAL_CTRL_8723B 0x0024 /* 4 Byte */ 46#define REG_AFE_PLL_CTRL_8723B 0x0028 /* 4 Byte */ 47#define REG_MAC_PLL_CTRL_EXT_8723B 0x002c /* 4 Byte */ 48#define REG_EFUSE_CTRL_8723B 0x0030 49#define REG_EFUSE_TEST_8723B 0x0034 50#define REG_PWR_DATA_8723B 0x0038 51#define REG_CAL_TIMER_8723B 0x003C 52#define REG_ACLK_MON_8723B 0x003E 53#define REG_GPIO_MUXCFG_8723B 0x0040 54#define REG_GPIO_IO_SEL_8723B 0x0042 55#define REG_MAC_PINMUX_CFG_8723B 0x0043 56#define REG_GPIO_PIN_CTRL_8723B 0x0044 57#define REG_GPIO_INTM_8723B 0x0048 58#define REG_LEDCFG0_8723B 0x004C 59#define REG_LEDCFG1_8723B 0x004D 60#define REG_LEDCFG2_8723B 0x004E 61#define REG_LEDCFG3_8723B 0x004F 62#define REG_FSIMR_8723B 0x0050 63#define REG_FSISR_8723B 0x0054 64#define REG_HSIMR_8723B 0x0058 65#define REG_HSISR_8723B 0x005c 66#define REG_GPIO_EXT_CTRL 0x0060 67#define REG_MULTI_FUNC_CTRL_8723B 0x0068 68#define REG_GPIO_STATUS_8723B 0x006C 69#define REG_SDIO_CTRL_8723B 0x0070 70#define REG_OPT_CTRL_8723B 0x0074 71#define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 72#define REG_MCUFWDL_8723B 0x0080 73#define REG_BT_PATCH_STATUS_8723B 0x0088 74#define REG_HIMR0_8723B 0x00B0 75#define REG_HISR0_8723B 0x00B4 76#define REG_HIMR1_8723B 0x00B8 77#define REG_HISR1_8723B 0x00BC 78#define REG_PMC_DBG_CTRL2_8723B 0x00CC 79#define REG_EFUSE_BURN_GNT_8723B 0x00CF 80#define REG_HPON_FSM_8723B 0x00EC 81#define REG_SYS_CFG_8723B 0x00F0 82#define REG_SYS_CFG1_8723B 0x00FC 83#define REG_ROM_VERSION 0x00FD 84 85/* */ 86/* */ 87/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 88/* */ 89/* */ 90#define REG_CR_8723B 0x0100 91#define REG_PBP_8723B 0x0104 92#define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 93#define REG_TRXDMA_CTRL_8723B 0x010C 94#define REG_TRXFF_BNDY_8723B 0x0114 95#define REG_TRXFF_STATUS_8723B 0x0118 96#define REG_RXFF_PTR_8723B 0x011C 97#define REG_CPWM_8723B 0x012F 98#define REG_FWIMR_8723B 0x0130 99#define REG_FWISR_8723B 0x0134 100#define REG_FTIMR_8723B 0x0138 101#define REG_PKTBUF_DBG_CTRL_8723B 0x0140 102#define REG_RXPKTBUF_CTRL_8723B 0x0142 103#define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 104#define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 105 106#define REG_TC0_CTRL_8723B 0x0150 107#define REG_TC1_CTRL_8723B 0x0154 108#define REG_TC2_CTRL_8723B 0x0158 109#define REG_TC3_CTRL_8723B 0x015C 110#define REG_TC4_CTRL_8723B 0x0160 111#define REG_TCUNIT_BASE_8723B 0x0164 112#define REG_RSVD3_8723B 0x0168 113#define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 114#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 115#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 116#define REG_C2HEVT_CMD_LEN_88XX 0x01AE 117#define REG_C2HEVT_CLEAR_8723B 0x01AF 118#define REG_MCUTST_1_8723B 0x01C0 119#define REG_MCUTST_WOWLAN_8723B 0x01C7 120#define REG_FMETHR_8723B 0x01C8 121#define REG_HMETFR_8723B 0x01CC 122#define REG_HMEBOX_0_8723B 0x01D0 123#define REG_HMEBOX_1_8723B 0x01D4 124#define REG_HMEBOX_2_8723B 0x01D8 125#define REG_HMEBOX_3_8723B 0x01DC 126#define REG_LLT_INIT_8723B 0x01E0 127#define REG_HMEBOX_EXT0_8723B 0x01F0 128#define REG_HMEBOX_EXT1_8723B 0x01F4 129#define REG_HMEBOX_EXT2_8723B 0x01F8 130#define REG_HMEBOX_EXT3_8723B 0x01FC 131 132/* */ 133/* */ 134/* 0x0200h ~ 0x027Fh TXDMA Configuration */ 135/* */ 136/* */ 137#define REG_RQPN_8723B 0x0200 138#define REG_FIFOPAGE_8723B 0x0204 139#define REG_DWBCN0_CTRL_8723B REG_TDECTRL 140#define REG_TXDMA_OFFSET_CHK_8723B 0x020C 141#define REG_TXDMA_STATUS_8723B 0x0210 142#define REG_RQPN_NPQ_8723B 0x0214 143#define REG_DWBCN1_CTRL_8723B 0x0228 144 145 146/* */ 147/* */ 148/* 0x0280h ~ 0x02FFh RXDMA Configuration */ 149/* */ 150/* */ 151#define REG_RXDMA_AGG_PG_TH_8723B 0x0280 152#define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 153#define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ 154#define REG_RXPKT_NUM_8723B 0x0287 /* The number of packets in RXPKTBUF. */ 155#define REG_RXDMA_STATUS_8723B 0x0288 156#define REG_RXDMA_PRO_8723B 0x0290 157#define REG_EARLY_MODE_CONTROL_8723B 0x02BC 158#define REG_RSVD5_8723B 0x02F0 159#define REG_RSVD6_8723B 0x02F4 160 161 162/* */ 163/* */ 164/* 0x0300h ~ 0x03FFh PCIe */ 165/* */ 166/* */ 167#define REG_PCIE_CTRL_REG_8723B 0x0300 168#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ 169#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ 170#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ 171#define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ 172#define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ 173#define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ 174#define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ 175#define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ 176#define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ 177#define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ 178#define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ 179#define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ 180#define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ 181#define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ 182#define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ 183#define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ 184#define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ 185#define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ 186#define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ 187#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ 188 189/* spec version 11 */ 190/* */ 191/* */ 192/* 0x0400h ~ 0x047Fh Protocol Configuration */ 193/* */ 194/* */ 195#define REG_VOQ_INFORMATION_8723B 0x0400 196#define REG_VIQ_INFORMATION_8723B 0x0404 197#define REG_BEQ_INFORMATION_8723B 0x0408 198#define REG_BKQ_INFORMATION_8723B 0x040C 199#define REG_MGQ_INFORMATION_8723B 0x0410 200#define REG_HGQ_INFORMATION_8723B 0x0414 201#define REG_BCNQ_INFORMATION_8723B 0x0418 202#define REG_TXPKT_EMPTY_8723B 0x041A 203 204#define REG_FWHW_TXQ_CTRL_8723B 0x0420 205#define REG_HWSEQ_CTRL_8723B 0x0423 206#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 207#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 208#define REG_LIFECTRL_CTRL_8723B 0x0426 209#define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 210#define REG_SPEC_SIFS_8723B 0x0428 211#define REG_RL_8723B 0x042A 212#define REG_TXBF_CTRL_8723B 0x042C 213#define REG_DARFRC_8723B 0x0430 214#define REG_RARFRC_8723B 0x0438 215#define REG_RRSR_8723B 0x0440 216#define REG_ARFR0_8723B 0x0444 217#define REG_ARFR1_8723B 0x044C 218#define REG_CCK_CHECK_8723B 0x0454 219#define REG_AMPDU_MAX_TIME_8723B 0x0456 220#define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 221 222#define REG_AMPDU_MAX_LENGTH_8723B 0x0458 223#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D 224#define REG_NDPA_OPT_CTRL_8723B 0x045F 225#define REG_FAST_EDCA_CTRL_8723B 0x0460 226#define REG_RD_RESP_PKT_TH_8723B 0x0463 227#define REG_DATA_SC_8723B 0x0483 228#define REG_TXRPT_START_OFFSET 0x04AC 229#define REG_POWER_STAGE1_8723B 0x04B4 230#define REG_POWER_STAGE2_8723B 0x04B8 231#define REG_AMPDU_BURST_MODE_8723B 0x04BC 232#define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 233#define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 234#define REG_STBC_SETTING_8723B 0x04C4 235#define REG_HT_SINGLE_AMPDU_8723B 0x04C7 236#define REG_PROT_MODE_CTRL_8723B 0x04C8 237#define REG_MAX_AGGR_NUM_8723B 0x04CA 238#define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB 239#define REG_BAR_MODE_CTRL_8723B 0x04CC 240#define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF 241#define REG_MACID_PKT_DROP0_8723B 0x04D0 242#define REG_MACID_PKT_SLEEP_8723B 0x04D4 243 244/* */ 245/* */ 246/* 0x0500h ~ 0x05FFh EDCA Configuration */ 247/* */ 248/* */ 249#define REG_EDCA_VO_PARAM_8723B 0x0500 250#define REG_EDCA_VI_PARAM_8723B 0x0504 251#define REG_EDCA_BE_PARAM_8723B 0x0508 252#define REG_EDCA_BK_PARAM_8723B 0x050C 253#define REG_BCNTCFG_8723B 0x0510 254#define REG_PIFS_8723B 0x0512 255#define REG_RDG_PIFS_8723B 0x0513 256#define REG_SIFS_CTX_8723B 0x0514 257#define REG_SIFS_TRX_8723B 0x0516 258#define REG_AGGR_BREAK_TIME_8723B 0x051A 259#define REG_SLOT_8723B 0x051B 260#define REG_TX_PTCL_CTRL_8723B 0x0520 261#define REG_TXPAUSE_8723B 0x0522 262#define REG_DIS_TXREQ_CLR_8723B 0x0523 263#define REG_RD_CTRL_8723B 0x0524 264/* */ 265/* Format for offset 540h-542h: */ 266/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ 267/* [7:4]: Reserved. */ 268/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */ 269/* [23:20]: Reserved */ 270/* Description: */ 271/* | */ 272/* |<--Setup--|--Hold------------>| */ 273/* --------------|---------------------- */ 274/* | */ 275/* TBTT */ 276/* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ 277/* Described by Designer Tim and Bruce, 2011-01-14. */ 278/* */ 279#define REG_TBTT_PROHIBIT_8723B 0x0540 280#define REG_RD_NAV_NXT_8723B 0x0544 281#define REG_NAV_PROT_LEN_8723B 0x0546 282#define REG_BCN_CTRL_8723B 0x0550 283#define REG_BCN_CTRL_1_8723B 0x0551 284#define REG_MBID_NUM_8723B 0x0552 285#define REG_DUAL_TSF_RST_8723B 0x0553 286#define REG_BCN_INTERVAL_8723B 0x0554 287#define REG_DRVERLYINT_8723B 0x0558 288#define REG_BCNDMATIM_8723B 0x0559 289#define REG_ATIMWND_8723B 0x055A 290#define REG_USTIME_TSF_8723B 0x055C 291#define REG_BCN_MAX_ERR_8723B 0x055D 292#define REG_RXTSF_OFFSET_CCK_8723B 0x055E 293#define REG_RXTSF_OFFSET_OFDM_8723B 0x055F 294#define REG_TSFTR_8723B 0x0560 295#define REG_CTWND_8723B 0x0572 296#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 297#define REG_PSTIMER_8723B 0x0580 298#define REG_TIMER0_8723B 0x0584 299#define REG_TIMER1_8723B 0x0588 300#define REG_ACMHWCTRL_8723B 0x05C0 301#define REG_SCH_TXCMD_8723B 0x05F8 302 303/* 0x0600h ~ 0x07FFh WMAC Configuration */ 304#define REG_MAC_CR_8723B 0x0600 305#define REG_TCR_8723B 0x0604 306#define REG_RCR_8723B 0x0608 307#define REG_RX_PKT_LIMIT_8723B 0x060C 308#define REG_RX_DLK_TIME_8723B 0x060D 309#define REG_RX_DRVINFO_SZ_8723B 0x060F 310 311#define REG_MACID_8723B 0x0610 312#define REG_BSSID_8723B 0x0618 313#define REG_MAR_8723B 0x0620 314#define REG_MBIDCAMCFG_8723B 0x0628 315 316#define REG_USTIME_EDCA_8723B 0x0638 317#define REG_MAC_SPEC_SIFS_8723B 0x063A 318#define REG_RESP_SIFP_CCK_8723B 0x063C 319#define REG_RESP_SIFS_OFDM_8723B 0x063E 320#define REG_ACKTO_8723B 0x0640 321#define REG_CTS2TO_8723B 0x0641 322#define REG_EIFS_8723B 0x0642 323 324#define REG_NAV_UPPER_8723B 0x0652 /* unit of 128 */ 325#define REG_TRXPTCL_CTL_8723B 0x0668 326 327/* Security */ 328#define REG_CAMCMD_8723B 0x0670 329#define REG_CAMWRITE_8723B 0x0674 330#define REG_CAMREAD_8723B 0x0678 331#define REG_CAMDBG_8723B 0x067C 332#define REG_SECCFG_8723B 0x0680 333 334/* Power */ 335#define REG_WOW_CTRL_8723B 0x0690 336#define REG_PS_RX_INFO_8723B 0x0692 337#define REG_UAPSD_TID_8723B 0x0693 338#define REG_WKFMCAM_CMD_8723B 0x0698 339#define REG_WKFMCAM_NUM_8723B 0x0698 340#define REG_WKFMCAM_RWD_8723B 0x069C 341#define REG_RXFLTMAP0_8723B 0x06A0 342#define REG_RXFLTMAP1_8723B 0x06A2 343#define REG_RXFLTMAP2_8723B 0x06A4 344#define REG_BCN_PSR_RPT_8723B 0x06A8 345#define REG_BT_COEX_TABLE_8723B 0x06C0 346#define REG_BFMER0_INFO_8723B 0x06E4 347#define REG_BFMER1_INFO_8723B 0x06EC 348#define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 349#define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 350#define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC 351 352/* Hardware Port 2 */ 353#define REG_MACID1_8723B 0x0700 354#define REG_BSSID1_8723B 0x0708 355#define REG_BFMEE_SEL_8723B 0x0714 356#define REG_SND_PTCL_CTRL_8723B 0x0718 357 358 359/* Redifine 8192C register definition for compatibility */ 360 361/* TODO: use these definition when using REG_xxx naming rule. */ 362/* NOTE: DO NOT Remove these definition. Use later. */ 363#define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B /* E-Fuse Control. */ 364#define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B /* E-Fuse Test. */ 365#define MSR_8723B (REG_CR_8723B + 2) /* Media Status register */ 366#define ISR_8723B REG_HISR0_8723B 367#define TSFR_8723B REG_TSFTR_8723B /* Timing Sync Function Timer Register. */ 368 369#define PBP_8723B REG_PBP_8723B 370 371/* Redifine MACID register, to compatible prior ICs. */ 372#define IDR0_8723B REG_MACID_8723B /* MAC ID Register, Offset 0x0050-0x0053 */ 373#define IDR4_8723B (REG_MACID_8723B + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ 374 375/* 9. Security Control Registers (Offset:) */ 376#define RWCAM_8723B REG_CAMCMD_8723B /* IN 8190 Data Sheet is called CAMcmd */ 377#define WCAMI_8723B REG_CAMWRITE_8723B /* Software write CAM input content */ 378#define RCAMO_8723B REG_CAMREAD_8723B /* Software read/write CAM config */ 379#define CAMDBG_8723B REG_CAMDBG_8723B 380#define SECR_8723B REG_SECCFG_8723B /* Security Configuration Register */ 381 382/* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ 383#define IMR_DISABLED_8723B 0 384/* IMR DW0(0x00B0-00B3) Bit 0-31 */ 385#define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ 386#define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ 387#define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ 388#define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 389#define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 390#define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ 391#define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ 392#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 393#define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ 394#define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ 395#define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 396#define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 397#define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ 398#define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 399#define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 400#define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 401#define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ 402#define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ 403#define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ 404#define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ 405#define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ 406#define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ 407#define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ 408#define IMR_ROK_8723B BIT0 /* Receive DMA OK */ 409 410/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 411#define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ 412#define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ 413#define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ 414#define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ 415#define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ 416#define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ 417#define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ 418#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrup 7 */ 419#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrup 6 */ 420#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrup 5 */ 421#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrup 4 */ 422#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrup 3 */ 423#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrup 2 */ 424#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrup 1 */ 425#define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ 426#define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ 427#define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ 428#define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ 429#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ 430 431/* 2 ACMHWCTRL 0x05C0 */ 432#define AcmHw_HwEn_8723B BIT(0) 433#define AcmHw_VoqEn_8723B BIT(1) 434#define AcmHw_ViqEn_8723B BIT(2) 435#define AcmHw_BeqEn_8723B BIT(3) 436#define AcmHw_VoqStatus_8723B BIT(5) 437#define AcmHw_ViqStatus_8723B BIT(6) 438#define AcmHw_BeqStatus_8723B BIT(7) 439 440/* 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ 441#define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */ 442 443#endif /* #ifndef __INC_HAL8723BREG_H */ 444