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15#define _HAL_COM_C_
16
17#include <linux/kernel.h>
18#include <drv_types.h>
19#include <rtw_debug.h>
20#include "hal_com_h2c.h"
21
22#include "odm_precomp.h"
23
24u8 rtw_hal_data_init(struct adapter *padapter)
25{
26 if (is_primary_adapter(padapter)) {
27 padapter->hal_data_sz = sizeof(struct hal_com_data);
28 padapter->HalData = vzalloc(padapter->hal_data_sz);
29 if (padapter->HalData == NULL) {
30 DBG_8192C("cannot alloc memory for HAL DATA\n");
31 return _FAIL;
32 }
33 }
34 return _SUCCESS;
35}
36
37void rtw_hal_data_deinit(struct adapter *padapter)
38{
39 if (is_primary_adapter(padapter)) {
40 if (padapter->HalData) {
41 phy_free_filebuf(padapter);
42 vfree(padapter->HalData);
43 padapter->HalData = NULL;
44 padapter->hal_data_sz = 0;
45 }
46 }
47}
48
49
50void dump_chip_info(HAL_VERSION ChipVersion)
51{
52 int cnt = 0;
53 u8 buf[128];
54
55 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723B_");
56 cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip");
57 if (IS_CHIP_VENDOR_TSMC(ChipVersion))
58 cnt += sprintf((buf+cnt), "%s_", "TSMC");
59 else if (IS_CHIP_VENDOR_UMC(ChipVersion))
60 cnt += sprintf((buf+cnt), "%s_", "UMC");
61 else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
62 cnt += sprintf((buf+cnt), "%s_", "SMIC");
63
64 if (IS_A_CUT(ChipVersion))
65 cnt += sprintf((buf+cnt), "A_CUT_");
66 else if (IS_B_CUT(ChipVersion))
67 cnt += sprintf((buf+cnt), "B_CUT_");
68 else if (IS_C_CUT(ChipVersion))
69 cnt += sprintf((buf+cnt), "C_CUT_");
70 else if (IS_D_CUT(ChipVersion))
71 cnt += sprintf((buf+cnt), "D_CUT_");
72 else if (IS_E_CUT(ChipVersion))
73 cnt += sprintf((buf+cnt), "E_CUT_");
74 else if (IS_I_CUT(ChipVersion))
75 cnt += sprintf((buf+cnt), "I_CUT_");
76 else if (IS_J_CUT(ChipVersion))
77 cnt += sprintf((buf+cnt), "J_CUT_");
78 else if (IS_K_CUT(ChipVersion))
79 cnt += sprintf((buf+cnt), "K_CUT_");
80 else
81 cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
82
83 if (IS_1T1R(ChipVersion))
84 cnt += sprintf((buf+cnt), "1T1R_");
85 else if (IS_1T2R(ChipVersion))
86 cnt += sprintf((buf+cnt), "1T2R_");
87 else if (IS_2T2R(ChipVersion))
88 cnt += sprintf((buf+cnt), "2T2R_");
89 else
90 cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
91
92 cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
93
94 DBG_871X("%s", buf);
95}
96
97
98#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
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118u8 hal_com_config_channel_plan(
119 struct adapter *padapter,
120 u8 hw_channel_plan,
121 u8 sw_channel_plan,
122 u8 def_channel_plan,
123 bool AutoLoadFail
124)
125{
126 struct hal_com_data *pHalData;
127 u8 chnlPlan;
128
129 pHalData = GET_HAL_DATA(padapter);
130 pHalData->bDisableSWChannelPlan = false;
131 chnlPlan = def_channel_plan;
132
133 if (0xFF == hw_channel_plan)
134 AutoLoadFail = true;
135
136 if (false == AutoLoadFail) {
137 u8 hw_chnlPlan;
138
139 hw_chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
140 if (rtw_is_channel_plan_valid(hw_chnlPlan)) {
141#ifndef CONFIG_SW_CHANNEL_PLAN
142 if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
143 pHalData->bDisableSWChannelPlan = true;
144#endif
145
146 chnlPlan = hw_chnlPlan;
147 }
148 }
149
150 if (
151 (false == pHalData->bDisableSWChannelPlan) &&
152 rtw_is_channel_plan_valid(sw_channel_plan)
153 )
154 chnlPlan = sw_channel_plan;
155
156 return chnlPlan;
157}
158
159bool HAL_IsLegalChannel(struct adapter *Adapter, u32 Channel)
160{
161 bool bLegalChannel = true;
162
163 if (Channel > 14) {
164 bLegalChannel = false;
165 DBG_871X("Channel > 14 but wireless_mode do not support 5G\n");
166 } else if ((Channel <= 14) && (Channel >= 1)) {
167 if (IsSupported24G(Adapter->registrypriv.wireless_mode) == false) {
168 bLegalChannel = false;
169 DBG_871X("(Channel <= 14) && (Channel >= 1) but wireless_mode do not support 2.4G\n");
170 }
171 } else {
172 bLegalChannel = false;
173 DBG_871X("Channel is Invalid !!!\n");
174 }
175
176 return bLegalChannel;
177}
178
179u8 MRateToHwRate(u8 rate)
180{
181 u8 ret = DESC_RATE1M;
182
183 switch (rate) {
184 case MGN_1M:
185 ret = DESC_RATE1M;
186 break;
187 case MGN_2M:
188 ret = DESC_RATE2M;
189 break;
190 case MGN_5_5M:
191 ret = DESC_RATE5_5M;
192 break;
193 case MGN_11M:
194 ret = DESC_RATE11M;
195 break;
196 case MGN_6M:
197 ret = DESC_RATE6M;
198 break;
199 case MGN_9M:
200 ret = DESC_RATE9M;
201 break;
202 case MGN_12M:
203 ret = DESC_RATE12M;
204 break;
205 case MGN_18M:
206 ret = DESC_RATE18M;
207 break;
208 case MGN_24M:
209 ret = DESC_RATE24M;
210 break;
211 case MGN_36M:
212 ret = DESC_RATE36M;
213 break;
214 case MGN_48M:
215 ret = DESC_RATE48M;
216 break;
217 case MGN_54M:
218 ret = DESC_RATE54M;
219 break;
220 case MGN_MCS0:
221 ret = DESC_RATEMCS0;
222 break;
223 case MGN_MCS1:
224 ret = DESC_RATEMCS1;
225 break;
226 case MGN_MCS2:
227 ret = DESC_RATEMCS2;
228 break;
229 case MGN_MCS3:
230 ret = DESC_RATEMCS3;
231 break;
232 case MGN_MCS4:
233 ret = DESC_RATEMCS4;
234 break;
235 case MGN_MCS5:
236 ret = DESC_RATEMCS5;
237 break;
238 case MGN_MCS6:
239 ret = DESC_RATEMCS6;
240 break;
241 case MGN_MCS7:
242 ret = DESC_RATEMCS7;
243 break;
244 case MGN_MCS8:
245 ret = DESC_RATEMCS8;
246 break;
247 case MGN_MCS9:
248 ret = DESC_RATEMCS9;
249 break;
250 case MGN_MCS10:
251 ret = DESC_RATEMCS10;
252 break;
253 case MGN_MCS11:
254 ret = DESC_RATEMCS11;
255 break;
256 case MGN_MCS12:
257 ret = DESC_RATEMCS12;
258 break;
259 case MGN_MCS13:
260 ret = DESC_RATEMCS13;
261 break;
262 case MGN_MCS14:
263 ret = DESC_RATEMCS14;
264 break;
265 case MGN_MCS15:
266 ret = DESC_RATEMCS15;
267 break;
268 case MGN_MCS16:
269 ret = DESC_RATEMCS16;
270 break;
271 case MGN_MCS17:
272 ret = DESC_RATEMCS17;
273 break;
274 case MGN_MCS18:
275 ret = DESC_RATEMCS18;
276 break;
277 case MGN_MCS19:
278 ret = DESC_RATEMCS19;
279 break;
280 case MGN_MCS20:
281 ret = DESC_RATEMCS20;
282 break;
283 case MGN_MCS21:
284 ret = DESC_RATEMCS21;
285 break;
286 case MGN_MCS22:
287 ret = DESC_RATEMCS22;
288 break;
289 case MGN_MCS23:
290 ret = DESC_RATEMCS23;
291 break;
292 case MGN_MCS24:
293 ret = DESC_RATEMCS24;
294 break;
295 case MGN_MCS25:
296 ret = DESC_RATEMCS25;
297 break;
298 case MGN_MCS26:
299 ret = DESC_RATEMCS26;
300 break;
301 case MGN_MCS27:
302 ret = DESC_RATEMCS27;
303 break;
304 case MGN_MCS28:
305 ret = DESC_RATEMCS28;
306 break;
307 case MGN_MCS29:
308 ret = DESC_RATEMCS29;
309 break;
310 case MGN_MCS30:
311 ret = DESC_RATEMCS30;
312 break;
313 case MGN_MCS31:
314 ret = DESC_RATEMCS31;
315 break;
316 case MGN_VHT1SS_MCS0:
317 ret = DESC_RATEVHTSS1MCS0;
318 break;
319 case MGN_VHT1SS_MCS1:
320 ret = DESC_RATEVHTSS1MCS1;
321 break;
322 case MGN_VHT1SS_MCS2:
323 ret = DESC_RATEVHTSS1MCS2;
324 break;
325 case MGN_VHT1SS_MCS3:
326 ret = DESC_RATEVHTSS1MCS3;
327 break;
328 case MGN_VHT1SS_MCS4:
329 ret = DESC_RATEVHTSS1MCS4;
330 break;
331 case MGN_VHT1SS_MCS5:
332 ret = DESC_RATEVHTSS1MCS5;
333 break;
334 case MGN_VHT1SS_MCS6:
335 ret = DESC_RATEVHTSS1MCS6;
336 break;
337 case MGN_VHT1SS_MCS7:
338 ret = DESC_RATEVHTSS1MCS7;
339 break;
340 case MGN_VHT1SS_MCS8:
341 ret = DESC_RATEVHTSS1MCS8;
342 break;
343 case MGN_VHT1SS_MCS9:
344 ret = DESC_RATEVHTSS1MCS9;
345 break;
346 case MGN_VHT2SS_MCS0:
347 ret = DESC_RATEVHTSS2MCS0;
348 break;
349 case MGN_VHT2SS_MCS1:
350 ret = DESC_RATEVHTSS2MCS1;
351 break;
352 case MGN_VHT2SS_MCS2:
353 ret = DESC_RATEVHTSS2MCS2;
354 break;
355 case MGN_VHT2SS_MCS3:
356 ret = DESC_RATEVHTSS2MCS3;
357 break;
358 case MGN_VHT2SS_MCS4:
359 ret = DESC_RATEVHTSS2MCS4;
360 break;
361 case MGN_VHT2SS_MCS5:
362 ret = DESC_RATEVHTSS2MCS5;
363 break;
364 case MGN_VHT2SS_MCS6:
365 ret = DESC_RATEVHTSS2MCS6;
366 break;
367 case MGN_VHT2SS_MCS7:
368 ret = DESC_RATEVHTSS2MCS7;
369 break;
370 case MGN_VHT2SS_MCS8:
371 ret = DESC_RATEVHTSS2MCS8;
372 break;
373 case MGN_VHT2SS_MCS9:
374 ret = DESC_RATEVHTSS2MCS9;
375 break;
376 case MGN_VHT3SS_MCS0:
377 ret = DESC_RATEVHTSS3MCS0;
378 break;
379 case MGN_VHT3SS_MCS1:
380 ret = DESC_RATEVHTSS3MCS1;
381 break;
382 case MGN_VHT3SS_MCS2:
383 ret = DESC_RATEVHTSS3MCS2;
384 break;
385 case MGN_VHT3SS_MCS3:
386 ret = DESC_RATEVHTSS3MCS3;
387 break;
388 case MGN_VHT3SS_MCS4:
389 ret = DESC_RATEVHTSS3MCS4;
390 break;
391 case MGN_VHT3SS_MCS5:
392 ret = DESC_RATEVHTSS3MCS5;
393 break;
394 case MGN_VHT3SS_MCS6:
395 ret = DESC_RATEVHTSS3MCS6;
396 break;
397 case MGN_VHT3SS_MCS7:
398 ret = DESC_RATEVHTSS3MCS7;
399 break;
400 case MGN_VHT3SS_MCS8:
401 ret = DESC_RATEVHTSS3MCS8;
402 break;
403 case MGN_VHT3SS_MCS9:
404 ret = DESC_RATEVHTSS3MCS9;
405 break;
406 case MGN_VHT4SS_MCS0:
407 ret = DESC_RATEVHTSS4MCS0;
408 break;
409 case MGN_VHT4SS_MCS1:
410 ret = DESC_RATEVHTSS4MCS1;
411 break;
412 case MGN_VHT4SS_MCS2:
413 ret = DESC_RATEVHTSS4MCS2;
414 break;
415 case MGN_VHT4SS_MCS3:
416 ret = DESC_RATEVHTSS4MCS3;
417 break;
418 case MGN_VHT4SS_MCS4:
419 ret = DESC_RATEVHTSS4MCS4;
420 break;
421 case MGN_VHT4SS_MCS5:
422 ret = DESC_RATEVHTSS4MCS5;
423 break;
424 case MGN_VHT4SS_MCS6:
425 ret = DESC_RATEVHTSS4MCS6;
426 break;
427 case MGN_VHT4SS_MCS7:
428 ret = DESC_RATEVHTSS4MCS7;
429 break;
430 case MGN_VHT4SS_MCS8:
431 ret = DESC_RATEVHTSS4MCS8;
432 break;
433 case MGN_VHT4SS_MCS9:
434 ret = DESC_RATEVHTSS4MCS9;
435 break;
436 default:
437 break;
438 }
439
440 return ret;
441}
442
443u8 HwRateToMRate(u8 rate)
444{
445 u8 ret_rate = MGN_1M;
446
447 switch (rate) {
448 case DESC_RATE1M:
449 ret_rate = MGN_1M;
450 break;
451 case DESC_RATE2M:
452 ret_rate = MGN_2M;
453 break;
454 case DESC_RATE5_5M:
455 ret_rate = MGN_5_5M;
456 break;
457 case DESC_RATE11M:
458 ret_rate = MGN_11M;
459 break;
460 case DESC_RATE6M:
461 ret_rate = MGN_6M;
462 break;
463 case DESC_RATE9M:
464 ret_rate = MGN_9M;
465 break;
466 case DESC_RATE12M:
467 ret_rate = MGN_12M;
468 break;
469 case DESC_RATE18M:
470 ret_rate = MGN_18M;
471 break;
472 case DESC_RATE24M:
473 ret_rate = MGN_24M;
474 break;
475 case DESC_RATE36M:
476 ret_rate = MGN_36M;
477 break;
478 case DESC_RATE48M:
479 ret_rate = MGN_48M;
480 break;
481 case DESC_RATE54M:
482 ret_rate = MGN_54M;
483 break;
484 case DESC_RATEMCS0:
485 ret_rate = MGN_MCS0;
486 break;
487 case DESC_RATEMCS1:
488 ret_rate = MGN_MCS1;
489 break;
490 case DESC_RATEMCS2:
491 ret_rate = MGN_MCS2;
492 break;
493 case DESC_RATEMCS3:
494 ret_rate = MGN_MCS3;
495 break;
496 case DESC_RATEMCS4:
497 ret_rate = MGN_MCS4;
498 break;
499 case DESC_RATEMCS5:
500 ret_rate = MGN_MCS5;
501 break;
502 case DESC_RATEMCS6:
503 ret_rate = MGN_MCS6;
504 break;
505 case DESC_RATEMCS7:
506 ret_rate = MGN_MCS7;
507 break;
508 case DESC_RATEMCS8:
509 ret_rate = MGN_MCS8;
510 break;
511 case DESC_RATEMCS9:
512 ret_rate = MGN_MCS9;
513 break;
514 case DESC_RATEMCS10:
515 ret_rate = MGN_MCS10;
516 break;
517 case DESC_RATEMCS11:
518 ret_rate = MGN_MCS11;
519 break;
520 case DESC_RATEMCS12:
521 ret_rate = MGN_MCS12;
522 break;
523 case DESC_RATEMCS13:
524 ret_rate = MGN_MCS13;
525 break;
526 case DESC_RATEMCS14:
527 ret_rate = MGN_MCS14;
528 break;
529 case DESC_RATEMCS15:
530 ret_rate = MGN_MCS15;
531 break;
532 case DESC_RATEMCS16:
533 ret_rate = MGN_MCS16;
534 break;
535 case DESC_RATEMCS17:
536 ret_rate = MGN_MCS17;
537 break;
538 case DESC_RATEMCS18:
539 ret_rate = MGN_MCS18;
540 break;
541 case DESC_RATEMCS19:
542 ret_rate = MGN_MCS19;
543 break;
544 case DESC_RATEMCS20:
545 ret_rate = MGN_MCS20;
546 break;
547 case DESC_RATEMCS21:
548 ret_rate = MGN_MCS21;
549 break;
550 case DESC_RATEMCS22:
551 ret_rate = MGN_MCS22;
552 break;
553 case DESC_RATEMCS23:
554 ret_rate = MGN_MCS23;
555 break;
556 case DESC_RATEMCS24:
557 ret_rate = MGN_MCS24;
558 break;
559 case DESC_RATEMCS25:
560 ret_rate = MGN_MCS25;
561 break;
562 case DESC_RATEMCS26:
563 ret_rate = MGN_MCS26;
564 break;
565 case DESC_RATEMCS27:
566 ret_rate = MGN_MCS27;
567 break;
568 case DESC_RATEMCS28:
569 ret_rate = MGN_MCS28;
570 break;
571 case DESC_RATEMCS29:
572 ret_rate = MGN_MCS29;
573 break;
574 case DESC_RATEMCS30:
575 ret_rate = MGN_MCS30;
576 break;
577 case DESC_RATEMCS31:
578 ret_rate = MGN_MCS31;
579 break;
580 case DESC_RATEVHTSS1MCS0:
581 ret_rate = MGN_VHT1SS_MCS0;
582 break;
583 case DESC_RATEVHTSS1MCS1:
584 ret_rate = MGN_VHT1SS_MCS1;
585 break;
586 case DESC_RATEVHTSS1MCS2:
587 ret_rate = MGN_VHT1SS_MCS2;
588 break;
589 case DESC_RATEVHTSS1MCS3:
590 ret_rate = MGN_VHT1SS_MCS3;
591 break;
592 case DESC_RATEVHTSS1MCS4:
593 ret_rate = MGN_VHT1SS_MCS4;
594 break;
595 case DESC_RATEVHTSS1MCS5:
596 ret_rate = MGN_VHT1SS_MCS5;
597 break;
598 case DESC_RATEVHTSS1MCS6:
599 ret_rate = MGN_VHT1SS_MCS6;
600 break;
601 case DESC_RATEVHTSS1MCS7:
602 ret_rate = MGN_VHT1SS_MCS7;
603 break;
604 case DESC_RATEVHTSS1MCS8:
605 ret_rate = MGN_VHT1SS_MCS8;
606 break;
607 case DESC_RATEVHTSS1MCS9:
608 ret_rate = MGN_VHT1SS_MCS9;
609 break;
610 case DESC_RATEVHTSS2MCS0:
611 ret_rate = MGN_VHT2SS_MCS0;
612 break;
613 case DESC_RATEVHTSS2MCS1:
614 ret_rate = MGN_VHT2SS_MCS1;
615 break;
616 case DESC_RATEVHTSS2MCS2:
617 ret_rate = MGN_VHT2SS_MCS2;
618 break;
619 case DESC_RATEVHTSS2MCS3:
620 ret_rate = MGN_VHT2SS_MCS3;
621 break;
622 case DESC_RATEVHTSS2MCS4:
623 ret_rate = MGN_VHT2SS_MCS4;
624 break;
625 case DESC_RATEVHTSS2MCS5:
626 ret_rate = MGN_VHT2SS_MCS5;
627 break;
628 case DESC_RATEVHTSS2MCS6:
629 ret_rate = MGN_VHT2SS_MCS6;
630 break;
631 case DESC_RATEVHTSS2MCS7:
632 ret_rate = MGN_VHT2SS_MCS7;
633 break;
634 case DESC_RATEVHTSS2MCS8:
635 ret_rate = MGN_VHT2SS_MCS8;
636 break;
637 case DESC_RATEVHTSS2MCS9:
638 ret_rate = MGN_VHT2SS_MCS9;
639 break;
640 case DESC_RATEVHTSS3MCS0:
641 ret_rate = MGN_VHT3SS_MCS0;
642 break;
643 case DESC_RATEVHTSS3MCS1:
644 ret_rate = MGN_VHT3SS_MCS1;
645 break;
646 case DESC_RATEVHTSS3MCS2:
647 ret_rate = MGN_VHT3SS_MCS2;
648 break;
649 case DESC_RATEVHTSS3MCS3:
650 ret_rate = MGN_VHT3SS_MCS3;
651 break;
652 case DESC_RATEVHTSS3MCS4:
653 ret_rate = MGN_VHT3SS_MCS4;
654 break;
655 case DESC_RATEVHTSS3MCS5:
656 ret_rate = MGN_VHT3SS_MCS5;
657 break;
658 case DESC_RATEVHTSS3MCS6:
659 ret_rate = MGN_VHT3SS_MCS6;
660 break;
661 case DESC_RATEVHTSS3MCS7:
662 ret_rate = MGN_VHT3SS_MCS7;
663 break;
664 case DESC_RATEVHTSS3MCS8:
665 ret_rate = MGN_VHT3SS_MCS8;
666 break;
667 case DESC_RATEVHTSS3MCS9:
668 ret_rate = MGN_VHT3SS_MCS9;
669 break;
670 case DESC_RATEVHTSS4MCS0:
671 ret_rate = MGN_VHT4SS_MCS0;
672 break;
673 case DESC_RATEVHTSS4MCS1:
674 ret_rate = MGN_VHT4SS_MCS1;
675 break;
676 case DESC_RATEVHTSS4MCS2:
677 ret_rate = MGN_VHT4SS_MCS2;
678 break;
679 case DESC_RATEVHTSS4MCS3:
680 ret_rate = MGN_VHT4SS_MCS3;
681 break;
682 case DESC_RATEVHTSS4MCS4:
683 ret_rate = MGN_VHT4SS_MCS4;
684 break;
685 case DESC_RATEVHTSS4MCS5:
686 ret_rate = MGN_VHT4SS_MCS5;
687 break;
688 case DESC_RATEVHTSS4MCS6:
689 ret_rate = MGN_VHT4SS_MCS6;
690 break;
691 case DESC_RATEVHTSS4MCS7:
692 ret_rate = MGN_VHT4SS_MCS7;
693 break;
694 case DESC_RATEVHTSS4MCS8:
695 ret_rate = MGN_VHT4SS_MCS8;
696 break;
697 case DESC_RATEVHTSS4MCS9:
698 ret_rate = MGN_VHT4SS_MCS9;
699 break;
700
701 default:
702 DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate);
703 break;
704 }
705
706 return ret_rate;
707}
708
709void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg)
710{
711 u8 i, is_brate, brate;
712
713 for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
714
715 is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
716 brate = mBratesOS[i] & 0x7f;
717
718 if (is_brate) {
719 switch (brate) {
720 case IEEE80211_CCK_RATE_1MB:
721 *pBrateCfg |= RATE_1M;
722 break;
723 case IEEE80211_CCK_RATE_2MB:
724 *pBrateCfg |= RATE_2M;
725 break;
726 case IEEE80211_CCK_RATE_5MB:
727 *pBrateCfg |= RATE_5_5M;
728 break;
729 case IEEE80211_CCK_RATE_11MB:
730 *pBrateCfg |= RATE_11M;
731 break;
732 case IEEE80211_OFDM_RATE_6MB:
733 *pBrateCfg |= RATE_6M;
734 break;
735 case IEEE80211_OFDM_RATE_9MB:
736 *pBrateCfg |= RATE_9M;
737 break;
738 case IEEE80211_OFDM_RATE_12MB:
739 *pBrateCfg |= RATE_12M;
740 break;
741 case IEEE80211_OFDM_RATE_18MB:
742 *pBrateCfg |= RATE_18M;
743 break;
744 case IEEE80211_OFDM_RATE_24MB:
745 *pBrateCfg |= RATE_24M;
746 break;
747 case IEEE80211_OFDM_RATE_36MB:
748 *pBrateCfg |= RATE_36M;
749 break;
750 case IEEE80211_OFDM_RATE_48MB:
751 *pBrateCfg |= RATE_48M;
752 break;
753 case IEEE80211_OFDM_RATE_54MB:
754 *pBrateCfg |= RATE_54M;
755 break;
756 }
757 }
758 }
759}
760
761static void _OneOutPipeMapping(struct adapter *padapter)
762{
763 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
764
765 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];
766 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];
767 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];
768 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];
769
770 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];
771 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];
772 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];
773 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];
774}
775
776static void _TwoOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
777{
778 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
779
780 if (bWIFICfg) {
781
782
783
784
785
786 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];
787 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];
788 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];
789 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];
790
791 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];
792 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];
793 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];
794 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];
795
796 } else {
797
798
799
800
801
802
803 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];
804 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];
805 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];
806 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];
807
808 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];
809 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];
810 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];
811 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];
812
813 }
814
815}
816
817static void _ThreeOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
818{
819 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
820
821 if (bWIFICfg) {
822
823
824
825
826
827 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];
828 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];
829 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];
830 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];
831
832 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];
833 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];
834 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];
835 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];
836
837 } else {
838
839
840
841
842
843
844 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];
845 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];
846 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];
847 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];
848
849 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];
850 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];
851 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];
852 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];
853 }
854
855}
856
857bool Hal_MappingOutPipe(struct adapter *padapter, u8 NumOutPipe)
858{
859 struct registry_priv *pregistrypriv = &padapter->registrypriv;
860
861 bool bWIFICfg = (pregistrypriv->wifi_spec) ? true : false;
862
863 bool result = true;
864
865 switch (NumOutPipe) {
866 case 2:
867 _TwoOutPipeMapping(padapter, bWIFICfg);
868 break;
869 case 3:
870 case 4:
871 _ThreeOutPipeMapping(padapter, bWIFICfg);
872 break;
873 case 1:
874 _OneOutPipeMapping(padapter);
875 break;
876 default:
877 result = false;
878 break;
879 }
880
881 return result;
882
883}
884
885void hal_init_macaddr(struct adapter *adapter)
886{
887 rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
888}
889
890void rtw_init_hal_com_default_value(struct adapter *Adapter)
891{
892 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
893
894 pHalData->AntDetection = 1;
895}
896
897
898
899
900
901
902
903void c2h_evt_clear(struct adapter *adapter)
904{
905 rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
906}
907
908
909
910
911
912
913s32 c2h_evt_read_88xx(struct adapter *adapter, u8 *buf)
914{
915 s32 ret = _FAIL;
916 struct c2h_evt_hdr_88xx *c2h_evt;
917 int i;
918 u8 trigger;
919
920 if (buf == NULL)
921 goto exit;
922
923 trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
924
925 if (trigger == C2H_EVT_HOST_CLOSE)
926 goto exit;
927 else if (trigger != C2H_EVT_FW_CLOSE)
928 goto clear_evt;
929
930 c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
931
932 memset(c2h_evt, 0, 16);
933
934 c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
935 c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
936 c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
937
938 RT_PRINT_DATA(
939 _module_hal_init_c_,
940 _drv_info_,
941 "c2h_evt_read(): ",
942 &c2h_evt,
943 sizeof(c2h_evt)
944 );
945
946 DBG_871X(
947 "%s id:%u, len:%u, seq:%u, trigger:0x%02x\n",
948 __func__,
949 c2h_evt->id,
950 c2h_evt->plen,
951 c2h_evt->seq,
952 trigger
953 );
954
955
956 for (i = 0; i < c2h_evt->plen; i++)
957 c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
958
959 RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
960 c2h_evt->payload, c2h_evt->plen);
961
962 ret = _SUCCESS;
963
964clear_evt:
965
966
967
968
969 c2h_evt_clear(adapter);
970exit:
971 return ret;
972}
973
974
975u8 rtw_hal_networktype_to_raid(struct adapter *adapter, struct sta_info *psta)
976{
977 return networktype_to_raid_ex(adapter, psta);
978}
979
980u8 rtw_get_mgntframe_raid(struct adapter *adapter, unsigned char network_type)
981{
982
983 u8 raid;
984 raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B : RATEID_IDX_G;
985 return raid;
986}
987
988void rtw_hal_update_sta_rate_mask(struct adapter *padapter, struct sta_info *psta)
989{
990 u8 i, rf_type, limit;
991 u32 tx_ra_bitmap;
992
993 if (psta == NULL)
994 return;
995
996 tx_ra_bitmap = 0;
997
998
999 for (i = 0; i < sizeof(psta->bssrateset); i++) {
1000 if (psta->bssrateset[i])
1001 tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
1002 }
1003
1004
1005 if (psta->htpriv.ht_option) {
1006 rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
1007 if (rf_type == RF_2T2R)
1008 limit = 16;
1009 else
1010 limit = 8;
1011
1012 for (i = 0; i < limit; i++) {
1013 if (psta->htpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8))
1014 tx_ra_bitmap |= BIT(i+12);
1015 }
1016 }
1017
1018 psta->ra_mask = tx_ra_bitmap;
1019 psta->init_rate = get_highest_rate_idx(tx_ra_bitmap)&0x3f;
1020}
1021
1022void hw_var_port_switch(struct adapter *adapter)
1023{
1024}
1025
1026void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1027{
1028 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1029 DM_ODM_T *odm = &(hal_data->odmpriv);
1030
1031 switch (variable) {
1032 case HW_VAR_PORT_SWITCH:
1033 hw_var_port_switch(adapter);
1034 break;
1035 case HW_VAR_INIT_RTS_RATE:
1036 rtw_warn_on(1);
1037 break;
1038 case HW_VAR_SEC_CFG:
1039 {
1040 u16 reg_scr;
1041
1042 reg_scr = rtw_read16(adapter, REG_SECCFG);
1043 rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
1044 }
1045 break;
1046 case HW_VAR_SEC_DK_CFG:
1047 {
1048 struct security_priv *sec = &adapter->securitypriv;
1049 u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
1050
1051 if (val) {
1052 reg_scr |= SCR_TXBCUSEDK;
1053 if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
1054 reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
1055 } else
1056 reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
1057
1058 rtw_write8(adapter, REG_SECCFG, reg_scr);
1059 }
1060 break;
1061 case HW_VAR_DM_FLAG:
1062 odm->SupportAbility = *((u32 *)val);
1063 break;
1064 case HW_VAR_DM_FUNC_OP:
1065 if (*((u8 *)val) == true) {
1066
1067 odm->BK_SupportAbility = odm->SupportAbility;
1068 } else {
1069
1070 odm->SupportAbility = odm->BK_SupportAbility;
1071 }
1072 break;
1073 case HW_VAR_DM_FUNC_SET:
1074 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1075 struct dm_priv *dm = &hal_data->dmpriv;
1076 dm->DMFlag = dm->InitDMFlag;
1077 odm->SupportAbility = dm->InitODMFlag;
1078 } else {
1079 odm->SupportAbility |= *((u32 *)val);
1080 }
1081 break;
1082 case HW_VAR_DM_FUNC_CLR:
1083
1084
1085
1086
1087 odm->SupportAbility &= *((u32 *)val);
1088 break;
1089 case HW_VAR_AMPDU_MIN_SPACE:
1090
1091 break;
1092 case HW_VAR_WIRELESS_MODE:
1093
1094 break;
1095 default:
1096 DBG_871X_LEVEL(
1097 _drv_always_,
1098 FUNC_ADPT_FMT" variable(%d) not defined!\n",
1099 FUNC_ADPT_ARG(adapter),
1100 variable
1101 );
1102 break;
1103 }
1104}
1105
1106void GetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1107{
1108 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1109 DM_ODM_T *odm = &(hal_data->odmpriv);
1110
1111 switch (variable) {
1112 case HW_VAR_BASIC_RATE:
1113 *((u16 *)val) = hal_data->BasicRateSet;
1114 break;
1115 case HW_VAR_DM_FLAG:
1116 *((u32 *)val) = odm->SupportAbility;
1117 break;
1118 case HW_VAR_RF_TYPE:
1119 *((u8 *)val) = hal_data->rf_type;
1120 break;
1121 default:
1122 DBG_871X_LEVEL(
1123 _drv_always_,
1124 FUNC_ADPT_FMT" variable(%d) not defined!\n",
1125 FUNC_ADPT_ARG(adapter),
1126 variable
1127 );
1128 break;
1129 }
1130}
1131
1132
1133
1134
1135u8 SetHalDefVar(
1136 struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1137)
1138{
1139 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1140 DM_ODM_T *odm = &(hal_data->odmpriv);
1141 u8 bResult = _SUCCESS;
1142
1143 switch (variable) {
1144 case HW_DEF_FA_CNT_DUMP:
1145
1146 if (*((u8 *)value))
1147 odm->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
1148 else
1149 odm->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
1150 break;
1151 case HAL_DEF_DBG_RX_INFO_DUMP:
1152 DBG_871X("============ Rx Info dump ===================\n");
1153 DBG_871X("bLinked = %d, RSSI_Min = %d(%%)\n",
1154 odm->bLinked, odm->RSSI_Min);
1155
1156 if (odm->bLinked) {
1157 DBG_871X("RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
1158 HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
1159
1160 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1161 rtw_dump_raw_rssi_info(adapter);
1162 #endif
1163 }
1164 break;
1165 case HW_DEF_ODM_DBG_FLAG:
1166 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_COMP, *((u64 *)value));
1167 break;
1168 case HW_DEF_ODM_DBG_LEVEL:
1169 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_LEVEL, *((u32 *)value));
1170 break;
1171 case HAL_DEF_DBG_DM_FUNC:
1172 {
1173 u8 dm_func = *((u8 *)value);
1174 struct dm_priv *dm = &hal_data->dmpriv;
1175
1176 if (dm_func == 0) {
1177 odm->SupportAbility = DYNAMIC_FUNC_DISABLE;
1178 DBG_8192C("==> Disable all dynamic function...\n");
1179 } else if (dm_func == 1) {
1180 odm->SupportAbility &= (~DYNAMIC_BB_DIG);
1181 DBG_8192C("==> Disable DIG...\n");
1182 } else if (dm_func == 2) {
1183 odm->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1184 } else if (dm_func == 3) {
1185 odm->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
1186 DBG_8192C("==> Disable tx power tracking...\n");
1187 } else if (dm_func == 4) {
1188 dm->DMFlag &= (~DYNAMIC_FUNC_BT);
1189 } else if (dm_func == 5) {
1190 odm->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
1191 } else if (dm_func == 6) {
1192 if (!(odm->SupportAbility & DYNAMIC_BB_DIG)) {
1193 DIG_T *pDigTable = &odm->DM_DigTable;
1194 pDigTable->CurIGValue = rtw_read8(adapter, 0xc50);
1195 }
1196 dm->DMFlag |= DYNAMIC_FUNC_BT;
1197 odm->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
1198 DBG_8192C("==> Turn on all dynamic function...\n");
1199 }
1200 }
1201 break;
1202 case HAL_DEF_DBG_DUMP_RXPKT:
1203 hal_data->bDumpRxPkt = *((u8 *)value);
1204 break;
1205 case HAL_DEF_DBG_DUMP_TXPKT:
1206 hal_data->bDumpTxPkt = *((u8 *)value);
1207 break;
1208 case HAL_DEF_ANT_DETECT:
1209 hal_data->AntDetection = *((u8 *)value);
1210 break;
1211 default:
1212 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1213 bResult = _FAIL;
1214 break;
1215 }
1216
1217 return bResult;
1218}
1219
1220u8 GetHalDefVar(
1221 struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1222)
1223{
1224 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1225 DM_ODM_T *odm = &(hal_data->odmpriv);
1226 u8 bResult = _SUCCESS;
1227
1228 switch (variable) {
1229 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1230 {
1231 struct mlme_priv *pmlmepriv;
1232 struct sta_priv *pstapriv;
1233 struct sta_info *psta;
1234
1235 pmlmepriv = &adapter->mlmepriv;
1236 pstapriv = &adapter->stapriv;
1237 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1238 if (psta)
1239 *((int *)value) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1240 }
1241 break;
1242 case HW_DEF_ODM_DBG_FLAG:
1243 *((u64 *)value) = odm->DebugComponents;
1244 break;
1245 case HW_DEF_ODM_DBG_LEVEL:
1246 *((u32 *)value) = odm->DebugLevel;
1247 break;
1248 case HAL_DEF_DBG_DM_FUNC:
1249 *((u32 *)value) = hal_data->odmpriv.SupportAbility;
1250 break;
1251 case HAL_DEF_DBG_DUMP_RXPKT:
1252 *((u8 *)value) = hal_data->bDumpRxPkt;
1253 break;
1254 case HAL_DEF_DBG_DUMP_TXPKT:
1255 *((u8 *)value) = hal_data->bDumpTxPkt;
1256 break;
1257 case HAL_DEF_ANT_DETECT:
1258 *((u8 *)value) = hal_data->AntDetection;
1259 break;
1260 case HAL_DEF_MACID_SLEEP:
1261 *(u8 *)value = false;
1262 break;
1263 case HAL_DEF_TX_PAGE_SIZE:
1264 *((u32 *)value) = PAGE_SIZE_128;
1265 break;
1266 default:
1267 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1268 bResult = _FAIL;
1269 break;
1270 }
1271
1272 return bResult;
1273}
1274
1275void GetHalODMVar(
1276 struct adapter *Adapter,
1277 enum HAL_ODM_VARIABLE eVariable,
1278 void *pValue1,
1279 void *pValue2
1280)
1281{
1282 switch (eVariable) {
1283#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1284 case HAL_ODM_NOISE_MONITOR:
1285 {
1286 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1287 u8 chan = *(u8 *)pValue1;
1288 *(s16 *)pValue2 = pHalData->noise[chan];
1289 #ifdef DBG_NOISE_MONITOR
1290 DBG_8192C("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
1291 chan, pHalData->noise[chan]);
1292 #endif
1293
1294 }
1295 break;
1296#endif
1297 default:
1298 break;
1299 }
1300}
1301
1302void SetHalODMVar(
1303 struct adapter *Adapter,
1304 enum HAL_ODM_VARIABLE eVariable,
1305 void *pValue1,
1306 bool bSet
1307)
1308{
1309 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1310 PDM_ODM_T podmpriv = &pHalData->odmpriv;
1311
1312 switch (eVariable) {
1313 case HAL_ODM_STA_INFO:
1314 {
1315 struct sta_info *psta = pValue1;
1316 if (bSet) {
1317 DBG_8192C("### Set STA_(%d) info ###\n", psta->mac_id);
1318 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
1319 } else {
1320 DBG_8192C("### Clean STA_(%d) info ###\n", psta->mac_id);
1321
1322 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
1323
1324
1325 }
1326 }
1327 break;
1328 case HAL_ODM_P2P_STATE:
1329 ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1330 break;
1331 case HAL_ODM_WIFI_DISPLAY_STATE:
1332 ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1333 break;
1334 #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1335 case HAL_ODM_NOISE_MONITOR:
1336 {
1337 struct noise_info *pinfo = pValue1;
1338
1339 #ifdef DBG_NOISE_MONITOR
1340 DBG_8192C("### Noise monitor chan(%d)-bPauseDIG:%d, IGIValue:0x%02x, max_time:%d (ms) ###\n",
1341 pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1342 #endif
1343
1344 pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1345 DBG_871X("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]);
1346 #ifdef DBG_NOISE_MONITOR
1347 DBG_871X("noise_a = %d, noise_b = %d noise_all:%d\n",
1348 podmpriv->noise_level.noise[ODM_RF_PATH_A],
1349 podmpriv->noise_level.noise[ODM_RF_PATH_B],
1350 podmpriv->noise_level.noise_all);
1351 #endif
1352 }
1353 break;
1354 #endif
1355
1356 default:
1357 break;
1358 }
1359}
1360
1361
1362bool eqNByte(u8 *str1, u8 *str2, u32 num)
1363{
1364 if (num == 0)
1365 return false;
1366 while (num > 0) {
1367 num--;
1368 if (str1[num] != str2[num])
1369 return false;
1370 }
1371 return true;
1372}
1373
1374
1375
1376
1377
1378
1379
1380bool IsHexDigit(char chTmp)
1381{
1382 if (
1383 (chTmp >= '0' && chTmp <= '9') ||
1384 (chTmp >= 'a' && chTmp <= 'f') ||
1385 (chTmp >= 'A' && chTmp <= 'F')
1386 )
1387 return true;
1388 else
1389 return false;
1390}
1391
1392
1393
1394
1395
1396
1397u32 MapCharToHexDigit(char chTmp)
1398{
1399 if (chTmp >= '0' && chTmp <= '9')
1400 return (chTmp - '0');
1401 else if (chTmp >= 'a' && chTmp <= 'f')
1402 return (10 + (chTmp - 'a'));
1403 else if (chTmp >= 'A' && chTmp <= 'F')
1404 return (10 + (chTmp - 'A'));
1405 else
1406 return 0;
1407}
1408
1409
1410
1411
1412
1413bool GetHexValueFromString(char *szStr, u32 *pu4bVal, u32 *pu4bMove)
1414{
1415 char *szScan = szStr;
1416
1417
1418 if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
1419 DBG_871X("GetHexValueFromString(): Invalid input arguments! szStr: %p, pu4bVal: %p, pu4bMove: %p\n",
1420 szStr, pu4bVal, pu4bMove);
1421 return false;
1422 }
1423
1424
1425 *pu4bMove = 0;
1426 *pu4bVal = 0;
1427
1428
1429 while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
1430 szScan++;
1431 (*pu4bMove)++;
1432 }
1433
1434
1435 if (*szScan == '0' && (*(szScan+1) == 'x' || *(szScan+1) == 'X')) {
1436 szScan += 2;
1437 (*pu4bMove) += 2;
1438 }
1439
1440
1441
1442 if (!IsHexDigit(*szScan))
1443 return false;
1444
1445
1446 do {
1447 (*pu4bVal) <<= 4;
1448 *pu4bVal += MapCharToHexDigit(*szScan);
1449
1450 szScan++;
1451 (*pu4bMove)++;
1452 } while (IsHexDigit(*szScan));
1453
1454 return true;
1455}
1456
1457bool GetFractionValueFromString(
1458 char *szStr, u8 *pInteger, u8 *pFraction, u32 *pu4bMove
1459)
1460{
1461 char *szScan = szStr;
1462
1463
1464 *pu4bMove = 0;
1465 *pInteger = 0;
1466 *pFraction = 0;
1467
1468
1469 while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
1470 ++szScan;
1471 ++(*pu4bMove);
1472 }
1473
1474
1475 do {
1476 (*pInteger) *= 10;
1477 *pInteger += (*szScan - '0');
1478
1479 ++szScan;
1480 ++(*pu4bMove);
1481
1482 if (*szScan == '.') {
1483 ++szScan;
1484 ++(*pu4bMove);
1485
1486 if (*szScan < '0' || *szScan > '9')
1487 return false;
1488 else {
1489 *pFraction = *szScan - '0';
1490 ++szScan;
1491 ++(*pu4bMove);
1492 return true;
1493 }
1494 }
1495 } while (*szScan >= '0' && *szScan <= '9');
1496
1497 return true;
1498}
1499
1500
1501
1502
1503
1504bool IsCommentString(char *szStr)
1505{
1506 if (*szStr == '/' && *(szStr+1) == '/')
1507 return true;
1508 else
1509 return false;
1510}
1511
1512bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
1513{
1514 u16 i = 0;
1515 *pInt = 0;
1516
1517 while (Str[i] != '\0') {
1518 if (Str[i] >= '0' && Str[i] <= '9') {
1519 *pInt *= 10;
1520 *pInt += (Str[i] - '0');
1521 } else
1522 return false;
1523
1524 ++i;
1525 }
1526
1527 return true;
1528}
1529
1530
1531
1532
1533
1534
1535bool ParseQualifiedString(
1536 char *In, u32 *Start, char *Out, char LeftQualifier, char RightQualifier
1537)
1538{
1539 u32 i = 0, j = 0;
1540 char c = In[(*Start)++];
1541
1542 if (c != LeftQualifier)
1543 return false;
1544
1545 i = (*Start);
1546 while ((c = In[(*Start)++]) != RightQualifier)
1547 ;
1548 j = (*Start) - 2;
1549 strncpy((char *)Out, (const char *)(In+i), j-i+1);
1550
1551 return true;
1552}
1553
1554bool isAllSpaceOrTab(u8 *data, u8 size)
1555{
1556 u8 cnt = 0, NumOfSpaceAndTab = 0;
1557
1558 while (size > cnt) {
1559 if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
1560 ++NumOfSpaceAndTab;
1561
1562 ++cnt;
1563 }
1564
1565 return size == NumOfSpaceAndTab;
1566}
1567
1568
1569void rtw_hal_check_rxfifo_full(struct adapter *adapter)
1570{
1571 struct dvobj_priv *psdpriv = adapter->dvobj;
1572 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1573 int save_cnt = false;
1574
1575
1576
1577 rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
1578 save_cnt = true;
1579
1580
1581 if (save_cnt) {
1582
1583 pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
1584 pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
1585 pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
1586 }
1587}
1588
1589void linked_info_dump(struct adapter *padapter, u8 benable)
1590{
1591 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1592
1593 if (padapter->bLinkInfoDump == benable)
1594 return;
1595
1596 DBG_871X("%s %s\n", __func__, (benable) ? "enable" : "disable");
1597
1598 if (benable) {
1599 pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;
1600 rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
1601
1602 pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;
1603 rtw_pm_set_ips(padapter, IPS_NONE);
1604 } else {
1605 rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
1606
1607 rtw_pm_set_lps(padapter, pwrctrlpriv->ips_org_mode);
1608 }
1609 padapter->bLinkInfoDump = benable;
1610}
1611
1612#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1613void rtw_get_raw_rssi_info(void *sel, struct adapter *padapter)
1614{
1615 u8 isCCKrate, rf_path;
1616 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1617 struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1618
1619 DBG_871X_SEL_NL(
1620 sel,
1621 "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1622 HDATA_RATE(psample_pkt_rssi->data_rate),
1623 psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all
1624 );
1625
1626 isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1627
1628 if (isCCKrate)
1629 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1630
1631 for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1632 DBG_871X_SEL_NL(
1633 sel,
1634 "RF_PATH_%d =>singal_strength:%d(%%), singal_quality:%d(%%)\n",
1635 rf_path, psample_pkt_rssi->mimo_singal_strength[rf_path],
1636 psample_pkt_rssi->mimo_singal_quality[rf_path]
1637 );
1638
1639 if (!isCCKrate) {
1640 DBG_871X_SEL_NL(
1641 sel,
1642 "\trx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1643 psample_pkt_rssi->ofdm_pwr[rf_path],
1644 psample_pkt_rssi->ofdm_snr[rf_path]
1645 );
1646 }
1647 }
1648}
1649
1650void rtw_dump_raw_rssi_info(struct adapter *padapter)
1651{
1652 u8 isCCKrate, rf_path;
1653 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1654 struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1655 DBG_871X("============ RAW Rx Info dump ===================\n");
1656 DBG_871X("RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1657 HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
1658
1659 isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1660
1661 if (isCCKrate)
1662 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1663
1664 for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1665 DBG_871X("RF_PATH_%d =>singal_strength:%d(%%), singal_quality:%d(%%)"
1666 , rf_path, psample_pkt_rssi->mimo_singal_strength[rf_path], psample_pkt_rssi->mimo_singal_quality[rf_path]);
1667
1668 if (!isCCKrate) {
1669 printk(", rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1670 psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
1671 } else {
1672 printk("\n");
1673 }
1674 }
1675}
1676
1677void rtw_store_phy_info(struct adapter *padapter, union recv_frame *prframe)
1678{
1679 u8 isCCKrate, rf_path;
1680 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1681 struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
1682
1683 struct odm_phy_info *pPhyInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info);
1684 struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1685
1686 psample_pkt_rssi->data_rate = pattrib->data_rate;
1687 isCCKrate = pattrib->data_rate <= DESC_RATE11M;
1688
1689 psample_pkt_rssi->pwdball = pPhyInfo->rx_pwd_ba11;
1690 psample_pkt_rssi->pwr_all = pPhyInfo->recv_signal_power;
1691
1692 for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1693 psample_pkt_rssi->mimo_singal_strength[rf_path] = pPhyInfo->rx_mimo_signal_strength[rf_path];
1694 psample_pkt_rssi->mimo_singal_quality[rf_path] = pPhyInfo->rx_mimo_signal_quality[rf_path];
1695 if (!isCCKrate) {
1696 psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
1697 psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
1698 }
1699 }
1700}
1701#endif
1702
1703static u32 Array_kfreemap[] = {
1704 0xf8, 0xe,
1705 0xf6, 0xc,
1706 0xf4, 0xa,
1707 0xf2, 0x8,
1708 0xf0, 0x6,
1709 0xf3, 0x4,
1710 0xf5, 0x2,
1711 0xf7, 0x0,
1712 0xf9, 0x0,
1713 0xfc, 0x0,
1714};
1715
1716void rtw_bb_rf_gain_offset(struct adapter *padapter)
1717{
1718 u8 value = padapter->eeprompriv.EEPROMRFGainOffset;
1719 u32 res, i = 0;
1720 u32 *Array = Array_kfreemap;
1721 u32 v1 = 0, v2 = 0, target = 0;
1722
1723
1724 if (value & BIT4) {
1725 DBG_871X("Offset RF Gain.\n");
1726 DBG_871X("Offset RF Gain. padapter->eeprompriv.EEPROMRFGainVal = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal);
1727 if (padapter->eeprompriv.EEPROMRFGainVal != 0xff) {
1728 res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1729 res &= 0xfff87fff;
1730 DBG_871X("Offset RF Gain. before reg 0x7f = 0x%08x\n", res);
1731
1732 for (i = 0; i < ARRAY_SIZE(Array_kfreemap); i += 2) {
1733 v1 = Array[i];
1734 v2 = Array[i+1];
1735 if (v1 == padapter->eeprompriv.EEPROMRFGainVal) {
1736 DBG_871X("Offset RF Gain. got v1 = 0x%x , v2 = 0x%x\n", v1, v2);
1737 target = v2;
1738 break;
1739 }
1740 }
1741 DBG_871X("padapter->eeprompriv.EEPROMRFGainVal = 0x%x , Gain offset Target Value = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal, target);
1742 PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
1743
1744
1745
1746 res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1747 DBG_871X("Offset RF Gain. After reg 0x7f = 0x%08x\n", res);
1748 } else
1749 DBG_871X("Offset RF Gain. padapter->eeprompriv.EEPROMRFGainVal = 0x%x != 0xff, didn't run Kfree\n", padapter->eeprompriv.EEPROMRFGainVal);
1750 } else
1751 DBG_871X("Using the default RF gain.\n");
1752}
1753
