LXR linux/drivers/staging/rtl8723bs/hal/odm.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12 * more details.
  13 *
  14 ******************************************************************************/
  15
  16
  17#ifndef __HALDMOUTSRC_H__
  18#define __HALDMOUTSRC_H__
  19
  20#include "odm_EdcaTurboCheck.h"
  21#include "odm_DIG.h"
  22#include "odm_PathDiv.h"
  23#include "odm_DynamicBBPowerSaving.h"
  24#include "odm_DynamicTxPower.h"
  25#include "odm_CfoTracking.h"
  26#include "odm_NoiseMonitor.h"
  27
  28#define TP_MODE         0
  29#define RSSI_MODE               1
  30#define TRAFFIC_LOW     0
  31#define TRAFFIC_HIGH    1
  32#define NONE                    0
  33
  34/* 3 Tx Power Tracking */
  35/* 3 ============================================================ */
  36#define         DPK_DELTA_MAPPING_NUM   13
  37#define         index_mapping_HP_NUM    15
  38#define OFDM_TABLE_SIZE         43
  39#define CCK_TABLE_SIZE                  33
  40#define TXSCALE_TABLE_SIZE              37
  41#define TXPWR_TRACK_TABLE_SIZE  30
  42#define DELTA_SWINGIDX_SIZE     30
  43#define BAND_NUM                                4
  44
  45/* 3 PSD Handler */
  46/* 3 ============================================================ */
  47
  48#define AFH_PSD         1       /* 0:normal PSD scan, 1: only do 20 pts PSD */
  49#define MODE_40M                0       /* 0:20M, 1:40M */
  50#define PSD_TH2         3
  51#define PSD_CHMIN               20   /*  Minimum channel number for BT AFH */
  52#define SIR_STEP_SIZE   3
  53#define   Smooth_Size_1         5
  54#define Smooth_TH_1     3
  55#define   Smooth_Size_2         10
  56#define Smooth_TH_2     4
  57#define   Smooth_Size_3         20
  58#define Smooth_TH_3     4
  59#define   Smooth_Step_Size 5
  60#define Adaptive_SIR    1
  61#define PSD_RESCAN              4
  62#define PSD_SCAN_INTERVAL       700 /* ms */
  63
  64/* 8723A High Power IGI Setting */
  65#define         DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  66#define                 DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
  67#define         DM_DIG_HIGH_PWR_THRESHOLD       0x3a
  68#define         DM_DIG_LOW_PWR_THRESHOLD        0x14
  69
  70/* ANT Test */
  71#define                 ANTTESTALL              0x00            /* Ant A or B will be Testing */
  72#define         ANTTESTA                0x01            /* Ant A will be Testing */
  73#define         ANTTESTB                0x02            /* Ant B will be testing */
  74
  75#define PS_MODE_ACTIVE 0x01
  76
  77/* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */
  78#define         MAIN_ANT                1               /* Ant A or Ant Main */
  79#define         AUX_ANT         2               /* AntB or Ant Aux */
  80#define         MAX_ANT         3               /*  3 for AP using */
  81
  82/* Antenna Diversity Type */
  83#define SW_ANTDIV       0
  84#define HW_ANTDIV       1
  85/*  structure and define */
  86
  87/* Remove DIG by Yuchen */
  88
  89/* Remoce BB power saving by Yuchn */
  90
  91/* Remove DIG by yuchen */
  92
  93typedef struct _Dynamic_Primary_CCA {
  94        u8 PriCCA_flag;
  95        u8 intf_flag;
  96        u8 intf_type;
  97        u8 DupRTS_flag;
  98        u8 Monitor_flag;
  99        u8 CH_offset;
 100        u8      MF_state;
 101} Pri_CCA_T, *pPri_CCA_T;
 102
 103typedef struct _Rate_Adaptive_Table_ {
 104        u8 firstconnect;
 105} RA_T, *pRA_T;
 106
 107typedef struct _RX_High_Power_ {
 108        u8 RXHP_flag;
 109        u8 PSD_func_trigger;
 110        u8 PSD_bitmap_RXHP[80];
 111        u8 Pre_IGI;
 112        u8 Cur_IGI;
 113        u8 Pre_pw_th;
 114        u8 Cur_pw_th;
 115        bool First_time_enter;
 116        bool RXHP_enable;
 117        u8 TP_Mode;
 118        RT_TIMER PSDTimer;
 119} RXHP_T, *pRXHP_T;
 120
 121#define ASSOCIATE_ENTRY_NUM                                     32 /*  Max size of AsocEntry[]. */
 122#define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM
 123
 124/*  This indicates two different the steps. */
 125/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
 126/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
 127/*  with original RSSI to determine if it is necessary to switch antenna. */
 128#define SWAW_STEP_PEAK          0
 129#define SWAW_STEP_DETERMINE     1
 130
 131#define TP_MODE         0
 132#define RSSI_MODE               1
 133#define TRAFFIC_LOW     0
 134#define TRAFFIC_HIGH    1
 135#define TRAFFIC_UltraLOW        2
 136
 137typedef struct _SW_Antenna_Switch_ {
 138        u8 Double_chk_flag;
 139        u8 try_flag;
 140        s32 PreRSSI;
 141        u8 CurAntenna;
 142        u8 PreAntenna;
 143        u8 RSSI_Trying;
 144        u8 TestMode;
 145        u8 bTriggerAntennaSwitch;
 146        u8 SelectAntennaMap;
 147        u8 RSSI_target;
 148        u8 reset_idx;
 149        u16 Single_Ant_Counter;
 150        u16 Dual_Ant_Counter;
 151        u16 Aux_FailDetec_Counter;
 152        u16 Retry_Counter;
 153
 154        /*  Before link Antenna Switch check */
 155        u8 SWAS_NoLink_State;
 156        u32 SWAS_NoLink_BK_Reg860;
 157        u32 SWAS_NoLink_BK_Reg92c;
 158        u32 SWAS_NoLink_BK_Reg948;
 159        bool ANTA_ON;   /* To indicate Ant A is or not */
 160        bool ANTB_ON;   /* To indicate Ant B is on or not */
 161        bool Pre_Aux_FailDetec;
 162        bool RSSI_AntDect_bResult;
 163        u8 Ant5G;
 164        u8 Ant2G;
 165
 166        s32 RSSI_sum_A;
 167        s32 RSSI_sum_B;
 168        s32 RSSI_cnt_A;
 169        s32 RSSI_cnt_B;
 170
 171        u64 lastTxOkCnt;
 172        u64 lastRxOkCnt;
 173        u64 TXByteCnt_A;
 174        u64 TXByteCnt_B;
 175        u64 RXByteCnt_A;
 176        u64 RXByteCnt_B;
 177        u8 TrafficLoad;
 178        u8 Train_time;
 179        u8 Train_time_flag;
 180        RT_TIMER SwAntennaSwitchTimer;
 181        RT_TIMER SwAntennaSwitchTimer_8723B;
 182        u32 PktCnt_SWAntDivByCtrlFrame;
 183        bool bSWAntDivByCtrlFrame;
 184} SWAT_T, *pSWAT_T;
 185
 186/* Remove Edca by YuChen */
 187
 188
 189typedef struct _ODM_RATE_ADAPTIVE {
 190        u8 Type;                                /*  DM_Type_ByFW/DM_Type_ByDriver */
 191        u8 LdpcThres;                   /*  if RSSI > LdpcThres => switch from LPDC to BCC */
 192        bool bUseLdpc;
 193        bool bLowerRtsRate;
 194        u8 HighRSSIThresh;              /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
 195        u8 LowRSSIThresh;               /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
 196        u8 RATRState;                   /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
 197
 198} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
 199
 200#define IQK_MAC_REG_NUM         4
 201#define IQK_ADDA_REG_NUM                16
 202#define IQK_BB_REG_NUM_MAX      10
 203#define IQK_BB_REG_NUM          9
 204#define HP_THERMAL_NUM          8
 205
 206#define AVG_THERMAL_NUM         8
 207#define IQK_Matrix_REG_NUM      8
 208#define IQK_Matrix_Settings_NUM (14 + 24 + 21) /*   Channels_2_4G_NUM
 209                                                * + Channels_5G_20M_NUM
 210                                                * + Channels_5G
 211                                                */
 212
 213#define         DM_Type_ByFW                    0
 214#define         DM_Type_ByDriver                1
 215
 216/*  */
 217/*  Declare for common info */
 218/*  */
 219#define MAX_PATH_NUM_92CS               2
 220#define MAX_PATH_NUM_8188E              1
 221#define MAX_PATH_NUM_8192E              2
 222#define MAX_PATH_NUM_8723B              1
 223#define MAX_PATH_NUM_8812A              2
 224#define MAX_PATH_NUM_8821A              1
 225#define MAX_PATH_NUM_8814A              4
 226#define MAX_PATH_NUM_8822B              2
 227
 228#define IQK_THRESHOLD                   8
 229#define DPK_THRESHOLD                   4
 230
 231struct odm_phy_info {
 232        /*
 233         *  Be care, if you want to add any element, please insert it between
 234         *  rx_pwd_ball and signal_strength.
 235         */
 236        u8 rx_pwd_ba11;
 237
 238        u8 signal_quality;             /* in 0-100 index. */
 239        s8 rx_mimo_signal_quality[4];  /* per-path's EVM */
 240        u8 rx_mimo_evm_dbm[4];         /* per-path's EVM dbm */
 241
 242        u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
 243
 244        u16 cfo_short[4];              /* per-path's Cfo_short */
 245        u16 cfo_tail[4];               /* per-path's Cfo_tail */
 246
 247        s8 rx_power;                   /* in dBm Translate from PWdB */
 248
 249        /*
 250         * Real power in dBm for this packet, no beautification and
 251         * aggregation. Keep this raw info to be used for the other procedures.
 252         */
 253        s8 recv_signal_power;
 254        u8 bt_rx_rssi_percentage;
 255        u8 signal_strength;            /* in 0-100 index. */
 256
 257        s8 rx_pwr[4];                  /* per-path's pwdb */
 258
 259        u8 rx_snr[4];                  /* per-path's SNR */
 260        u8 band_width;
 261        u8 bt_coex_pwr_adjust;
 262};
 263
 264struct odm_packet_info {
 265        u8 data_rate;
 266        u8 station_id;
 267        bool bssid_match;
 268        bool to_self;
 269        bool is_beacon;
 270};
 271
 272typedef struct _ODM_Phy_Dbg_Info_ {
 273        /* ODM Write, debug info */
 274        s8 RxSNRdB[4];
 275        u32 NumQryPhyStatus;
 276        u32 NumQryPhyStatusCCK;
 277        u32 NumQryPhyStatusOFDM;
 278        u8 NumQryBeaconPkt;
 279        /* Others */
 280        s32 RxEVM[4];
 281
 282} ODM_PHY_DBG_INFO_T;
 283
 284typedef struct _ODM_Mac_Status_Info_ {
 285        u8 test;
 286} ODM_MAC_INFO;
 287
 288typedef enum tag_Dynamic_ODM_Support_Ability_Type {
 289        /*  BB Team */
 290        ODM_DIG                         = 0x00000001,
 291        ODM_HIGH_POWER          = 0x00000002,
 292        ODM_CCK_CCA_TH          = 0x00000004,
 293        ODM_FA_STATISTICS       = 0x00000008,
 294        ODM_RAMASK                      = 0x00000010,
 295        ODM_RSSI_MONITOR        = 0x00000020,
 296        ODM_SW_ANTDIV           = 0x00000040,
 297        ODM_HW_ANTDIV           = 0x00000080,
 298        ODM_BB_PWRSV            = 0x00000100,
 299        ODM_2TPATHDIV           = 0x00000200,
 300        ODM_1TPATHDIV           = 0x00000400,
 301        ODM_PSD2AFH                     = 0x00000800
 302} ODM_Ability_E;
 303
 304/*  */
 305/*  2011/20/20 MH For MP driver RT_WLAN_STA =  STA_INFO_T */
 306/*  Please declare below ODM relative info in your STA info structure. */
 307/*  */
 308typedef struct _ODM_STA_INFO {
 309        /*  Driver Write */
 310        bool bUsed;                             /*  record the sta status link or not? */
 311        /* u8 WirelessMode;              */
 312        u8 IOTPeer;                     /*  Enum value. HT_IOT_PEER_E */
 313
 314        /*  ODM Write */
 315        /* 1 PHY_STATUS_INFO */
 316        u8 RSSI_Path[4];                /*  */
 317        u8 RSSI_Ave;
 318        u8 RXEVM[4];
 319        u8 RXSNR[4];
 320
 321        /*  ODM Write */
 322        /* 1 TX_INFO (may changed by IC) */
 323        /* TX_INFO_T            pTxInfo;                Define in IC folder. Move lower layer. */
 324
 325        /*  */
 326        /*      Please use compile flag to disabe the strcutrue for other IC except 88E. */
 327        /*      Move To lower layer. */
 328        /*  */
 329        /*  ODM Write Wilson will handle this part(said by Luke.Lee) */
 330        /* TX_RPT_T             pTxRpt;                 Define in IC folder. Move lower layer. */
 331} ODM_STA_INFO_T, *PODM_STA_INFO_T;
 332
 333/*  */
 334/*  2011/10/20 MH Define Common info enum for all team. */
 335/*  */
 336typedef enum _ODM_Common_Info_Definition {
 337        /*  Fixed value: */
 338
 339        /* HOOK BEFORE REG INIT----------- */
 340        ODM_CMNINFO_PLATFORM = 0,
 341        ODM_CMNINFO_ABILITY,                                    /*  ODM_ABILITY_E */
 342        ODM_CMNINFO_INTERFACE,                          /*  ODM_INTERFACE_E */
 343        ODM_CMNINFO_MP_TEST_CHIP,
 344        ODM_CMNINFO_IC_TYPE,                                    /*  ODM_IC_TYPE_E */
 345        ODM_CMNINFO_CUT_VER,                                    /*  ODM_CUT_VERSION_E */
 346        ODM_CMNINFO_FAB_VER,                                    /*  ODM_FAB_E */
 347        ODM_CMNINFO_RF_TYPE,                                    /*  ODM_RF_PATH_E or ODM_RF_TYPE_E? */
 348        ODM_CMNINFO_RFE_TYPE,
 349        ODM_CMNINFO_BOARD_TYPE,                         /*  ODM_BOARD_TYPE_E */
 350        ODM_CMNINFO_PACKAGE_TYPE,
 351        ODM_CMNINFO_EXT_LNA,                                    /*  true */
 352        ODM_CMNINFO_5G_EXT_LNA,
 353        ODM_CMNINFO_EXT_PA,
 354        ODM_CMNINFO_5G_EXT_PA,
 355        ODM_CMNINFO_GPA,
 356        ODM_CMNINFO_APA,
 357        ODM_CMNINFO_GLNA,
 358        ODM_CMNINFO_ALNA,
 359        ODM_CMNINFO_EXT_TRSW,
 360        ODM_CMNINFO_PATCH_ID,                           /* CUSTOMER ID */
 361        ODM_CMNINFO_BINHCT_TEST,
 362        ODM_CMNINFO_BWIFI_TEST,
 363        ODM_CMNINFO_SMART_CONCURRENT,
 364        /* HOOK BEFORE REG INIT----------- */
 365
 366        /*  Dynamic value: */
 367/*  POINTER REFERENCE----------- */
 368        ODM_CMNINFO_MAC_PHY_MODE,       /*  ODM_MAC_PHY_MODE_E */
 369        ODM_CMNINFO_TX_UNI,
 370        ODM_CMNINFO_RX_UNI,
 371        ODM_CMNINFO_WM_MODE,            /*  ODM_WIRELESS_MODE_E */
 372        ODM_CMNINFO_BAND,               /*  ODM_BAND_TYPE_E */
 373        ODM_CMNINFO_SEC_CHNL_OFFSET,    /*  ODM_SEC_CHNL_OFFSET_E */
 374        ODM_CMNINFO_SEC_MODE,           /*  ODM_SECURITY_E */
 375        ODM_CMNINFO_BW,                 /*  ODM_BW_E */
 376        ODM_CMNINFO_CHNL,
 377        ODM_CMNINFO_FORCED_RATE,
 378
 379        ODM_CMNINFO_DMSP_GET_VALUE,
 380        ODM_CMNINFO_BUDDY_ADAPTOR,
 381        ODM_CMNINFO_DMSP_IS_MASTER,
 382        ODM_CMNINFO_SCAN,
 383        ODM_CMNINFO_POWER_SAVING,
 384        ODM_CMNINFO_ONE_PATH_CCA,       /*  ODM_CCA_PATH_E */
 385        ODM_CMNINFO_DRV_STOP,
 386        ODM_CMNINFO_PNP_IN,
 387        ODM_CMNINFO_INIT_ON,
 388        ODM_CMNINFO_ANT_TEST,
 389        ODM_CMNINFO_NET_CLOSED,
 390        ODM_CMNINFO_MP_MODE,
 391        /* ODM_CMNINFO_RTSTA_AID,        For win driver only? */
 392        ODM_CMNINFO_FORCED_IGI_LB,
 393        ODM_CMNINFO_IS1ANTENNA,
 394        ODM_CMNINFO_RFDEFAULTPATH,
 395/*  POINTER REFERENCE----------- */
 396
 397/* CALL BY VALUE------------- */
 398        ODM_CMNINFO_WIFI_DIRECT,
 399        ODM_CMNINFO_WIFI_DISPLAY,
 400        ODM_CMNINFO_LINK_IN_PROGRESS,
 401        ODM_CMNINFO_LINK,
 402        ODM_CMNINFO_STATION_STATE,
 403        ODM_CMNINFO_RSSI_MIN,
 404        ODM_CMNINFO_DBG_COMP,                   /*  u64 */
 405        ODM_CMNINFO_DBG_LEVEL,                  /*  u32 */
 406        ODM_CMNINFO_RA_THRESHOLD_HIGH,          /*  u8 */
 407        ODM_CMNINFO_RA_THRESHOLD_LOW,           /*  u8 */
 408        ODM_CMNINFO_RF_ANTENNA_TYPE,            /*  u8 */
 409        ODM_CMNINFO_BT_ENABLED,
 410        ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
 411        ODM_CMNINFO_BT_HS_RSSI,
 412        ODM_CMNINFO_BT_OPERATION,
 413        ODM_CMNINFO_BT_LIMITED_DIG,             /* Need to Limited Dig or not */
 414        ODM_CMNINFO_BT_DISABLE_EDCA,
 415/* CALL BY VALUE------------- */
 416
 417        /*  Dynamic ptr array hook itms. */
 418        ODM_CMNINFO_STA_STATUS,
 419        ODM_CMNINFO_PHY_STATUS,
 420        ODM_CMNINFO_MAC_STATUS,
 421
 422        ODM_CMNINFO_MAX,
 423} ODM_CMNINFO_E;
 424
 425/*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
 426typedef enum _ODM_Support_Ability_Definition {
 427        /*  */
 428        /*  BB ODM section BIT 0-15 */
 429        /*  */
 430        ODM_BB_DIG                      = BIT0,
 431        ODM_BB_RA_MASK                  = BIT1,
 432        ODM_BB_DYNAMIC_TXPWR            = BIT2,
 433        ODM_BB_FA_CNT                   = BIT3,
 434        ODM_BB_RSSI_MONITOR             = BIT4,
 435        ODM_BB_CCK_PD                   = BIT5,
 436        ODM_BB_ANT_DIV                  = BIT6,
 437        ODM_BB_PWR_SAVE                 = BIT7,
 438        ODM_BB_PWR_TRAIN                = BIT8,
 439        ODM_BB_RATE_ADAPTIVE            = BIT9,
 440        ODM_BB_PATH_DIV                 = BIT10,
 441        ODM_BB_PSD                      = BIT11,
 442        ODM_BB_RXHP                     = BIT12,
 443        ODM_BB_ADAPTIVITY               = BIT13,
 444        ODM_BB_CFO_TRACKING             = BIT14,
 445
 446        /*  MAC DM section BIT 16-23 */
 447        ODM_MAC_EDCA_TURBO              = BIT16,
 448        ODM_MAC_EARLY_MODE              = BIT17,
 449
 450        /*  RF ODM section BIT 24-31 */
 451        ODM_RF_TX_PWR_TRACK             = BIT24,
 452        ODM_RF_RX_GAIN_TRACK    = BIT25,
 453        ODM_RF_CALIBRATION              = BIT26,
 454} ODM_ABILITY_E;
 455
 456/*      ODM_CMNINFO_INTERFACE */
 457typedef enum tag_ODM_Support_Interface_Definition {
 458        ODM_ITRF_SDIO   =       0x4,
 459        ODM_ITRF_ALL    =       0x7,
 460} ODM_INTERFACE_E;
 461
 462/*  ODM_CMNINFO_IC_TYPE */
 463typedef enum tag_ODM_Support_IC_Type_Definition {
 464        ODM_RTL8723B    =       BIT8,
 465} ODM_IC_TYPE_E;
 466
 467/* ODM_CMNINFO_CUT_VER */
 468typedef enum tag_ODM_Cut_Version_Definition {
 469        ODM_CUT_A               =       0,
 470        ODM_CUT_B               =       1,
 471        ODM_CUT_C               =       2,
 472        ODM_CUT_D               =       3,
 473        ODM_CUT_E               =       4,
 474        ODM_CUT_F               =       5,
 475
 476        ODM_CUT_I               =       8,
 477        ODM_CUT_J               =       9,
 478        ODM_CUT_K               =       10,
 479        ODM_CUT_TEST    =       15,
 480} ODM_CUT_VERSION_E;
 481
 482/*  ODM_CMNINFO_FAB_VER */
 483typedef enum tag_ODM_Fab_Version_Definition {
 484        ODM_TSMC        =       0,
 485        ODM_UMC         =       1,
 486} ODM_FAB_E;
 487
 488/*  ODM_CMNINFO_RF_TYPE */
 489/*  */
 490/*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
 491/*  */
 492typedef enum tag_ODM_RF_Path_Bit_Definition {
 493        ODM_RF_TX_A     =       BIT0,
 494        ODM_RF_TX_B     =       BIT1,
 495        ODM_RF_TX_C     =       BIT2,
 496        ODM_RF_TX_D     =       BIT3,
 497        ODM_RF_RX_A     =       BIT4,
 498        ODM_RF_RX_B     =       BIT5,
 499        ODM_RF_RX_C     =       BIT6,
 500        ODM_RF_RX_D     =       BIT7,
 501} ODM_RF_PATH_E;
 502
 503typedef enum tag_ODM_RF_Type_Definition {
 504        ODM_1T1R        =       0,
 505        ODM_1T2R        =       1,
 506        ODM_2T2R        =       2,
 507        ODM_2T3R        =       3,
 508        ODM_2T4R        =       4,
 509        ODM_3T3R        =       5,
 510        ODM_3T4R        =       6,
 511        ODM_4T4R        =       7,
 512} ODM_RF_TYPE_E;
 513
 514/*  */
 515/*  ODM Dynamic common info value definition */
 516/*  */
 517
 518/* typedef enum _MACPHY_MODE_8192D{ */
 519/*      SINGLEMAC_SINGLEPHY, */
 520/*      DUALMAC_DUALPHY, */
 521/*      DUALMAC_SINGLEPHY, */
 522/* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */
 523/*  Above is the original define in MP driver. Please use the same define. THX. */
 524typedef enum tag_ODM_MAC_PHY_Mode_Definition {
 525        ODM_SMSP        = 0,
 526        ODM_DMSP        = 1,
 527        ODM_DMDP        = 2,
 528} ODM_MAC_PHY_MODE_E;
 529
 530typedef enum tag_BT_Coexist_Definition {
 531        ODM_BT_BUSY             = 1,
 532        ODM_BT_ON               = 2,
 533        ODM_BT_OFF              = 3,
 534        ODM_BT_NONE             = 4,
 535} ODM_BT_COEXIST_E;
 536
 537/*  ODM_CMNINFO_OP_MODE */
 538typedef enum tag_Operation_Mode_Definition {
 539        ODM_NO_LINK      = BIT0,
 540        ODM_LINK         = BIT1,
 541        ODM_SCAN         = BIT2,
 542        ODM_POWERSAVE    = BIT3,
 543        ODM_AP_MODE      = BIT4,
 544        ODM_CLIENT_MODE  = BIT5,
 545        ODM_AD_HOC       = BIT6,
 546        ODM_WIFI_DIRECT  = BIT7,
 547        ODM_WIFI_DISPLAY = BIT8,
 548} ODM_OPERATION_MODE_E;
 549
 550/*  ODM_CMNINFO_WM_MODE */
 551typedef enum tag_Wireless_Mode_Definition {
 552        ODM_WM_UNKNOW     = 0x0,
 553        ODM_WM_B          = BIT0,
 554        ODM_WM_G          = BIT1,
 555        ODM_WM_A          = BIT2,
 556        ODM_WM_N24G       = BIT3,
 557        ODM_WM_N5G        = BIT4,
 558        ODM_WM_AUTO       = BIT5,
 559        ODM_WM_AC         = BIT6,
 560} ODM_WIRELESS_MODE_E;
 561
 562/*  ODM_CMNINFO_BAND */
 563typedef enum tag_Band_Type_Definition {
 564        ODM_BAND_2_4G = 0,
 565        ODM_BAND_5G,
 566        ODM_BAND_ON_BOTH,
 567        ODM_BANDMAX
 568} ODM_BAND_TYPE_E;
 569
 570/*  ODM_CMNINFO_SEC_CHNL_OFFSET */
 571typedef enum tag_Secondary_Channel_Offset_Definition {
 572        ODM_DONT_CARE   = 0,
 573        ODM_BELOW               = 1,
 574        ODM_ABOVE               = 2
 575} ODM_SEC_CHNL_OFFSET_E;
 576
 577/*  ODM_CMNINFO_SEC_MODE */
 578typedef enum tag_Security_Definition {
 579        ODM_SEC_OPEN            = 0,
 580        ODM_SEC_WEP40           = 1,
 581        ODM_SEC_TKIP            = 2,
 582        ODM_SEC_RESERVE         = 3,
 583        ODM_SEC_AESCCMP         = 4,
 584        ODM_SEC_WEP104          = 5,
 585        ODM_WEP_WPA_MIXED       = 6, /*  WEP + WPA */
 586        ODM_SEC_SMS4            = 7,
 587} ODM_SECURITY_E;
 588
 589/*  ODM_CMNINFO_BW */
 590typedef enum tag_Bandwidth_Definition {
 591        ODM_BW20M               = 0,
 592        ODM_BW40M               = 1,
 593        ODM_BW80M               = 2,
 594        ODM_BW160M              = 3,
 595        ODM_BW10M               = 4,
 596} ODM_BW_E;
 597
 598/*  ODM_CMNINFO_BOARD_TYPE */
 599/*  For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */
 600/*  For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */
 601typedef enum tag_Board_Definition {
 602        ODM_BOARD_DEFAULT    = 0,      /*  The DEFAULT case. */
 603        ODM_BOARD_MINICARD   = BIT(0), /*  0 = non-mini card, 1 = mini card. */
 604        ODM_BOARD_SLIM       = BIT(1), /*  0 = non-slim card, 1 = slim card */
 605        ODM_BOARD_BT         = BIT(2), /*  0 = without BT card, 1 = with BT */
 606        ODM_BOARD_EXT_PA     = BIT(3), /*  0 = no 2G ext-PA, 1 = existing 2G ext-PA */
 607        ODM_BOARD_EXT_LNA    = BIT(4), /*  0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
 608        ODM_BOARD_EXT_TRSW   = BIT(5), /*  0 = no ext-TRSW, 1 = existing ext-TRSW */
 609        ODM_BOARD_EXT_PA_5G  = BIT(6), /*  0 = no 5G ext-PA, 1 = existing 5G ext-PA */
 610        ODM_BOARD_EXT_LNA_5G = BIT(7), /*  0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
 611} ODM_BOARD_TYPE_E;
 612
 613typedef enum tag_ODM_Package_Definition {
 614        ODM_PACKAGE_DEFAULT      = 0,
 615        ODM_PACKAGE_QFN68        = BIT(0),
 616        ODM_PACKAGE_TFBGA90      = BIT(1),
 617        ODM_PACKAGE_TFBGA79      = BIT(2),
 618} ODM_Package_TYPE_E;
 619
 620typedef enum tag_ODM_TYPE_GPA_Definition {
 621        TYPE_GPA0 = 0,
 622        TYPE_GPA1 = BIT(1)|BIT(0)
 623} ODM_TYPE_GPA_E;
 624
 625typedef enum tag_ODM_TYPE_APA_Definition {
 626        TYPE_APA0 = 0,
 627        TYPE_APA1 = BIT(1)|BIT(0)
 628} ODM_TYPE_APA_E;
 629
 630typedef enum tag_ODM_TYPE_GLNA_Definition {
 631        TYPE_GLNA0 = 0,
 632        TYPE_GLNA1 = BIT(2)|BIT(0),
 633        TYPE_GLNA2 = BIT(3)|BIT(1),
 634        TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
 635} ODM_TYPE_GLNA_E;
 636
 637typedef enum tag_ODM_TYPE_ALNA_Definition {
 638        TYPE_ALNA0 = 0,
 639        TYPE_ALNA1 = BIT(2)|BIT(0),
 640        TYPE_ALNA2 = BIT(3)|BIT(1),
 641        TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
 642} ODM_TYPE_ALNA_E;
 643
 644/*  ODM_CMNINFO_ONE_PATH_CCA */
 645typedef enum tag_CCA_Path {
 646        ODM_CCA_2R                      = 0,
 647        ODM_CCA_1R_A            = 1,
 648        ODM_CCA_1R_B            = 2,
 649} ODM_CCA_PATH_E;
 650
 651typedef struct _ODM_RA_Info_ {
 652        u8 RateID;
 653        u32 RateMask;
 654        u32 RAUseRate;
 655        u8 RateSGI;
 656        u8 RssiStaRA;
 657        u8 PreRssiStaRA;
 658        u8 SGIEnable;
 659        u8 DecisionRate;
 660        u8 PreRate;
 661        u8 HighestRate;
 662        u8 LowestRate;
 663        u32 NscUp;
 664        u32 NscDown;
 665        u16 RTY[5];
 666        u32 TOTAL;
 667        u16 DROP;
 668        u8 Active;
 669        u16 RptTime;
 670        u8 RAWaitingCounter;
 671        u8 RAPendingCounter;
 672        u8 PTActive;  /*  on or off */
 673        u8 PTTryState;  /*  0 trying state, 1 for decision state */
 674        u8 PTStage;  /*  0~6 */
 675        u8 PTStopCount; /* Stop PT counter */
 676        u8 PTPreRate;  /*  if rate change do PT */
 677        u8 PTPreRssi; /*  if RSSI change 5% do PT */
 678        u8 PTModeSS;  /*  decide whitch rate should do PT */
 679        u8 RAstage;  /*  StageRA, decide how many times RA will be done between PT */
 680        u8 PTSmoothFactor;
 681} ODM_RA_INFO_T, *PODM_RA_INFO_T;
 682
 683typedef struct _IQK_MATRIX_REGS_SETTING {
 684        bool bIQKDone;
 685        s32 Value[3][IQK_Matrix_REG_NUM];
 686        bool bBWIqkResultSaved[3];
 687} IQK_MATRIX_REGS_SETTING, *PIQK_MATRIX_REGS_SETTING;
 688
 689/* Remove PATHDIV_PARA struct to odm_PathDiv.h */
 690
 691typedef struct ODM_RF_Calibration_Structure {
 692        /* for tx power tracking */
 693
 694        u32 RegA24; /*  for TempCCK */
 695        s32 RegE94;
 696        s32 RegE9C;
 697        s32 RegEB4;
 698        s32 RegEBC;
 699
 700        u8 TXPowercount;
 701        bool bTXPowerTrackingInit;
 702        bool bTXPowerTracking;
 703        u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
 704        u8 TM_Trigger;
 705        u8 InternalPA5G[2];     /* pathA / pathB */
 706
 707        u8 ThermalMeter[2];    /*  ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
 708        u8 ThermalValue;
 709        u8 ThermalValue_LCK;
 710        u8 ThermalValue_IQK;
 711        u8 ThermalValue_DPK;
 712        u8 ThermalValue_AVG[AVG_THERMAL_NUM];
 713        u8 ThermalValue_AVG_index;
 714        u8 ThermalValue_RxGain;
 715        u8 ThermalValue_Crystal;
 716        u8 ThermalValue_DPKstore;
 717        u8 ThermalValue_DPKtrack;
 718        bool TxPowerTrackingInProgress;
 719
 720        bool bReloadtxpowerindex;
 721        u8 bRfPiEnable;
 722        u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
 723
 724        /*  Tx power Tracking ------------------------- */
 725        u8 bCCKinCH14;
 726        u8 CCK_index;
 727        u8 OFDM_index[MAX_RF_PATH];
 728        s8 PowerIndexOffset[MAX_RF_PATH];
 729        s8 DeltaPowerIndex[MAX_RF_PATH];
 730        s8 DeltaPowerIndexLast[MAX_RF_PATH];
 731        bool bTxPowerChanged;
 732
 733        u8 ThermalValue_HP[HP_THERMAL_NUM];
 734        u8 ThermalValue_HP_index;
 735        IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 736        bool bNeedIQK;
 737        bool bIQKInProgress;
 738        u8 Delta_IQK;
 739        u8 Delta_LCK;
 740        s8 BBSwingDiff2G, BBSwingDiff5G; /*  Unit: dB */
 741        u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
 742        u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
 743        u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
 744        u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
 745        u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
 746        u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
 747        u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
 748        u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
 749        u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
 750        u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
 751        u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
 752        u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
 753        u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
 754        u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
 755
 756        /*  */
 757
 758        /* for IQK */
 759        u32 RegC04;
 760        u32 Reg874;
 761        u32 RegC08;
 762        u32 RegB68;
 763        u32 RegB6C;
 764        u32 Reg870;
 765        u32 Reg860;
 766        u32 Reg864;
 767
 768        bool bIQKInitialized;
 769        bool bLCKInProgress;
 770        bool bAntennaDetected;
 771        u32 ADDA_backup[IQK_ADDA_REG_NUM];
 772        u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
 773        u32 IQK_BB_backup_recover[9];
 774        u32 IQK_BB_backup[IQK_BB_REG_NUM];
 775        u32 TxIQC_8723B[2][3][2]; /*  { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
 776        u32 RxIQC_8723B[2][2][2]; /*  { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
 777
 778        /* for APK */
 779        u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
 780        u8 bAPKdone;
 781        u8 bAPKThermalMeterIgnore;
 782
 783        /*  DPK */
 784        bool bDPKFail;
 785        u8 bDPdone;
 786        u8 bDPPathAOK;
 787        u8 bDPPathBOK;
 788
 789        u32 TxLOK[2];
 790
 791} ODM_RF_CAL_T, *PODM_RF_CAL_T;
 792/*  */
 793/*  ODM Dynamic common info value definition */
 794/*  */
 795
 796typedef struct _FAST_ANTENNA_TRAINNING_ {
 797        u8 Bssid[6];
 798        u8 antsel_rx_keep_0;
 799        u8 antsel_rx_keep_1;
 800        u8 antsel_rx_keep_2;
 801        u8 antsel_rx_keep_3;
 802        u32 antSumRSSI[7];
 803        u32 antRSSIcnt[7];
 804        u32 antAveRSSI[7];
 805        u8 FAT_State;
 806        u32 TrainIdx;
 807        u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 808        u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 809        u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 810        u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 811        u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 812        u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 813        u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 814        u8 RxIdleAnt;
 815        bool    bBecomeLinked;
 816        u32 MinMaxRSSI;
 817        u8 idx_AntDiv_counter_2G;
 818        u8 idx_AntDiv_counter_5G;
 819        u32 AntDiv_2G_5G;
 820        u32 CCK_counter_main;
 821        u32 CCK_counter_aux;
 822        u32 OFDM_counter_main;
 823        u32 OFDM_counter_aux;
 824
 825        u32 CCK_CtrlFrame_Cnt_main;
 826        u32 CCK_CtrlFrame_Cnt_aux;
 827        u32 OFDM_CtrlFrame_Cnt_main;
 828        u32 OFDM_CtrlFrame_Cnt_aux;
 829        u32 MainAnt_CtrlFrame_Sum;
 830        u32 AuxAnt_CtrlFrame_Sum;
 831        u32 MainAnt_CtrlFrame_Cnt;
 832        u32 AuxAnt_CtrlFrame_Cnt;
 833
 834} FAT_T, *pFAT_T;
 835
 836typedef enum _FAT_STATE {
 837        FAT_NORMAL_STATE                        = 0,
 838        FAT_TRAINING_STATE              = 1,
 839} FAT_STATE_E, *PFAT_STATE_E;
 840
 841typedef enum _ANT_DIV_TYPE {
 842        NO_ANTDIV                       = 0xFF,
 843        CG_TRX_HW_ANTDIV                = 0x01,
 844        CGCS_RX_HW_ANTDIV       = 0x02,
 845        FIXED_HW_ANTDIV         = 0x03,
 846        CG_TRX_SMART_ANTDIV     = 0x04,
 847        CGCS_RX_SW_ANTDIV       = 0x05,
 848        S0S1_SW_ANTDIV          = 0x06 /* 8723B intrnal switch S0 S1 */
 849} ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
 850
 851typedef struct _ODM_PATH_DIVERSITY_ {
 852        u8 RespTxPath;
 853        u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM];
 854        u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 855        u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 856        u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 857        u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 858} PATHDIV_T, *pPATHDIV_T;
 859
 860typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
 861        PHY_REG_PG_RELATIVE_VALUE = 0,
 862        PHY_REG_PG_EXACT_VALUE = 1
 863} PHY_REG_PG_TYPE;
 864
 865/*  */
 866/*  Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */
 867/*  */
 868typedef struct _ANT_DETECTED_INFO {
 869        bool bAntDetected;
 870        u32 dBForAntA;
 871        u32 dBForAntB;
 872        u32 dBForAntO;
 873} ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
 874
 875/*  */
 876/*  2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
 877/*  */
 878typedef  struct DM_Out_Source_Dynamic_Mechanism_Structure {
 879        /* RT_TIMER     FastAntTrainingTimer; */
 880        /*  */
 881        /*      Add for different team use temporarily */
 882        /*  */
 883        struct adapter *Adapter;                /*  For CE/NIC team */
 884        /*  WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */
 885        bool odm_ready;
 886
 887        PHY_REG_PG_TYPE PhyRegPgValueType;
 888        u8 PhyRegPgVersion;
 889
 890        u64     DebugComponents;
 891        u32 DebugLevel;
 892
 893        u32 NumQryPhyStatusAll; /* CCK + OFDM */
 894        u32 LastNumQryPhyStatusAll;
 895        u32 RxPWDBAve;
 896        bool MPDIG_2G;          /* off MPDIG */
 897        u8 Times_2G;
 898
 899/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 900        bool bCckHighPower;
 901        u8 RFPathRxEnable;              /*  ODM_CMNINFO_RFPATH_ENABLE */
 902        u8 ControlChannel;
 903/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 904
 905/* REMOVED COMMON INFO---------- */
 906        /* u8           PseudoMacPhyMode; */
 907        /* bool                 *BTCoexist; */
 908        /* bool                 PseudoBtCoexist; */
 909        /* u8           OPMode; */
 910        /* bool                 bAPMode; */
 911        /* bool                 bClientMode; */
 912        /* bool                 bAdHocMode; */
 913        /* bool                 bSlaveOfDMSP; */
 914/* REMOVED COMMON INFO---------- */
 915
 916/* 1  COMMON INFORMATION */
 917
 918        /*  */
 919        /*  Init Value */
 920        /*  */
 921/* HOOK BEFORE REG INIT----------- */
 922        /*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
 923        u8 SupportPlatform;
 924        /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ?K?K = 1/2/3/?K */
 925        u32 SupportAbility;
 926        /*  ODM PCIE/USB/SDIO = 1/2/3 */
 927        u8 SupportInterface;
 928        /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
 929        u32 SupportICType;
 930        /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
 931        u8 CutVersion;
 932        /*  Fab Version TSMC/UMC = 0/1 */
 933        u8 FabVersion;
 934        /*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
 935        u8 RFType;
 936        u8 RFEType;
 937        /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
 938        u8 BoardType;
 939        u8 PackageType;
 940        u8 TypeGLNA;
 941        u8 TypeGPA;
 942        u8 TypeALNA;
 943        u8 TypeAPA;
 944        /*  with external LNA  NO/Yes = 0/1 */
 945        u8 ExtLNA;
 946        u8 ExtLNA5G;
 947        /*  with external PA  NO/Yes = 0/1 */
 948        u8 ExtPA;
 949        u8 ExtPA5G;
 950        /*  with external TRSW  NO/Yes = 0/1 */
 951        u8 ExtTRSW;
 952        u8 PatchID; /* Customer ID */
 953        bool bInHctTest;
 954        bool bWIFITest;
 955
 956        bool bDualMacSmartConcurrent;
 957        u32 BK_SupportAbility;
 958        u8 AntDivType;
 959/* HOOK BEFORE REG INIT----------- */
 960
 961        /*  */
 962        /*  Dynamic Value */
 963        /*  */
 964/*  POINTER REFERENCE----------- */
 965
 966        u8 u8_temp;
 967        bool bool_temp;
 968        struct adapter *adapter_temp;
 969
 970        /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
 971        u8 *pMacPhyMode;
 972        /* TX Unicast byte count */
 973        u64 *pNumTxBytesUnicast;
 974        /* RX Unicast byte count */
 975        u64 *pNumRxBytesUnicast;
 976        /*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
 977        u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */
 978        /*  Frequence band 2.4G/5G = 0/1 */
 979        u8 *pBandType;
 980        /*  Secondary channel offset don't_care/below/above = 0/1/2 */
 981        u8 *pSecChOffset;
 982        /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
 983        u8 *pSecurity;
 984        /*  BW info 20M/40M/80M = 0/1/2 */
 985        u8 *pBandWidth;
 986        /*  Central channel location Ch1/Ch2/.... */
 987        u8 *pChannel; /* central channel number */
 988        bool DPK_Done;
 989        /*  Common info for 92D DMSP */
 990
 991        bool *pbGetValueFromOtherMac;
 992        struct adapter **pBuddyAdapter;
 993        bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
 994        /*  Common info for Status */
 995        bool *pbScanInProcess;
 996        bool *pbPowerSaving;
 997        /*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
 998        u8 *pOnePathCCA;
 999        /* pMgntInfo->AntennaTest */
1000        u8 *pAntennaTest;

1001        bool *pbNet_closed;
1002        u8 *mp_mode;
1003        /* u8   *pAidMap; */
1004        u8 *pu1ForcedIgiLb;
1005/*  For 8723B IQK----------- */
1006        bool *pIs1Antenna;
1007        u8 *pRFDefaultPath;
1008        /*  0:S1, 1:S0 */
1009
1010/*  POINTER REFERENCE----------- */
1011        u16 *pForcedDataRate;
1012/* CALL BY VALUE------------- */
1013        bool bLinkInProcess;
1014        bool bWIFI_Direct;
1015        bool bWIFI_Display;
1016        bool bLinked;
1017
1018        bool bsta_state;
1019        u8 RSSI_Min;
1020        u8 InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
1021        bool bIsMPChip;
1022        bool bOneEntryOnly;
1023        /*  Common info for BTDM */
1024        bool bBtEnabled;                        /*  BT is disabled */
1025        bool bBtConnectProcess; /*  BT HS is under connection progress. */
1026        u8 btHsRssi;                            /*  BT HS mode wifi rssi value. */
1027        bool bBtHsOperation;            /*  BT HS mode is under progress */
1028        bool bBtDisableEdcaTurbo;       /*  Under some condition, don't enable the EDCA Turbo */
1029        bool bBtLimitedDig;                     /*  BT is busy. */
1030/* CALL BY VALUE------------- */
1031        u8 RSSI_A;
1032        u8 RSSI_B;
1033        u64 RSSI_TRSW;
1034        u64 RSSI_TRSW_H;
1035        u64 RSSI_TRSW_L;
1036        u64 RSSI_TRSW_iso;
1037
1038        u8 RxRate;
1039        bool bNoisyState;
1040        u8 TxRate;
1041        u8 LinkedInterval;
1042        u8 preChannel;
1043        u32 TxagcOffsetValueA;
1044        bool IsTxagcOffsetPositiveA;
1045        u32 TxagcOffsetValueB;
1046        bool IsTxagcOffsetPositiveB;
1047        u64     lastTxOkCnt;
1048        u64     lastRxOkCnt;
1049        u32 BbSwingOffsetA;
1050        bool IsBbSwingOffsetPositiveA;
1051        u32 BbSwingOffsetB;
1052        bool IsBbSwingOffsetPositiveB;
1053        s8 TH_L2H_ini;
1054        s8 TH_EDCCA_HL_diff;
1055        s8 IGI_Base;
1056        u8 IGI_target;
1057        bool ForceEDCCA;
1058        u8 AdapEn_RSSI;
1059        s8 Force_TH_H;
1060        s8 Force_TH_L;
1061        u8 IGI_LowerBound;
1062        u8 antdiv_rssi;
1063        u8 AntType;
1064        u8 pre_AntType;
1065        u8 antdiv_period;
1066        u8 antdiv_select;
1067        u8 NdpaPeriod;
1068        bool H2C_RARpt_connect;
1069
1070        /*  add by Yu Cehn for adaptivtiy */
1071        bool adaptivity_flag;
1072        bool NHM_disable;
1073        bool TxHangFlg;
1074        bool Carrier_Sense_enable;
1075        u8 tolerance_cnt;
1076        u64 NHMCurTxOkcnt;
1077        u64 NHMCurRxOkcnt;
1078        u64 NHMLastTxOkcnt;
1079        u64 NHMLastRxOkcnt;
1080        u8 txEdcca1;
1081        u8 txEdcca0;
1082        s8 H2L_lb;
1083        s8 L2H_lb;
1084        u8 Adaptivity_IGI_upper;
1085        u8 NHM_cnt_0;
1086
1087        ODM_NOISE_MONITOR noise_level;/* ODM_MAX_CHANNEL_NUM]; */
1088        /*  */
1089        /* 2 Define STA info. */
1090        /*  _ODM_STA_INFO */
1091        /*  2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
1092        PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
1093
1094        /*  */
1095        /*  2012/02/14 MH Add to share 88E ra with other SW team. */
1096        /*  We need to colelct all support abilit to a proper area. */
1097        /*  */
1098        bool RaSupport88E;
1099
1100        /*  Define ........... */
1101
1102        /*  Latest packet phy info (ODM write) */
1103        ODM_PHY_DBG_INFO_T PhyDbgInfo;
1104        /* PHY_INFO_88E         PhyInfo; */
1105
1106        /*  Latest packet phy info (ODM write) */
1107        ODM_MAC_INFO *pMacInfo;
1108        /* MAC_INFO_88E         MacInfo; */
1109
1110        /*  Different Team independt structure?? */
1111
1112        /*  */
1113        /* TX_RTP_CMN           TX_retrpo; */
1114        /* TX_RTP_88E           TX_retrpo; */
1115        /* TX_RTP_8195          TX_retrpo; */
1116
1117        /*  */
1118        /* ODM Structure */
1119        /*  */
1120        FAT_T DM_FatTable;
1121        DIG_T DM_DigTable;
1122        PS_T DM_PSTable;
1123        Pri_CCA_T DM_PriCCA;
1124        RXHP_T DM_RXHP_Table;
1125        RA_T DM_RA_Table;
1126        false_ALARM_STATISTICS FalseAlmCnt;
1127        false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
1128        SWAT_T DM_SWAT_Table;
1129        bool RSSI_test;
1130        CFO_TRACKING DM_CfoTrack;
1131
1132        EDCA_T DM_EDCA_Table;
1133        u32 WMMEDCA_BE;
1134        PATHDIV_T DM_PathDiv;
1135        /*  Copy from SD4 structure */
1136        /*  */
1137        /*  ================================================== */
1138        /*  */
1139
1140        /* common */
1141        /* u8 DM_Type; */
1142        /* u8    PSD_Report_RXHP[80];    Add By Gary */
1143        /* u8    PSD_func_flag;                Add By Gary */
1144        /* for DIG */
1145        /* u8 bDMInitialGainEnable; */
1146        /* u8 binitialized;  for dm_initial_gain_Multi_STA use. */
1147        /* for Antenna diversity */
1148        /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */
1149        /* PSTA_INFO_T RSSI_target; */
1150
1151        bool *pbDriverStopped;
1152        bool *pbDriverIsGoingToPnpSetPowerSleep;
1153        bool *pinit_adpt_in_progress;
1154
1155        /* PSD */
1156        bool bUserAssignLevel;
1157        RT_TIMER PSDTimer;
1158        u8 RSSI_BT;                     /* come from BT */
1159        bool bPSDinProcess;
1160        bool bPSDactive;
1161        bool bDMInitialGainEnable;
1162
1163        /* MPT DIG */
1164        RT_TIMER MPT_DIGTimer;
1165
1166        /* for rate adaptive, in fact,  88c/92c fw will handle this */
1167        u8 bUseRAMask;
1168
1169        ODM_RATE_ADAPTIVE RateAdaptive;
1170
1171        ANT_DETECTED_INFO AntDetectedInfo; /*  Antenna detected information for RSSI tool */
1172
1173        ODM_RF_CAL_T RFCalibrateInfo;
1174
1175        /*  */
1176        /*  TX power tracking */
1177        /*  */
1178        u8 BbSwingIdxOfdm[MAX_RF_PATH];
1179        u8 BbSwingIdxOfdmCurrent;
1180        u8 BbSwingIdxOfdmBase[MAX_RF_PATH];
1181        bool BbSwingFlagOfdm;
1182        u8 BbSwingIdxCck;
1183        u8 BbSwingIdxCckCurrent;
1184        u8 BbSwingIdxCckBase;
1185        u8 DefaultOfdmIndex;
1186        u8 DefaultCckIndex;
1187        bool BbSwingFlagCck;
1188
1189        s8 Absolute_OFDMSwingIdx[MAX_RF_PATH];
1190        s8 Remnant_OFDMSwingIdx[MAX_RF_PATH];
1191        s8 Remnant_CCKSwingIdx;
1192        s8 Modify_TxAGC_Value;       /* Remnat compensate value at TxAGC */
1193        bool Modify_TxAGC_Flag_PathA;
1194        bool Modify_TxAGC_Flag_PathB;
1195        bool Modify_TxAGC_Flag_PathC;
1196        bool Modify_TxAGC_Flag_PathD;
1197        bool Modify_TxAGC_Flag_PathA_CCK;
1198
1199        s8 KfreeOffset[MAX_RF_PATH];
1200        /*  */
1201        /*  ODM system resource. */
1202        /*  */
1203
1204        /*  ODM relative time. */
1205        RT_TIMER PathDivSwitchTimer;
1206        /* 2011.09.27 add for Path Diversity */
1207        RT_TIMER CCKPathDiversityTimer;
1208        RT_TIMER FastAntTrainingTimer;
1209
1210        /*  ODM relative workitem. */
1211
1212        #if (BEAMFORMING_SUPPORT == 1)
1213        RT_BEAMFORMING_INFO BeamformingInfo;
1214        #endif
1215} DM_ODM_T, *PDM_ODM_T; /*  DM_Dynamic_Mechanism_Structure */
1216
1217#define ODM_RF_PATH_MAX 2
1218
1219typedef enum _ODM_RF_RADIO_PATH {
1220        ODM_RF_PATH_A = 0,   /* Radio Path A */
1221        ODM_RF_PATH_B = 1,   /* Radio Path B */
1222        ODM_RF_PATH_C = 2,   /* Radio Path C */
1223        ODM_RF_PATH_D = 3,   /* Radio Path D */
1224        ODM_RF_PATH_AB,
1225        ODM_RF_PATH_AC,
1226        ODM_RF_PATH_AD,
1227        ODM_RF_PATH_BC,
1228        ODM_RF_PATH_BD,
1229        ODM_RF_PATH_CD,
1230        ODM_RF_PATH_ABC,
1231        ODM_RF_PATH_ACD,
1232        ODM_RF_PATH_BCD,
1233        ODM_RF_PATH_ABCD,
1234        /*   ODM_RF_PATH_MAX,    Max RF number 90 support */
1235} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
1236
1237 typedef enum _ODM_RF_CONTENT {
1238        odm_radioa_txt = 0x1000,
1239        odm_radiob_txt = 0x1001,
1240        odm_radioc_txt = 0x1002,
1241        odm_radiod_txt = 0x1003
1242} ODM_RF_CONTENT;
1243
1244typedef enum _ODM_BB_Config_Type {
1245        CONFIG_BB_PHY_REG,
1246        CONFIG_BB_AGC_TAB,
1247        CONFIG_BB_AGC_TAB_2G,
1248        CONFIG_BB_AGC_TAB_5G,
1249        CONFIG_BB_PHY_REG_PG,
1250        CONFIG_BB_PHY_REG_MP,
1251        CONFIG_BB_AGC_TAB_DIFF,
1252} ODM_BB_Config_Type, *PODM_BB_Config_Type;
1253
1254typedef enum _ODM_RF_Config_Type {
1255        CONFIG_RF_RADIO,
1256        CONFIG_RF_TXPWR_LMT,
1257} ODM_RF_Config_Type, *PODM_RF_Config_Type;
1258
1259typedef enum _ODM_FW_Config_Type {
1260        CONFIG_FW_NIC,
1261        CONFIG_FW_NIC_2,
1262        CONFIG_FW_AP,
1263        CONFIG_FW_WoWLAN,
1264        CONFIG_FW_WoWLAN_2,
1265        CONFIG_FW_AP_WoWLAN,
1266        CONFIG_FW_BT,
1267} ODM_FW_Config_Type;
1268
1269/*  Status code */
1270typedef enum _RT_STATUS {
1271        RT_STATUS_SUCCESS,
1272        RT_STATUS_FAILURE,
1273        RT_STATUS_PENDING,
1274        RT_STATUS_RESOURCE,
1275        RT_STATUS_INVALID_CONTEXT,
1276        RT_STATUS_INVALID_PARAMETER,
1277        RT_STATUS_NOT_SUPPORT,
1278        RT_STATUS_OS_API_FAILED,
1279} RT_STATUS, *PRT_STATUS;
1280
1281#ifdef REMOVE_PACK
1282#pragma pack()
1283#endif
1284
1285/* include "odm_function.h" */
1286
1287/* 3 =========================================================== */
1288/* 3 DIG */
1289/* 3 =========================================================== */
1290
1291/* Remove DIG by Yuchen */
1292
1293/* 3 =========================================================== */
1294/* 3 AGC RX High Power Mode */
1295/* 3 =========================================================== */
1296#define          LNA_Low_Gain_1                      0x64
1297#define          LNA_Low_Gain_2                      0x5A
1298#define          LNA_Low_Gain_3                      0x58
1299
1300#define          FA_RXHP_TH1                           5000
1301#define          FA_RXHP_TH2                           1500
1302#define          FA_RXHP_TH3                             800
1303#define          FA_RXHP_TH4                             600
1304#define          FA_RXHP_TH5                             500
1305
1306/* 3 =========================================================== */
1307/* 3 EDCA */
1308/* 3 =========================================================== */
1309
1310/* 3 =========================================================== */
1311/* 3 Dynamic Tx Power */
1312/* 3 =========================================================== */
1313/* Dynamic Tx Power Control Threshold */
1314
1315/* 3 =========================================================== */
1316/* 3 Rate Adaptive */
1317/* 3 =========================================================== */
1318#define         DM_RATR_STA_INIT                        0
1319#define         DM_RATR_STA_HIGH                        1
1320#define         DM_RATR_STA_MIDDLE                      2
1321#define         DM_RATR_STA_LOW                         3
1322
1323/* 3 =========================================================== */
1324/* 3 BB Power Save */
1325/* 3 =========================================================== */
1326
1327typedef enum tag_1R_CCA_Type_Definition {
1328        CCA_1R = 0,
1329        CCA_2R = 1,
1330        CCA_MAX = 2,
1331} DM_1R_CCA_E;
1332
1333typedef enum tag_RF_Type_Definition {
1334        RF_Save = 0,
1335        RF_Normal = 1,
1336        RF_MAX = 2,
1337} DM_RF_E;
1338
1339/* 3 =========================================================== */
1340/* 3 Antenna Diversity */
1341/* 3 =========================================================== */
1342typedef enum tag_SW_Antenna_Switch_Definition {
1343        Antenna_A = 1,
1344        Antenna_B = 2,
1345        Antenna_MAX = 3,
1346} DM_SWAS_E;
1347
1348/*  Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1349#define MAX_ANTENNA_DETECTION_CNT       10
1350
1351/*  */
1352/*  Extern Global Variables. */
1353/*  */
1354extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE];
1355extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1356extern  u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1357
1358extern  u32 OFDMSwingTable_New[OFDM_TABLE_SIZE];
1359extern  u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
1360extern  u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8];
1361
1362extern  u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
1363
1364/*  */
1365/*  check Sta pointer valid or not */
1366/*  */
1367#define IS_STA_VALID(pSta)              (pSta)
1368/*  20100514 Joseph: Add definition for antenna switching test after link. */
1369/*  This indicates two different the steps. */
1370/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1371/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1372/*  with original RSSI to determine if it is necessary to switch antenna. */
1373#define SWAW_STEP_PEAK          0
1374#define SWAW_STEP_DETERMINE     1
1375
1376/* Remove DIG by yuchen */
1377
1378void ODM_SetAntenna(PDM_ODM_T pDM_Odm, u8 Antenna);
1379
1380/* Remove BB power saving by Yuchen */
1381
1382#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1383void ODM_TXPowerTrackingCheck(PDM_ODM_T pDM_Odm);
1384
1385bool ODM_RAStateCheck(
1386        PDM_ODM_T pDM_Odm,
1387        s32     RSSI,
1388        bool bForceUpdate,
1389        u8 *pRATRState
1390);
1391
1392#define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi
1393void ODM_SwAntDivChkPerPktRssi(
1394        PDM_ODM_T pDM_Odm,
1395        u8 StationID,
1396        struct odm_phy_info *pPhyInfo
1397);
1398
1399u32 ODM_Get_Rate_Bitmap(
1400        PDM_ODM_T pDM_Odm,
1401        u32 macid,
1402        u32 ra_mask,
1403        u8 rssi_level
1404);
1405
1406#if (BEAMFORMING_SUPPORT == 1)
1407BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId);
1408#endif
1409
1410void odm_TXPowerTrackingInit(PDM_ODM_T pDM_Odm);
1411
1412void ODM_DMInit(PDM_ODM_T pDM_Odm);
1413
1414void ODM_DMWatchdog(PDM_ODM_T pDM_Odm); /*  For common use in the future */
1415
1416void ODM_CmnInfoInit(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, u32 Value);
1417
1418void ODM_CmnInfoHook(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, void *pValue);
1419
1420void ODM_CmnInfoPtrArrayHook(
1421        PDM_ODM_T pDM_Odm,
1422        ODM_CMNINFO_E CmnInfo,
1423        u16 Index,
1424        void *pValue
1425);
1426
1427void ODM_CmnInfoUpdate(PDM_ODM_T pDM_Odm, u32 CmnInfo, u64 Value);
1428
1429void ODM_InitAllTimers(PDM_ODM_T pDM_Odm);
1430
1431void ODM_CancelAllTimers(PDM_ODM_T pDM_Odm);
1432
1433void ODM_ReleaseAllTimers(PDM_ODM_T pDM_Odm);
1434
1435void ODM_AntselStatistics_88C(
1436        PDM_ODM_T pDM_Odm,
1437        u8 MacId,
1438        u32 PWDBAll,
1439        bool isCCKrate
1440);
1441
1442void ODM_DynamicARFBSelect(PDM_ODM_T pDM_Odm, u8 rate, bool Collision_State);
1443
1444#endif
1445