1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15/* File Name: odm_reg.h */ 16/* Description: */ 17/* This file is for general register definition. */ 18#ifndef __HAL_ODM_REG_H__ 19#define __HAL_ODM_REG_H__ 20 21/* Register Definition */ 22 23/* MAC REG */ 24#define ODM_BB_RESET 0x002 25#define ODM_DUMMY 0x4fe 26#define RF_T_METER_OLD 0x24 27#define RF_T_METER_NEW 0x42 28 29#define ODM_EDCA_VO_PARAM 0x500 30#define ODM_EDCA_VI_PARAM 0x504 31#define ODM_EDCA_BE_PARAM 0x508 32#define ODM_EDCA_BK_PARAM 0x50C 33#define ODM_TXPAUSE 0x522 34 35/* BB REG */ 36#define ODM_FPGA_PHY0_PAGE8 0x800 37#define ODM_PSD_SETTING 0x808 38#define ODM_AFE_SETTING 0x818 39#define ODM_TXAGC_B_24_54 0x834 40#define ODM_TXAGC_B_MCS32_5 0x838 41#define ODM_TXAGC_B_MCS0_MCS3 0x83c 42#define ODM_TXAGC_B_MCS4_MCS7 0x848 43#define ODM_TXAGC_B_MCS8_MCS11 0x84c 44#define ODM_ANALOG_REGISTER 0x85c 45#define ODM_RF_INTERFACE_OUTPUT 0x860 46#define ODM_TXAGC_B_MCS12_MCS15 0x868 47#define ODM_TXAGC_B_11_A_2_11 0x86c 48#define ODM_AD_DA_LSB_MASK 0x874 49#define ODM_ENABLE_3_WIRE 0x88c 50#define ODM_PSD_REPORT 0x8b4 51#define ODM_R_ANT_SELECT 0x90c 52#define ODM_CCK_ANT_SELECT 0xa07 53#define ODM_CCK_PD_THRESH 0xa0a 54#define ODM_CCK_RF_REG1 0xa11 55#define ODM_CCK_MATCH_FILTER 0xa20 56#define ODM_CCK_RAKE_MAC 0xa2e 57#define ODM_CCK_CNT_RESET 0xa2d 58#define ODM_CCK_TX_DIVERSITY 0xa2f 59#define ODM_CCK_FA_CNT_MSB 0xa5b 60#define ODM_CCK_FA_CNT_LSB 0xa5c 61#define ODM_CCK_NEW_FUNCTION 0xa75 62#define ODM_OFDM_PHY0_PAGE_C 0xc00 63#define ODM_OFDM_RX_ANT 0xc04 64#define ODM_R_A_RXIQI 0xc14 65#define ODM_R_A_AGC_CORE1 0xc50 66#define ODM_R_A_AGC_CORE2 0xc54 67#define ODM_R_B_AGC_CORE1 0xc58 68#define ODM_R_AGC_PAR 0xc70 69#define ODM_R_HTSTF_AGC_PAR 0xc7c 70#define ODM_TX_PWR_TRAINING_A 0xc90 71#define ODM_TX_PWR_TRAINING_B 0xc98 72#define ODM_OFDM_FA_CNT1 0xcf0 73#define ODM_OFDM_PHY0_PAGE_D 0xd00 74#define ODM_OFDM_FA_CNT2 0xda0 75#define ODM_OFDM_FA_CNT3 0xda4 76#define ODM_OFDM_FA_CNT4 0xda8 77#define ODM_TXAGC_A_6_18 0xe00 78#define ODM_TXAGC_A_24_54 0xe04 79#define ODM_TXAGC_A_1_MCS32 0xe08 80#define ODM_TXAGC_A_MCS0_MCS3 0xe10 81#define ODM_TXAGC_A_MCS4_MCS7 0xe14 82#define ODM_TXAGC_A_MCS8_MCS11 0xe18 83#define ODM_TXAGC_A_MCS12_MCS15 0xe1c 84 85/* RF REG */ 86#define ODM_GAIN_SETTING 0x00 87#define ODM_CHANNEL 0x18 88 89/* Ant Detect Reg */ 90#define ODM_DPDT 0x300 91 92/* PSD Init */ 93#define ODM_PSDREG 0x808 94 95/* 92D Path Div */ 96#define PATHDIV_REG 0xB30 97#define PATHDIV_TRI 0xBA0 98 99/* Bitmap Definition */ 100 101#define BIT_FA_RESET BIT0 102 103#endif 104