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14
15#define _HAL_INIT_C_
16
17#include <linux/firmware.h>
18#include <linux/slab.h>
19#include <drv_types.h>
20#include <rtw_debug.h>
21#include <rtl8723b_hal.h>
22#include "hal_com_h2c.h"
23
24static void _FWDownloadEnable(struct adapter *padapter, bool enable)
25{
26 u8 tmp, count = 0;
27
28 if (enable) {
29
30 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
31 rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04);
32
33 tmp = rtw_read8(padapter, REG_MCUFWDL);
34 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
35
36 do {
37 tmp = rtw_read8(padapter, REG_MCUFWDL);
38 if (tmp & 0x01)
39 break;
40 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
41 msleep(1);
42 } while (count++ < 100);
43
44 if (count > 0)
45 DBG_871X("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count);
46
47
48 tmp = rtw_read8(padapter, REG_MCUFWDL+2);
49 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
50 } else {
51
52 tmp = rtw_read8(padapter, REG_MCUFWDL);
53 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
54 }
55}
56
57static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)
58{
59 int ret = _SUCCESS;
60
61 u32 blockSize_p1 = 4;
62 u32 blockSize_p2 = 8;
63 u32 blockSize_p3 = 1;
64 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
65 u32 remainSize_p1 = 0, remainSize_p2 = 0;
66 u8 *bufferPtr = buffer;
67 u32 i = 0, offset = 0;
68
69
70
71
72 blockCount_p1 = buffSize / blockSize_p1;
73 remainSize_p1 = buffSize % blockSize_p1;
74
75 if (blockCount_p1) {
76 RT_TRACE(
77 _module_hal_init_c_,
78 _drv_notice_,
79 (
80 "_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n",
81 buffSize,
82 blockSize_p1,
83 blockCount_p1,
84 remainSize_p1
85 )
86 );
87 }
88
89 for (i = 0; i < blockCount_p1; i++) {
90 ret = rtw_write32(padapter, (FW_8723B_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1)));
91 if (ret == _FAIL) {
92 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
93 goto exit;
94 }
95 }
96
97
98 if (remainSize_p1) {
99 offset = blockCount_p1 * blockSize_p1;
100
101 blockCount_p2 = remainSize_p1/blockSize_p2;
102 remainSize_p2 = remainSize_p1%blockSize_p2;
103
104 if (blockCount_p2) {
105 RT_TRACE(
106 _module_hal_init_c_,
107 _drv_notice_,
108 (
109 "_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n",
110 (buffSize-offset),
111 blockSize_p2,
112 blockCount_p2,
113 remainSize_p2
114 )
115 );
116 }
117
118 }
119
120
121 if (remainSize_p2) {
122 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
123
124 blockCount_p3 = remainSize_p2 / blockSize_p3;
125
126 RT_TRACE(_module_hal_init_c_, _drv_notice_,
127 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
128 (buffSize-offset), blockSize_p3, blockCount_p3));
129
130 for (i = 0; i < blockCount_p3; i++) {
131 ret = rtw_write8(padapter, (FW_8723B_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
132
133 if (ret == _FAIL) {
134 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
135 goto exit;
136 }
137 }
138 }
139exit:
140 return ret;
141}
142
143static int _PageWrite(
144 struct adapter *padapter,
145 u32 page,
146 void *buffer,
147 u32 size
148)
149{
150 u8 value8;
151 u8 u8Page = (u8) (page & 0x07);
152
153 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page;
154 rtw_write8(padapter, REG_MCUFWDL+2, value8);
155
156 return _BlockWrite(padapter, buffer, size);
157}
158
159static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)
160{
161
162
163 int ret = _SUCCESS;
164 u32 pageNums, remainSize;
165 u32 page, offset;
166 u8 *bufferPtr = buffer;
167
168 pageNums = size / MAX_DLFW_PAGE_SIZE;
169
170 remainSize = size % MAX_DLFW_PAGE_SIZE;
171
172 for (page = 0; page < pageNums; page++) {
173 offset = page * MAX_DLFW_PAGE_SIZE;
174 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE);
175
176 if (ret == _FAIL) {
177 printk("====>%s %d\n", __func__, __LINE__);
178 goto exit;
179 }
180 }
181
182 if (remainSize) {
183 offset = pageNums * MAX_DLFW_PAGE_SIZE;
184 page = pageNums;
185 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
186
187 if (ret == _FAIL) {
188 printk("====>%s %d\n", __func__, __LINE__);
189 goto exit;
190 }
191 }
192 RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n"));
193
194exit:
195 return ret;
196}
197
198void _8051Reset8723(struct adapter *padapter)
199{
200 u8 cpu_rst;
201 u8 io_rst;
202
203
204
205
206
207 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
208 io_rst &= ~BIT(0);
209 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
210
211 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
212 cpu_rst &= ~BIT(2);
213 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
214
215
216
217 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
218 io_rst |= BIT(0);
219 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
220
221 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
222 cpu_rst |= BIT(2);
223 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
224
225 DBG_8192C("%s: Finish\n", __func__);
226}
227
228u8 g_fwdl_chksum_fail = 0;
229
230static s32 polling_fwdl_chksum(
231 struct adapter *adapter, u32 min_cnt, u32 timeout_ms
232)
233{
234 s32 ret = _FAIL;
235 u32 value32;
236 unsigned long start = jiffies;
237 u32 cnt = 0;
238
239
240 do {
241 cnt++;
242 value32 = rtw_read32(adapter, REG_MCUFWDL);
243 if (value32 & FWDL_ChkSum_rpt || adapter->bSurpriseRemoved || adapter->bDriverStopped)
244 break;
245 yield();
246 } while (jiffies_to_msecs(jiffies-start) < timeout_ms || cnt < min_cnt);
247
248 if (!(value32 & FWDL_ChkSum_rpt)) {
249 goto exit;
250 }
251
252 if (g_fwdl_chksum_fail) {
253 DBG_871X("%s: fwdl test case: fwdl_chksum_fail\n", __func__);
254 g_fwdl_chksum_fail--;
255 goto exit;
256 }
257
258 ret = _SUCCESS;
259
260exit:
261 DBG_871X(
262 "%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n",
263 __func__,
264 (ret == _SUCCESS) ? "OK" : "Fail",
265 cnt,
266 jiffies_to_msecs(jiffies-start),
267 value32
268 );
269
270 return ret;
271}
272
273u8 g_fwdl_wintint_rdy_fail = 0;
274
275static s32 _FWFreeToGo(struct adapter *adapter, u32 min_cnt, u32 timeout_ms)
276{
277 s32 ret = _FAIL;
278 u32 value32;
279 unsigned long start = jiffies;
280 u32 cnt = 0;
281
282 value32 = rtw_read32(adapter, REG_MCUFWDL);
283 value32 |= MCUFWDL_RDY;
284 value32 &= ~WINTINI_RDY;
285 rtw_write32(adapter, REG_MCUFWDL, value32);
286
287 _8051Reset8723(adapter);
288
289
290 do {
291 cnt++;
292 value32 = rtw_read32(adapter, REG_MCUFWDL);
293 if (value32 & WINTINI_RDY || adapter->bSurpriseRemoved || adapter->bDriverStopped)
294 break;
295 yield();
296 } while (jiffies_to_msecs(jiffies - start) < timeout_ms || cnt < min_cnt);
297
298 if (!(value32 & WINTINI_RDY)) {
299 goto exit;
300 }
301
302 if (g_fwdl_wintint_rdy_fail) {
303 DBG_871X("%s: fwdl test case: wintint_rdy_fail\n", __func__);
304 g_fwdl_wintint_rdy_fail--;
305 goto exit;
306 }
307
308 ret = _SUCCESS;
309
310exit:
311 DBG_871X(
312 "%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n",
313 __func__,
314 (ret == _SUCCESS) ? "OK" : "Fail",
315 cnt,
316 jiffies_to_msecs(jiffies-start),
317 value32
318 );
319
320 return ret;
321}
322
323#define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
324
325void rtl8723b_FirmwareSelfReset(struct adapter *padapter)
326{
327 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
328 u8 u1bTmp;
329 u8 Delay = 100;
330
331 if (
332 !(IS_FW_81xxC(padapter) && ((pHalData->FirmwareVersion < 0x21) || (pHalData->FirmwareVersion == 0x21 && pHalData->FirmwareSubVersion < 0x01)))
333 ) {
334
335 rtw_write8(padapter, REG_HMETFR+3, 0x20);
336
337 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
338 while (u1bTmp & BIT2) {
339 Delay--;
340 if (Delay == 0)
341 break;
342 udelay(50);
343 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
344 }
345 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("-%s: 8051 reset success (%d)\n", __func__, Delay));
346
347 if (Delay == 0) {
348 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("%s: Force 8051 reset!!!\n", __func__));
349
350 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
351 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
352 }
353 }
354}
355
356
357
358
359
360
361s32 rtl8723b_FirmwareDownload(struct adapter *padapter, bool bUsedWoWLANFw)
362{
363 s32 rtStatus = _SUCCESS;
364 u8 write_fw = 0;
365 unsigned long fwdl_start_time;
366 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
367 struct rt_firmware *pFirmware;
368 struct rt_firmware *pBTFirmware;
369 struct rt_firmware_hdr *pFwHdr = NULL;
370 u8 *pFirmwareBuf;
371 u32 FirmwareLen;
372 const struct firmware *fw;
373 struct device *device = dvobj_to_dev(padapter->dvobj);
374 u8 *fwfilepath;
375 struct dvobj_priv *psdpriv = padapter->dvobj;
376 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
377 u8 tmp_ps;
378
379 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__));
380#ifdef CONFIG_WOWLAN
381 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("+%s, bUsedWoWLANFw:%d\n", __func__, bUsedWoWLANFw));
382#endif
383 pFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
384 if (!pFirmware)
385 return _FAIL;
386 pBTFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
387 if (!pBTFirmware) {
388 kfree(pFirmware);
389 return _FAIL;
390 }
391 tmp_ps = rtw_read8(padapter, 0xa3);
392 tmp_ps &= 0xf8;
393 tmp_ps |= 0x02;
394
395 rtw_write8(padapter, 0xa3, tmp_ps);
396
397 tmp_ps = rtw_read8(padapter, 0xa0);
398 tmp_ps &= 0x03;
399 if (tmp_ps != 0x01) {
400 DBG_871X(FUNC_ADPT_FMT" tmp_ps =%x\n", FUNC_ADPT_ARG(padapter), tmp_ps);
401 pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
402 }
403
404#ifdef CONFIG_WOWLAN
405 if (bUsedWoWLANFw)
406 fwfilepath = "rtlwifi/rtl8723bs_wowlan.bin";
407 else
408#endif
409 fwfilepath = "rtlwifi/rtl8723bs_nic.bin";
410
411 pr_info("rtl8723bs: acquire FW from file:%s\n", fwfilepath);
412
413 rtStatus = request_firmware(&fw, fwfilepath, device);
414 if (rtStatus) {
415 pr_err("Request firmware failed with error 0x%x\n", rtStatus);
416 rtStatus = _FAIL;
417 goto exit;
418 }
419
420 if (!fw) {
421 pr_err("Firmware %s not available\n", fwfilepath);
422 rtStatus = _FAIL;
423 goto exit;
424 }
425
426 if (fw->size > FW_8723B_SIZE) {
427 rtStatus = _FAIL;
428 RT_TRACE(
429 _module_hal_init_c_,
430 _drv_err_,
431 ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE)
432 );
433 goto exit;
434 }
435
436 pFirmware->szFwBuffer = kmemdup(fw->data, fw->size, GFP_KERNEL);
437 if (!pFirmware->szFwBuffer) {
438 rtStatus = _FAIL;
439 goto exit;
440 }
441
442 pFirmware->ulFwLength = fw->size;
443 release_firmware(fw);
444 if (pFirmware->ulFwLength > FW_8723B_SIZE) {
445 rtStatus = _FAIL;
446 DBG_871X_LEVEL(_drv_emerg_, "Firmware size:%u exceed %u\n", pFirmware->ulFwLength, FW_8723B_SIZE);
447 goto release_fw1;
448 }
449
450 pFirmwareBuf = pFirmware->szFwBuffer;
451 FirmwareLen = pFirmware->ulFwLength;
452
453
454 pFwHdr = (struct rt_firmware_hdr *)pFirmwareBuf;
455
456 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
457 pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->Subversion);
458 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
459
460 DBG_871X(
461 "%s: fw_ver =%x fw_subver =%04x sig = 0x%x, Month =%02x, Date =%02x, Hour =%02x, Minute =%02x\n",
462 __func__,
463 pHalData->FirmwareVersion,
464 pHalData->FirmwareSubVersion,
465 pHalData->FirmwareSignature,
466 pFwHdr->Month,
467 pFwHdr->Date,
468 pFwHdr->Hour,
469 pFwHdr->Minute
470 );
471
472 if (IS_FW_HEADER_EXIST_8723B(pFwHdr)) {
473 DBG_871X("%s(): Shift for fw header!\n", __func__);
474
475 pFirmwareBuf = pFirmwareBuf + 32;
476 FirmwareLen = FirmwareLen - 32;
477 }
478
479
480
481 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
482 rtw_write8(padapter, REG_MCUFWDL, 0x00);
483 rtl8723b_FirmwareSelfReset(padapter);
484 }
485
486 _FWDownloadEnable(padapter, true);
487 fwdl_start_time = jiffies;
488 while (
489 !padapter->bDriverStopped &&
490 !padapter->bSurpriseRemoved &&
491 (write_fw++ < 3 || jiffies_to_msecs(jiffies - fwdl_start_time) < 500)
492 ) {
493
494 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt);
495
496 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
497 if (rtStatus != _SUCCESS)
498 continue;
499
500 rtStatus = polling_fwdl_chksum(padapter, 5, 50);
501 if (rtStatus == _SUCCESS)
502 break;
503 }
504 _FWDownloadEnable(padapter, false);
505 if (_SUCCESS != rtStatus)
506 goto fwdl_stat;
507
508 rtStatus = _FWFreeToGo(padapter, 10, 200);
509 if (_SUCCESS != rtStatus)
510 goto fwdl_stat;
511
512fwdl_stat:
513 DBG_871X(
514 "FWDL %s. write_fw:%u, %dms\n",
515 (rtStatus == _SUCCESS)?"success":"fail",
516 write_fw,
517 jiffies_to_msecs(jiffies - fwdl_start_time)
518 );
519
520exit:
521 kfree(pFirmware->szFwBuffer);
522 kfree(pFirmware);
523release_fw1:
524 kfree(pBTFirmware);
525 DBG_871X(" <=== rtl8723b_FirmwareDownload()\n");
526 return rtStatus;
527}
528
529void rtl8723b_InitializeFirmwareVars(struct adapter *padapter)
530{
531 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
532
533
534 adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = false;
535
536
537 rtw_write8(padapter, REG_HMETFR, 0x0f);
538
539
540 pHalData->LastHMEBoxNum = 0;
541
542
543
544}
545
546#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
547
548
549
550
551
552
553
554
555
556
557void SetFwRelatedForWoWLAN8723b(
558 struct adapter *padapter, u8 bHostIsGoingtoSleep
559)
560{
561 int status = _FAIL;
562
563
564
565 status = rtl8723b_FirmwareDownload(padapter, bHostIsGoingtoSleep);
566 if (status != _SUCCESS) {
567 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware failed!!\n");
568 return;
569 } else {
570 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware Success !!\n");
571 }
572
573
574
575 rtl8723b_InitializeFirmwareVars(padapter);
576}
577#endif
578
579static void rtl8723b_free_hal_data(struct adapter *padapter)
580{
581}
582
583
584
585
586static u8 hal_EfuseSwitchToBank(
587 struct adapter *padapter, u8 bank, bool bPseudoTest
588)
589{
590 u8 bRet = false;
591 u32 value32 = 0;
592#ifdef HAL_EFUSE_MEMORY
593 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
594 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
595#endif
596
597
598 DBG_8192C("%s: Efuse switch bank to %d\n", __func__, bank);
599 if (bPseudoTest) {
600#ifdef HAL_EFUSE_MEMORY
601 pEfuseHal->fakeEfuseBank = bank;
602#else
603 fakeEfuseBank = bank;
604#endif
605 bRet = true;
606 } else {
607 value32 = rtw_read32(padapter, EFUSE_TEST);
608 bRet = true;
609 switch (bank) {
610 case 0:
611 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
612 break;
613 case 1:
614 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
615 break;
616 case 2:
617 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
618 break;
619 case 3:
620 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
621 break;
622 default:
623 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
624 bRet = false;
625 break;
626 }
627 rtw_write32(padapter, EFUSE_TEST, value32);
628 }
629
630 return bRet;
631}
632
633static void Hal_GetEfuseDefinition(
634 struct adapter *padapter,
635 u8 efuseType,
636 u8 type,
637 void *pOut,
638 bool bPseudoTest
639)
640{
641 switch (type) {
642 case TYPE_EFUSE_MAX_SECTION:
643 {
644 u8 *pMax_section;
645 pMax_section = pOut;
646
647 if (efuseType == EFUSE_WIFI)
648 *pMax_section = EFUSE_MAX_SECTION_8723B;
649 else
650 *pMax_section = EFUSE_BT_MAX_SECTION;
651 }
652 break;
653
654 case TYPE_EFUSE_REAL_CONTENT_LEN:
655 {
656 u16 *pu2Tmp;
657 pu2Tmp = pOut;
658
659 if (efuseType == EFUSE_WIFI)
660 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
661 else
662 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
663 }
664 break;
665
666 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
667 {
668 u16 *pu2Tmp;
669 pu2Tmp = pOut;
670
671 if (efuseType == EFUSE_WIFI)
672 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
673 else
674 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK);
675 }
676 break;
677
678 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
679 {
680 u16 *pu2Tmp;
681 pu2Tmp = pOut;
682
683 if (efuseType == EFUSE_WIFI)
684 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
685 else
686 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3));
687 }
688 break;
689
690 case TYPE_EFUSE_MAP_LEN:
691 {
692 u16 *pu2Tmp;
693 pu2Tmp = pOut;
694
695 if (efuseType == EFUSE_WIFI)
696 *pu2Tmp = EFUSE_MAX_MAP_LEN;
697 else
698 *pu2Tmp = EFUSE_BT_MAP_LEN;
699 }
700 break;
701
702 case TYPE_EFUSE_PROTECT_BYTES_BANK:
703 {
704 u8 *pu1Tmp;
705 pu1Tmp = pOut;
706
707 if (efuseType == EFUSE_WIFI)
708 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
709 else
710 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
711 }
712 break;
713
714 case TYPE_EFUSE_CONTENT_LEN_BANK:
715 {
716 u16 *pu2Tmp;
717 pu2Tmp = pOut;
718
719 if (efuseType == EFUSE_WIFI)
720 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
721 else
722 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
723 }
724 break;
725
726 default:
727 {
728 u8 *pu1Tmp;
729 pu1Tmp = pOut;
730 *pu1Tmp = 0;
731 }
732 break;
733 }
734}
735
736#define VOLTAGE_V25 0x03
737#define LDOE25_SHIFT 28
738
739
740
741
742
743#define EFUSE_ACCESS_ON_8723 0x69
744#define EFUSE_ACCESS_OFF_8723 0x00
745#define REG_EFUSE_ACCESS_8723 0x00CF
746
747
748static void Hal_BT_EfusePowerSwitch(
749 struct adapter *padapter, u8 bWrite, u8 PwrState
750)
751{
752 u8 tempval;
753 if (PwrState == true) {
754
755
756 tempval = rtw_read8(padapter, 0x6B);
757 tempval |= BIT(6);
758 rtw_write8(padapter, 0x6B, tempval);
759
760
761
762 msleep(1);
763
764
765 tempval = rtw_read8(padapter, 0x6B);
766 tempval &= ~BIT(7);
767 rtw_write8(padapter, 0x6B, tempval);
768 } else {
769
770
771 tempval = rtw_read8(padapter, 0x6B);
772 tempval |= BIT(7);
773 rtw_write8(padapter, 0x6B, tempval);
774
775
776
777
778
779
780 tempval = rtw_read8(padapter, 0x6B);
781 tempval &= ~BIT(6);
782 rtw_write8(padapter, 0x6B, tempval);
783 }
784
785}
786static void Hal_EfusePowerSwitch(
787 struct adapter *padapter, u8 bWrite, u8 PwrState
788)
789{
790 u8 tempval;
791 u16 tmpV16;
792
793
794 if (PwrState == true) {
795
796
797 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
798 if (tempval & BIT(0)) {
799 u8 count = 0;
800
801
802 tempval &= ~BIT(0);
803 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL, tempval);
804
805
806 do {
807 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
808 tempval &= 0x3;
809 if (tempval == 0x02)
810 break;
811
812 count++;
813 if (count >= 100)
814 break;
815
816 mdelay(10);
817 } while (1);
818
819 if (count >= 100) {
820 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86 =%#X\n",
821 FUNC_ADPT_ARG(padapter), tempval);
822 } else {
823 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86 =%#X\n",
824 FUNC_ADPT_ARG(padapter), tempval);
825 }
826 }
827
828 rtw_write8(padapter, REG_EFUSE_ACCESS_8723, EFUSE_ACCESS_ON_8723);
829
830
831 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
832 if (!(tmpV16 & FEN_ELDR)) {
833 tmpV16 |= FEN_ELDR;
834 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
835 }
836
837
838 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
839 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
840 tmpV16 |= (LOADER_CLK_EN | ANA8M);
841 rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
842 }
843
844 if (bWrite == true) {
845
846 tempval = rtw_read8(padapter, EFUSE_TEST+3);
847 tempval &= 0x0F;
848 tempval |= (VOLTAGE_V25 << 4);
849 rtw_write8(padapter, EFUSE_TEST+3, (tempval | 0x80));
850
851
852 }
853 } else {
854 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
855
856 if (bWrite == true) {
857
858 tempval = rtw_read8(padapter, EFUSE_TEST+3);
859 rtw_write8(padapter, EFUSE_TEST+3, (tempval & 0x7F));
860 }
861
862 }
863}
864
865static void hal_ReadEFuse_WiFi(
866 struct adapter *padapter,
867 u16 _offset,
868 u16 _size_byte,
869 u8 *pbuf,
870 bool bPseudoTest
871)
872{
873#ifdef HAL_EFUSE_MEMORY
874 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
875 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
876#endif
877 u8 *efuseTbl = NULL;
878 u16 eFuse_Addr = 0;
879 u8 offset, wden;
880 u8 efuseHeader, efuseExtHdr, efuseData;
881 u16 i, total, used;
882 u8 efuse_usage = 0;
883
884
885
886
887
888 if ((_offset+_size_byte) > EFUSE_MAX_MAP_LEN) {
889 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte);
890 return;
891 }
892
893 efuseTbl = rtw_malloc(EFUSE_MAX_MAP_LEN);
894 if (efuseTbl == NULL) {
895 DBG_8192C("%s: alloc efuseTbl fail!\n", __func__);
896 return;
897 }
898
899 memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
900
901
902#ifdef DEBUG
903if (0) {
904 for (i = 0; i < 256; i++)
905 efuse_OneByteRead(padapter, i, &efuseTbl[i], false);
906 DBG_871X("Efuse Content:\n");
907 for (i = 0; i < 256; i++) {
908 if (i % 16 == 0)
909 printk("\n");
910 printk("%02X ", efuseTbl[i]);
911 }
912 printk("\n");
913}
914#endif
915
916
917
918 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
919
920 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
921 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
922 if (efuseHeader == 0xFF) {
923 DBG_8192C("%s: data end at address =%#x\n", __func__, eFuse_Addr-1);
924 break;
925 }
926
927
928
929 if (EXT_HEADER(efuseHeader)) {
930 offset = GET_HDR_OFFSET_2_0(efuseHeader);
931
932
933 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
934
935 if (ALL_WORDS_DISABLED(efuseExtHdr))
936 continue;
937
938 offset |= ((efuseExtHdr & 0xF0) >> 1);
939 wden = (efuseExtHdr & 0x0F);
940 } else {
941 offset = ((efuseHeader >> 4) & 0x0f);
942 wden = (efuseHeader & 0x0f);
943 }
944
945
946 if (offset < EFUSE_MAX_SECTION_8723B) {
947 u16 addr;
948
949
950
951 addr = offset * PGPKT_DATA_SIZE;
952 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
953
954 if (!(wden & (0x01<<i))) {
955 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
956
957 efuseTbl[addr] = efuseData;
958
959 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
960
961 efuseTbl[addr+1] = efuseData;
962 }
963 addr += 2;
964 }
965 } else {
966 DBG_8192C(KERN_ERR "%s: offset(%d) is illegal!!\n", __func__, offset);
967 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
968 }
969 }
970
971
972 for (i = 0; i < _size_byte; i++)
973 pbuf[i] = efuseTbl[_offset+i];
974
975#ifdef DEBUG
976if (1) {
977 DBG_871X("Efuse Realmap:\n");
978 for (i = 0; i < _size_byte; i++) {
979 if (i % 16 == 0)
980 printk("\n");
981 printk("%02X ", pbuf[i]);
982 }
983 printk("\n");
984}
985#endif
986
987 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
988 used = eFuse_Addr - 1;
989 efuse_usage = (u8)((used*100)/total);
990 if (bPseudoTest) {
991#ifdef HAL_EFUSE_MEMORY
992 pEfuseHal->fakeEfuseUsedBytes = used;
993#else
994 fakeEfuseUsedBytes = used;
995#endif
996 } else {
997 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
998 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
999 }
1000
1001 kfree(efuseTbl);
1002}
1003
1004static void hal_ReadEFuse_BT(
1005 struct adapter *padapter,
1006 u16 _offset,
1007 u16 _size_byte,
1008 u8 *pbuf,
1009 bool bPseudoTest
1010)
1011{
1012#ifdef HAL_EFUSE_MEMORY
1013 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1014 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1015#endif
1016 u8 *efuseTbl;
1017 u8 bank;
1018 u16 eFuse_Addr;
1019 u8 efuseHeader, efuseExtHdr, efuseData;
1020 u8 offset, wden;
1021 u16 i, total, used;
1022 u8 efuse_usage;
1023
1024
1025
1026
1027
1028 if ((_offset+_size_byte) > EFUSE_BT_MAP_LEN) {
1029 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte);
1030 return;
1031 }
1032
1033 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
1034 if (efuseTbl == NULL) {
1035 DBG_8192C("%s: efuseTbl malloc fail!\n", __func__);
1036 return;
1037 }
1038
1039 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
1040
1041 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
1042
1043 for (bank = 1; bank < 3; bank++) {
1044 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) {
1045 DBG_8192C("%s: hal_EfuseSwitchToBank Fail!!\n", __func__);
1046 goto exit;
1047 }
1048
1049 eFuse_Addr = 0;
1050
1051 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
1052 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1053 if (efuseHeader == 0xFF)
1054 break;
1055 DBG_8192C("%s: efuse[%#X]= 0x%02x (header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseHeader);
1056
1057
1058 if (EXT_HEADER(efuseHeader)) {
1059 offset = GET_HDR_OFFSET_2_0(efuseHeader);
1060 DBG_8192C("%s: extended header offset_2_0 = 0x%X\n", __func__, offset);
1061
1062 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
1063 DBG_8192C("%s: efuse[%#X]= 0x%02x (ext header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseExtHdr);
1064 if (ALL_WORDS_DISABLED(efuseExtHdr))
1065 continue;
1066
1067
1068 offset |= ((efuseExtHdr & 0xF0) >> 1);
1069 wden = (efuseExtHdr & 0x0F);
1070 } else {
1071 offset = ((efuseHeader >> 4) & 0x0f);
1072 wden = (efuseHeader & 0x0f);
1073 }
1074
1075 if (offset < EFUSE_BT_MAX_SECTION) {
1076 u16 addr;
1077
1078
1079 DBG_8192C("%s: Offset =%d Worden =%#X\n", __func__, offset, wden);
1080
1081 addr = offset * PGPKT_DATA_SIZE;
1082 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1083
1084 if (!(wden & (0x01<<i))) {
1085 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1086 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData);
1087 efuseTbl[addr] = efuseData;
1088
1089 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1090 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData);
1091 efuseTbl[addr+1] = efuseData;
1092 }
1093 addr += 2;
1094 }
1095 } else {
1096 DBG_8192C("%s: offset(%d) is illegal!!\n", __func__, offset);
1097 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
1098 }
1099 }
1100
1101 if ((eFuse_Addr-1) < total) {
1102 DBG_8192C("%s: bank(%d) data end at %#x\n", __func__, bank, eFuse_Addr-1);
1103 break;
1104 }
1105 }
1106
1107
1108 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1109
1110
1111 for (i = 0; i < _size_byte; i++)
1112 pbuf[i] = efuseTbl[_offset+i];
1113
1114
1115
1116
1117 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
1118 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1;
1119 DBG_8192C("%s: bank(%d) data end at %#x , used =%d\n", __func__, bank, eFuse_Addr-1, used);
1120 efuse_usage = (u8)((used*100)/total);
1121 if (bPseudoTest) {
1122#ifdef HAL_EFUSE_MEMORY
1123 pEfuseHal->fakeBTEfuseUsedBytes = used;
1124#else
1125 fakeBTEfuseUsedBytes = used;
1126#endif
1127 } else {
1128 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
1129 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
1130 }
1131
1132exit:
1133 kfree(efuseTbl);
1134}
1135
1136static void Hal_ReadEFuse(
1137 struct adapter *padapter,
1138 u8 efuseType,
1139 u16 _offset,
1140 u16 _size_byte,
1141 u8 *pbuf,
1142 bool bPseudoTest
1143)
1144{
1145 if (efuseType == EFUSE_WIFI)
1146 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1147 else
1148 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1149}
1150
1151static u16 hal_EfuseGetCurrentSize_WiFi(
1152 struct adapter *padapter, bool bPseudoTest
1153)
1154{
1155#ifdef HAL_EFUSE_MEMORY
1156 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1157 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1158#endif
1159 u16 efuse_addr = 0;
1160 u16 start_addr = 0;
1161 u8 hoffset = 0, hworden = 0;
1162 u8 efuse_data, word_cnts = 0;
1163 u32 count = 0;
1164
1165
1166 if (bPseudoTest) {
1167#ifdef HAL_EFUSE_MEMORY
1168 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
1169#else
1170 efuse_addr = (u16)fakeEfuseUsedBytes;
1171#endif
1172 } else
1173 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1174
1175 start_addr = efuse_addr;
1176 DBG_8192C("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr);
1177
1178
1179 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1180
1181 count = 0;
1182 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1183 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) {
1184 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr);
1185 goto error;
1186 }
1187
1188 if (efuse_data == 0xFF)
1189 break;
1190
1191 if ((start_addr != 0) && (efuse_addr == start_addr)) {
1192 count++;
1193 DBG_8192C(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X = 0x%02X not 0xFF!!(%d times)\n",
1194 FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count);
1195
1196 efuse_data = 0xFF;
1197 if (count < 4) {
1198
1199
1200 if (count > 2) {
1201
1202 efuse_addr = 0;
1203 start_addr = 0;
1204 }
1205
1206 continue;
1207 }
1208
1209 goto error;
1210 }
1211
1212 if (EXT_HEADER(efuse_data)) {
1213 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1214 efuse_addr++;
1215 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1216 if (ALL_WORDS_DISABLED(efuse_data))
1217 continue;
1218
1219 hoffset |= ((efuse_data & 0xF0) >> 1);
1220 hworden = efuse_data & 0x0F;
1221 } else {
1222 hoffset = (efuse_data>>4) & 0x0F;
1223 hworden = efuse_data & 0x0F;
1224 }
1225
1226 word_cnts = Efuse_CalculateWordCnts(hworden);
1227 efuse_addr += (word_cnts*2)+1;
1228 }
1229
1230 if (bPseudoTest) {
1231#ifdef HAL_EFUSE_MEMORY
1232 pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
1233#else
1234 fakeEfuseUsedBytes = efuse_addr;
1235#endif
1236 } else
1237 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1238
1239 goto exit;
1240
1241error:
1242
1243 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
1244
1245exit:
1246 DBG_8192C("%s: CurrentSize =%d\n", __func__, efuse_addr);
1247
1248 return efuse_addr;
1249}
1250
1251static u16 hal_EfuseGetCurrentSize_BT(struct adapter *padapter, u8 bPseudoTest)
1252{
1253#ifdef HAL_EFUSE_MEMORY
1254 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1255 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1256#endif
1257 u16 btusedbytes;
1258 u16 efuse_addr;
1259 u8 bank, startBank;
1260 u8 hoffset = 0, hworden = 0;
1261 u8 efuse_data, word_cnts = 0;
1262 u16 retU2 = 0;
1263
1264 if (bPseudoTest) {
1265#ifdef HAL_EFUSE_MEMORY
1266 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
1267#else
1268 btusedbytes = fakeBTEfuseUsedBytes;
1269#endif
1270 } else
1271 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
1272
1273 efuse_addr = (u16)((btusedbytes%EFUSE_BT_REAL_BANK_CONTENT_LEN));
1274 startBank = (u8)(1+(btusedbytes/EFUSE_BT_REAL_BANK_CONTENT_LEN));
1275
1276 DBG_8192C("%s: start from bank =%d addr = 0x%X\n", __func__, startBank, efuse_addr);
1277
1278 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
1279
1280 for (bank = startBank; bank < 3; bank++) {
1281 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) {
1282 DBG_8192C(KERN_ERR "%s: switch bank(%d) Fail!!\n", __func__, bank);
1283
1284 break;
1285 }
1286
1287
1288 if (bank != startBank)
1289 efuse_addr = 0;
1290#if 1
1291
1292 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1293 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) {
1294 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr);
1295
1296 break;
1297 }
1298 DBG_8192C("%s: efuse_OneByteRead ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank);
1299
1300 if (efuse_data == 0xFF)
1301 break;
1302
1303 if (EXT_HEADER(efuse_data)) {
1304 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1305 efuse_addr++;
1306 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1307 DBG_8192C("%s: efuse_OneByteRead EXT_HEADER ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank);
1308
1309 if (ALL_WORDS_DISABLED(efuse_data)) {
1310 efuse_addr++;
1311 continue;
1312 }
1313
1314
1315 hoffset |= ((efuse_data & 0xF0) >> 1);
1316 hworden = efuse_data & 0x0F;
1317 } else {
1318 hoffset = (efuse_data>>4) & 0x0F;
1319 hworden = efuse_data & 0x0F;
1320 }
1321
1322 DBG_8192C(FUNC_ADPT_FMT": Offset =%d Worden =%#X\n",
1323 FUNC_ADPT_ARG(padapter), hoffset, hworden);
1324
1325 word_cnts = Efuse_CalculateWordCnts(hworden);
1326
1327 efuse_addr += (word_cnts*2)+1;
1328 }
1329#else
1330 while (
1331 bContinual &&
1332 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) &&
1333 AVAILABLE_EFUSE_ADDR(efuse_addr)
1334 ) {
1335 if (efuse_data != 0xFF) {
1336 if ((efuse_data&0x1F) == 0x0F) {
1337 hoffset = efuse_data;
1338 efuse_addr++;
1339 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1340 if ((efuse_data & 0x0F) == 0x0F) {
1341 efuse_addr++;
1342 continue;
1343 } else {
1344 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1345 hworden = efuse_data & 0x0F;
1346 }
1347 } else {
1348 hoffset = (efuse_data>>4) & 0x0F;
1349 hworden = efuse_data & 0x0F;
1350 }
1351 word_cnts = Efuse_CalculateWordCnts(hworden);
1352
1353 efuse_addr = efuse_addr + (word_cnts*2)+1;
1354 } else
1355 bContinual = false;
1356 }
1357#endif
1358
1359
1360
1361 if (efuse_addr < retU2)
1362 break;
1363 }
1364
1365 retU2 = ((bank-1)*EFUSE_BT_REAL_BANK_CONTENT_LEN)+efuse_addr;
1366 if (bPseudoTest) {
1367 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
1368
1369 } else {
1370 pEfuseHal->BTEfuseUsedBytes = retU2;
1371
1372 }
1373
1374 DBG_8192C("%s: CurrentSize =%d\n", __func__, retU2);
1375 return retU2;
1376}
1377
1378static u16 Hal_EfuseGetCurrentSize(
1379 struct adapter *padapter, u8 efuseType, bool bPseudoTest
1380)
1381{
1382 u16 ret = 0;
1383
1384 if (efuseType == EFUSE_WIFI)
1385 ret = hal_EfuseGetCurrentSize_WiFi(padapter, bPseudoTest);
1386 else
1387 ret = hal_EfuseGetCurrentSize_BT(padapter, bPseudoTest);
1388
1389 return ret;
1390}
1391
1392static u8 Hal_EfuseWordEnableDataWrite(
1393 struct adapter *padapter,
1394 u16 efuse_addr,
1395 u8 word_en,
1396 u8 *data,
1397 bool bPseudoTest
1398)
1399{
1400 u16 tmpaddr = 0;
1401 u16 start_addr = efuse_addr;
1402 u8 badworden = 0x0F;
1403 u8 tmpdata[PGPKT_DATA_SIZE];
1404
1405
1406
1407 memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
1408
1409 if (!(word_en & BIT(0))) {
1410 tmpaddr = start_addr;
1411 efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest);
1412 efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest);
1413
1414 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest);
1415 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[1], bPseudoTest);
1416 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1])) {
1417 badworden &= (~BIT(0));
1418 }
1419 }
1420 if (!(word_en & BIT(1))) {
1421 tmpaddr = start_addr;
1422 efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest);
1423 efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest);
1424
1425 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest);
1426 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[3], bPseudoTest);
1427 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3])) {
1428 badworden &= (~BIT(1));
1429 }
1430 }
1431
1432 if (!(word_en & BIT(2))) {
1433 tmpaddr = start_addr;
1434 efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest);
1435 efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest);
1436
1437 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest);
1438 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[5], bPseudoTest);
1439 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5])) {
1440 badworden &= (~BIT(2));
1441 }
1442 }
1443
1444 if (!(word_en & BIT(3))) {
1445 tmpaddr = start_addr;
1446 efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest);
1447 efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest);
1448
1449 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest);
1450 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[7], bPseudoTest);
1451 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7])) {
1452 badworden &= (~BIT(3));
1453 }
1454 }
1455
1456 return badworden;
1457}
1458
1459static s32 Hal_EfusePgPacketRead(
1460 struct adapter *padapter,
1461 u8 offset,
1462 u8 *data,
1463 bool bPseudoTest
1464)
1465{
1466 u8 efuse_data, word_cnts = 0;
1467 u16 efuse_addr = 0;
1468 u8 hoffset = 0, hworden = 0;
1469 u8 i;
1470 u8 max_section = 0;
1471 s32 ret;
1472
1473
1474 if (data == NULL)
1475 return false;
1476
1477 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest);
1478 if (offset > max_section) {
1479 DBG_8192C("%s: Packet offset(%d) is illegal(>%d)!\n", __func__, offset, max_section);
1480 return false;
1481 }
1482
1483 memset(data, 0xFF, PGPKT_DATA_SIZE);
1484 ret = true;
1485
1486
1487
1488
1489
1490
1491 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1492 if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == false) {
1493 ret = false;
1494 break;
1495 }
1496
1497 if (efuse_data == 0xFF)
1498 break;
1499
1500 if (EXT_HEADER(efuse_data)) {
1501 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1502 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
1503 if (ALL_WORDS_DISABLED(efuse_data)) {
1504 DBG_8192C("%s: Error!! All words disabled!\n", __func__);
1505 continue;
1506 }
1507
1508 hoffset |= ((efuse_data & 0xF0) >> 1);
1509 hworden = efuse_data & 0x0F;
1510 } else {
1511 hoffset = (efuse_data>>4) & 0x0F;
1512 hworden = efuse_data & 0x0F;
1513 }
1514
1515 if (hoffset == offset) {
1516 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1517
1518 if (!(hworden & (0x01<<i))) {
1519 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
1520
1521 data[i*2] = efuse_data;
1522
1523 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
1524
1525 data[(i*2)+1] = efuse_data;
1526 }
1527 }
1528 } else {
1529 word_cnts = Efuse_CalculateWordCnts(hworden);
1530 efuse_addr += word_cnts*2;
1531 }
1532 }
1533
1534 return ret;
1535}
1536
1537static u8 hal_EfusePgCheckAvailableAddr(
1538 struct adapter *padapter, u8 efuseType, u8 bPseudoTest
1539)
1540{
1541 u16 max_available = 0;
1542 u16 current_size;
1543
1544
1545 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest);
1546
1547
1548 current_size = Efuse_GetCurrentSize(padapter, efuseType, bPseudoTest);
1549 if (current_size >= max_available) {
1550 DBG_8192C("%s: Error!! current_size(%d)>max_available(%d)\n", __func__, current_size, max_available);
1551 return false;
1552 }
1553 return true;
1554}
1555
1556static void hal_EfuseConstructPGPkt(
1557 u8 offset,
1558 u8 word_en,
1559 u8 *pData,
1560 PPGPKT_STRUCT pTargetPkt
1561)
1562{
1563 memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
1564 pTargetPkt->offset = offset;
1565 pTargetPkt->word_en = word_en;
1566 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
1567 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1568}
1569
1570static u8 hal_EfusePartialWriteCheck(
1571 struct adapter *padapter,
1572 u8 efuseType,
1573 u16 *pAddr,
1574 PPGPKT_STRUCT pTargetPkt,
1575 u8 bPseudoTest
1576)
1577{
1578 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1579 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1580 u8 bRet = false;
1581 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
1582 u8 efuse_data = 0;
1583
1584 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest);
1585 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest);
1586
1587 if (efuseType == EFUSE_WIFI) {
1588 if (bPseudoTest) {
1589#ifdef HAL_EFUSE_MEMORY
1590 startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes;
1591#else
1592 startAddr = (u16)fakeEfuseUsedBytes;
1593#endif
1594 } else
1595 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
1596 } else {
1597 if (bPseudoTest) {
1598#ifdef HAL_EFUSE_MEMORY
1599 startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes;
1600#else
1601 startAddr = (u16)fakeBTEfuseUsedBytes;
1602#endif
1603 } else
1604 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr);
1605 }
1606 startAddr %= efuse_max;
1607 DBG_8192C("%s: startAddr =%#X\n", __func__, startAddr);
1608
1609 while (1) {
1610 if (startAddr >= efuse_max_available_len) {
1611 bRet = false;
1612 DBG_8192C("%s: startAddr(%d) >= efuse_max_available_len(%d)\n", __func__, startAddr, efuse_max_available_len);
1613 break;
1614 }
1615
1616 if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
1617#if 1
1618 bRet = false;
1619 DBG_8192C("%s: Something Wrong! last bytes(%#X = 0x%02X) is not 0xFF\n",
1620 __func__, startAddr, efuse_data);
1621 break;
1622#else
1623 if (EXT_HEADER(efuse_data)) {
1624 cur_header = efuse_data;
1625 startAddr++;
1626 efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest);
1627 if (ALL_WORDS_DISABLED(efuse_data)) {
1628 DBG_8192C("%s: Error condition, all words disabled!", __func__);
1629 bRet = false;
1630 break;
1631 } else {
1632 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1633 curPkt.word_en = efuse_data & 0x0F;
1634 }
1635 } else {
1636 cur_header = efuse_data;
1637 curPkt.offset = (cur_header>>4) & 0x0F;
1638 curPkt.word_en = cur_header & 0x0F;
1639 }
1640
1641 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
1642
1643
1644 if (
1645 (curPkt.offset == pTargetPkt->offset) &&
1646 (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr+1, bPseudoTest) == false) &&
1647 wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == true
1648 ) {
1649 DBG_8192C("%s: Need to partial write data by the previous wrote header\n", __func__);
1650
1651 badworden = Efuse_WordEnableDataWrite(padapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest);
1652 if (badworden != 0x0F) {
1653 u32 PgWriteSuccess = 0;
1654
1655 if (efuseType == EFUSE_WIFI)
1656 PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1657 else
1658 PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
1659
1660 if (!PgWriteSuccess) {
1661 bRet = false;
1662 break;
1663 }
1664 }
1665
1666 for (i = 0; i < 4; i++) {
1667 if ((matched_wden & (0x1<<i)) == 0) {
1668 pTargetPkt->word_en |= (0x1<<i);
1669 }
1670 }
1671 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
1672 }
1673
1674 startAddr = startAddr + (curPkt.word_cnts*2) + 1;
1675#endif
1676 } else {
1677
1678 *pAddr = startAddr;
1679
1680 bRet = true;
1681 break;
1682 }
1683 }
1684
1685 return bRet;
1686}
1687
1688static u8 hal_EfusePgPacketWrite1ByteHeader(
1689 struct adapter *padapter,
1690 u8 efuseType,
1691 u16 *pAddr,
1692 PPGPKT_STRUCT pTargetPkt,
1693 u8 bPseudoTest
1694)
1695{
1696 u8 pg_header = 0, tmp_header = 0;
1697 u16 efuse_addr = *pAddr;
1698 u8 repeatcnt = 0;
1699
1700
1701
1702 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
1703
1704 do {
1705 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
1706 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
1707 if (tmp_header != 0xFF)
1708 break;
1709 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1710 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__);
1711 return false;
1712 }
1713 } while (1);
1714
1715 if (tmp_header != pg_header) {
1716 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header);
1717 return false;
1718 }
1719
1720 *pAddr = efuse_addr;
1721
1722 return true;
1723}
1724
1725static u8 hal_EfusePgPacketWrite2ByteHeader(
1726 struct adapter *padapter,
1727 u8 efuseType,
1728 u16 *pAddr,
1729 PPGPKT_STRUCT pTargetPkt,
1730 u8 bPseudoTest
1731)
1732{
1733 u16 efuse_addr, efuse_max_available_len = 0;
1734 u8 pg_header = 0, tmp_header = 0;
1735 u8 repeatcnt = 0;
1736
1737
1738
1739 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest);
1740
1741 efuse_addr = *pAddr;
1742 if (efuse_addr >= efuse_max_available_len) {
1743 DBG_8192C("%s: addr(%d) over available (%d)!!\n", __func__,
1744 efuse_addr, efuse_max_available_len);
1745 return false;
1746 }
1747
1748 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
1749
1750
1751 do {
1752 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
1753 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
1754 if (tmp_header != 0xFF)
1755 break;
1756 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1757 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__);
1758 return false;
1759 }
1760 } while (1);
1761
1762 if (tmp_header != pg_header) {
1763 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header);
1764 return false;
1765 }
1766
1767
1768 efuse_addr++;
1769 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
1770
1771 do {
1772 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
1773 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
1774 if (tmp_header != 0xFF)
1775 break;
1776 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
1777 DBG_8192C("%s: Repeat over limit for ext_header!!\n", __func__);
1778 return false;
1779 }
1780 } while (1);
1781
1782 if (tmp_header != pg_header) {
1783 DBG_8192C(KERN_ERR "%s: PG EXT Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header);
1784 return false;
1785 }
1786
1787 *pAddr = efuse_addr;
1788
1789 return true;
1790}
1791
1792static u8 hal_EfusePgPacketWriteHeader(
1793 struct adapter *padapter,
1794 u8 efuseType,
1795 u16 *pAddr,
1796 PPGPKT_STRUCT pTargetPkt,
1797 u8 bPseudoTest
1798)
1799{
1800 u8 bRet = false;
1801
1802 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
1803 bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1804 else
1805 bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
1806
1807 return bRet;
1808}
1809
1810static u8 hal_EfusePgPacketWriteData(
1811 struct adapter *padapter,
1812 u8 efuseType,
1813 u16 *pAddr,
1814 PPGPKT_STRUCT pTargetPkt,
1815 u8 bPseudoTest
1816)
1817{
1818 u16 efuse_addr;
1819 u8 badworden;
1820
1821
1822 efuse_addr = *pAddr;
1823 badworden = Efuse_WordEnableDataWrite(padapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
1824 if (badworden != 0x0F) {
1825 DBG_8192C("%s: Fail!!\n", __func__);
1826 return false;
1827 }
1828
1829
1830 return true;
1831}
1832
1833static s32 Hal_EfusePgPacketWrite(
1834 struct adapter *padapter,
1835 u8 offset,
1836 u8 word_en,
1837 u8 *pData,
1838 bool bPseudoTest
1839)
1840{
1841 PGPKT_STRUCT targetPkt;
1842 u16 startAddr = 0;
1843 u8 efuseType = EFUSE_WIFI;
1844
1845 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
1846 return false;
1847
1848 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
1849
1850 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1851 return false;
1852
1853 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1854 return false;
1855
1856 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1857 return false;
1858
1859 return true;
1860}
1861
1862static bool Hal_EfusePgPacketWrite_BT(
1863 struct adapter *padapter,
1864 u8 offset,
1865 u8 word_en,
1866 u8 *pData,
1867 bool bPseudoTest
1868)
1869{
1870 PGPKT_STRUCT targetPkt;
1871 u16 startAddr = 0;
1872 u8 efuseType = EFUSE_BT;
1873
1874 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
1875 return false;
1876
1877 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
1878
1879 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1880 return false;
1881
1882 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1883 return false;
1884
1885 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
1886 return false;
1887
1888 return true;
1889}
1890
1891static HAL_VERSION ReadChipVersion8723B(struct adapter *padapter)
1892{
1893 u32 value32;
1894 HAL_VERSION ChipVersion;
1895 struct hal_com_data *pHalData;
1896
1897
1898 pHalData = GET_HAL_DATA(padapter);
1899
1900 value32 = rtw_read32(padapter, REG_SYS_CFG);
1901 ChipVersion.ICType = CHIP_8723B;
1902 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
1903 ChipVersion.RFType = RF_TYPE_1T1R;
1904 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
1905 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT;
1906
1907
1908 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
1909
1910 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
1911 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20);
1912
1913
1914 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
1915 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
1916 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
1917 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
1918 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
1919 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
1920#if 1
1921 dump_chip_info(ChipVersion);
1922#endif
1923 pHalData->VersionID = ChipVersion;
1924 if (IS_1T2R(ChipVersion))
1925 pHalData->rf_type = RF_1T2R;
1926 else if (IS_2T2R(ChipVersion))
1927 pHalData->rf_type = RF_2T2R;
1928 else
1929 pHalData->rf_type = RF_1T1R;
1930
1931 MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type);
1932
1933 return ChipVersion;
1934}
1935
1936static void rtl8723b_read_chip_version(struct adapter *padapter)
1937{
1938 ReadChipVersion8723B(padapter);
1939}
1940
1941void rtl8723b_InitBeaconParameters(struct adapter *padapter)
1942{
1943 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1944 u16 val16;
1945 u8 val8;
1946
1947
1948 val8 = DIS_TSF_UDT;
1949 val16 = val8 | (val8 << 8);
1950
1951
1952 val16 |= EN_BCN_FUNCTION;
1953
1954 rtw_write16(padapter, REG_BCN_CTRL, val16);
1955
1956
1957 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);
1958
1959
1960 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
1961 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8723B);
1962 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723B);
1963
1964
1965
1966 rtw_write16(padapter, REG_BCNTCFG, 0x660F);
1967
1968 pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL);
1969 pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE);
1970 pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
1971 pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2);
1972 pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1);
1973}
1974
1975void _InitBurstPktLen_8723BS(struct adapter *Adapter)
1976{
1977 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1978
1979 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7));
1980 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8723B, 0x18);
1981 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8723B, 0x1F);
1982 rtw_write8(Adapter, REG_PIFS_8723B, 0x00);
1983 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7)));
1984 if (pHalData->AMPDUBurstMode)
1985 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8723B, 0x5F);
1986 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8723B, 0x70);
1987
1988
1989 rtw_write32(Adapter, REG_ARFR0_8723B, 0x00000010);
1990 if (IS_NORMAL_CHIP(pHalData->VersionID))
1991 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0xfffff000);
1992 else
1993 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0x3e0ff000);
1994
1995
1996 rtw_write32(Adapter, REG_ARFR1_8723B, 0x00000010);
1997 rtw_write32(Adapter, REG_ARFR1_8723B+4, 0x003ff000);
1998}
1999
2000static void ResumeTxBeacon(struct adapter *padapter)
2001{
2002 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2003
2004
2005
2006
2007
2008 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
2009
2010 pHalData->RegFwHwTxQCtrl |= BIT(6);
2011 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
2012 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff);
2013 pHalData->RegReg542 |= BIT(0);
2014 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
2015}
2016
2017static void StopTxBeacon(struct adapter *padapter)
2018{
2019 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2020
2021
2022
2023
2024
2025 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
2026
2027 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
2028 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
2029 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
2030 pHalData->RegReg542 &= ~BIT(0);
2031 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
2032
2033 CheckFwRsvdPageContent(padapter);
2034}
2035
2036static void _BeaconFunctionEnable(struct adapter *padapter, u8 Enable, u8 Linked)
2037{
2038 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
2039 rtw_write8(padapter, REG_RD_CTRL+1, 0x6F);
2040}
2041
2042static void rtl8723b_SetBeaconRelatedRegisters(struct adapter *padapter)
2043{
2044 u8 val8;
2045 u32 value32;
2046 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2047 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2048 u32 bcn_ctrl_reg;
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063 bcn_ctrl_reg = REG_BCN_CTRL;
2064
2065
2066
2067
2068 rtw_write16(padapter, REG_ATIMWND, 2);
2069
2070
2071
2072
2073 rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2074
2075 rtl8723b_InitBeaconParameters(padapter);
2076
2077 rtw_write8(padapter, REG_SLOT, 0x09);
2078
2079
2080
2081
2082 value32 = rtw_read32(padapter, REG_TCR);
2083 value32 &= ~TSFRST;
2084 rtw_write32(padapter, REG_TCR, value32);
2085
2086 value32 |= TSFRST;
2087 rtw_write32(padapter, REG_TCR, value32);
2088
2089
2090 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == true) {
2091 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
2092 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
2093 }
2094
2095 _BeaconFunctionEnable(padapter, true, true);
2096
2097 ResumeTxBeacon(padapter);
2098 val8 = rtw_read8(padapter, bcn_ctrl_reg);
2099 val8 |= DIS_BCNQ_SUB;
2100 rtw_write8(padapter, bcn_ctrl_reg, val8);
2101}
2102
2103static void rtl8723b_GetHalODMVar(
2104 struct adapter *Adapter,
2105 enum HAL_ODM_VARIABLE eVariable,
2106 void *pValue1,
2107 void *pValue2
2108)
2109{
2110 GetHalODMVar(Adapter, eVariable, pValue1, pValue2);
2111}
2112
2113static void rtl8723b_SetHalODMVar(
2114 struct adapter *Adapter,
2115 enum HAL_ODM_VARIABLE eVariable,
2116 void *pValue1,
2117 bool bSet
2118)
2119{
2120 SetHalODMVar(Adapter, eVariable, pValue1, bSet);
2121}
2122
2123static void hal_notch_filter_8723b(struct adapter *adapter, bool enable)
2124{
2125 if (enable) {
2126 DBG_871X("Enable notch filter\n");
2127 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
2128 } else {
2129 DBG_871X("Disable notch filter\n");
2130 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
2131 }
2132}
2133
2134static void UpdateHalRAMask8723B(struct adapter *padapter, u32 mac_id, u8 rssi_level)
2135{
2136 u32 mask, rate_bitmap;
2137 u8 shortGIrate = false;
2138 struct sta_info *psta;
2139 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2140 struct dm_priv *pdmpriv = &pHalData->dmpriv;
2141 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2142 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2143
2144 DBG_871X("%s(): mac_id =%d rssi_level =%d\n", __func__, mac_id, rssi_level);
2145
2146 if (mac_id >= NUM_STA)
2147 return;
2148
2149 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2150 if (psta == NULL)
2151 return;
2152
2153 shortGIrate = query_ra_short_GI(psta);
2154
2155 mask = psta->ra_mask;
2156
2157 rate_bitmap = 0xffffffff;
2158 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level);
2159 DBG_871X("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2160 __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap);
2161
2162 mask &= rate_bitmap;
2163
2164 rate_bitmap = rtw_btcoex_GetRaMask(padapter);
2165 mask &= ~rate_bitmap;
2166
2167#ifdef CONFIG_CMCC_TEST
2168 if (pmlmeext->cur_wireless_mode & WIRELESS_11G) {
2169 if (mac_id == 0) {
2170 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask);
2171 mask &= 0xffffff00;
2172 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask);
2173 }
2174 }
2175#endif
2176
2177 if (pHalData->fw_ractrl == true) {
2178 rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask);
2179 }
2180
2181
2182 pdmpriv->INIDATA_RATE[mac_id] = psta->init_rate;
2183 DBG_871X("%s(): mac_id =%d raid = 0x%x bw =%d mask = 0x%x init_rate = 0x%x\n", __func__, mac_id, psta->raid, psta->bw_mode, mask, psta->init_rate);
2184}
2185
2186
2187void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc)
2188{
2189 pHalFunc->free_hal_data = &rtl8723b_free_hal_data;
2190
2191 pHalFunc->dm_init = &rtl8723b_init_dm_priv;
2192
2193 pHalFunc->read_chip_version = &rtl8723b_read_chip_version;
2194
2195 pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8723B;
2196
2197 pHalFunc->set_bwmode_handler = &PHY_SetBWMode8723B;
2198 pHalFunc->set_channel_handler = &PHY_SwChnl8723B;
2199 pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8723B;
2200
2201 pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8723B;
2202 pHalFunc->get_tx_power_level_handler = &PHY_GetTxPowerLevel8723B;
2203
2204 pHalFunc->hal_dm_watchdog = &rtl8723b_HalDmWatchDog;
2205 pHalFunc->hal_dm_watchdog_in_lps = &rtl8723b_HalDmWatchDog_in_LPS;
2206
2207
2208 pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8723b_SetBeaconRelatedRegisters;
2209
2210 pHalFunc->Add_RateATid = &rtl8723b_Add_RateATid;
2211
2212 pHalFunc->run_thread = &rtl8723b_start_thread;
2213 pHalFunc->cancel_thread = &rtl8723b_stop_thread;
2214
2215 pHalFunc->read_bbreg = &PHY_QueryBBReg_8723B;
2216 pHalFunc->write_bbreg = &PHY_SetBBReg_8723B;
2217 pHalFunc->read_rfreg = &PHY_QueryRFReg_8723B;
2218 pHalFunc->write_rfreg = &PHY_SetRFReg_8723B;
2219
2220
2221 pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch;
2222 pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch;
2223 pHalFunc->ReadEFuse = &Hal_ReadEFuse;
2224 pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition;
2225 pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize;
2226 pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead;
2227 pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite;
2228 pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite;
2229 pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT;
2230
2231 pHalFunc->GetHalODMVarHandler = &rtl8723b_GetHalODMVar;
2232 pHalFunc->SetHalODMVarHandler = &rtl8723b_SetHalODMVar;
2233
2234 pHalFunc->xmit_thread_handler = &hal_xmit_handler;
2235 pHalFunc->hal_notch_filter = &hal_notch_filter_8723b;
2236
2237 pHalFunc->c2h_handler = c2h_handler_8723b;
2238 pHalFunc->c2h_id_filter_ccx = c2h_id_filter_ccx_8723b;
2239
2240 pHalFunc->fill_h2c_cmd = &FillH2CCmd8723B;
2241}
2242
2243void rtl8723b_InitAntenna_Selection(struct adapter *padapter)
2244{
2245 struct hal_com_data *pHalData;
2246 u8 val;
2247
2248
2249 pHalData = GET_HAL_DATA(padapter);
2250
2251 val = rtw_read8(padapter, REG_LEDCFG2);
2252
2253 val |= BIT(7);
2254 rtw_write8(padapter, REG_LEDCFG2, val);
2255}
2256
2257void rtl8723b_init_default_value(struct adapter *padapter)
2258{
2259 struct hal_com_data *pHalData;
2260 struct dm_priv *pdmpriv;
2261 u8 i;
2262
2263
2264 pHalData = GET_HAL_DATA(padapter);
2265 pdmpriv = &pHalData->dmpriv;
2266
2267 padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N;
2268
2269
2270 pHalData->fw_ractrl = false;
2271 pHalData->bIQKInitialized = false;
2272 if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
2273 pHalData->LastHMEBoxNum = 0;
2274
2275 pHalData->bIQKInitialized = false;
2276
2277
2278 pdmpriv->TM_Trigger = 0;
2279
2280
2281
2282
2283 pdmpriv->ThermalValue_HP_index = 0;
2284 for (i = 0; i < HP_THERMAL_NUM; i++)
2285 pdmpriv->ThermalValue_HP[i] = 0;
2286
2287
2288 pHalData->EfuseUsedBytes = 0;
2289 pHalData->EfuseUsedPercentage = 0;
2290#ifdef HAL_EFUSE_MEMORY
2291 pHalData->EfuseHal.fakeEfuseBank = 0;
2292 pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
2293 memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
2294 memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
2295 memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
2296 pHalData->EfuseHal.BTEfuseUsedBytes = 0;
2297 pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
2298 memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
2299 memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2300 memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2301 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
2302 memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
2303 memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2304 memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
2305#endif
2306}
2307
2308u8 GetEEPROMSize8723B(struct adapter *padapter)
2309{
2310 u8 size = 0;
2311 u32 cr;
2312
2313 cr = rtw_read16(padapter, REG_9346CR);
2314
2315 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
2316
2317 MSG_8192C("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
2318
2319 return size;
2320}
2321
2322
2323
2324
2325
2326
2327s32 rtl8723b_InitLLTTable(struct adapter *padapter)
2328{
2329 unsigned long start, passing_time;
2330 u32 val32;
2331 s32 ret;
2332
2333
2334 ret = _FAIL;
2335
2336 val32 = rtw_read32(padapter, REG_AUTO_LLT);
2337 val32 |= BIT_AUTO_INIT_LLT;
2338 rtw_write32(padapter, REG_AUTO_LLT, val32);
2339
2340 start = jiffies;
2341
2342 do {
2343 val32 = rtw_read32(padapter, REG_AUTO_LLT);
2344 if (!(val32 & BIT_AUTO_INIT_LLT)) {
2345 ret = _SUCCESS;
2346 break;
2347 }
2348
2349 passing_time = jiffies_to_msecs(jiffies - start);
2350 if (passing_time > 1000) {
2351 DBG_8192C(
2352 "%s: FAIL!! REG_AUTO_LLT(0x%X) =%08x\n",
2353 __func__,
2354 REG_AUTO_LLT,
2355 val32
2356 );
2357 break;
2358 }
2359
2360 msleep(1);
2361 } while (1);
2362
2363 return ret;
2364}
2365
2366static bool Hal_GetChnlGroup8723B(u8 Channel, u8 *pGroup)
2367{
2368 bool bIn24G = true;
2369
2370 if (Channel <= 14) {
2371 bIn24G = true;
2372
2373 if (1 <= Channel && Channel <= 2)
2374 *pGroup = 0;
2375 else if (3 <= Channel && Channel <= 5)
2376 *pGroup = 1;
2377 else if (6 <= Channel && Channel <= 8)
2378 *pGroup = 2;
2379 else if (9 <= Channel && Channel <= 11)
2380 *pGroup = 3;
2381 else if (12 <= Channel && Channel <= 14)
2382 *pGroup = 4;
2383 else {
2384 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 2.4 G, but Channel %d in Group not found\n", Channel));
2385 }
2386 } else {
2387 bIn24G = false;
2388
2389 if (36 <= Channel && Channel <= 42)
2390 *pGroup = 0;
2391 else if (44 <= Channel && Channel <= 48)
2392 *pGroup = 1;
2393 else if (50 <= Channel && Channel <= 58)
2394 *pGroup = 2;
2395 else if (60 <= Channel && Channel <= 64)
2396 *pGroup = 3;
2397 else if (100 <= Channel && Channel <= 106)
2398 *pGroup = 4;
2399 else if (108 <= Channel && Channel <= 114)
2400 *pGroup = 5;
2401 else if (116 <= Channel && Channel <= 122)
2402 *pGroup = 6;
2403 else if (124 <= Channel && Channel <= 130)
2404 *pGroup = 7;
2405 else if (132 <= Channel && Channel <= 138)
2406 *pGroup = 8;
2407 else if (140 <= Channel && Channel <= 144)
2408 *pGroup = 9;
2409 else if (149 <= Channel && Channel <= 155)
2410 *pGroup = 10;
2411 else if (157 <= Channel && Channel <= 161)
2412 *pGroup = 11;
2413 else if (165 <= Channel && Channel <= 171)
2414 *pGroup = 12;
2415 else if (173 <= Channel && Channel <= 177)
2416 *pGroup = 13;
2417 else {
2418 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 5G, but Channel %d in Group not found\n", Channel));
2419 }
2420
2421 }
2422 RT_TRACE(
2423 _module_hci_hal_init_c_,
2424 _drv_info_,
2425 (
2426 "<==Hal_GetChnlGroup8723B, (%s) Channel = %d, Group =%d,\n",
2427 bIn24G ? "2.4G" : "5G",
2428 Channel,
2429 *pGroup
2430 )
2431 );
2432 return bIn24G;
2433}
2434
2435void Hal_InitPGData(struct adapter *padapter, u8 *PROMContent)
2436{
2437 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2438
2439 if (false == pEEPROM->bautoload_fail_flag) {
2440 if (!pEEPROM->EepromOrEfuse) {
2441
2442 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
2443 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
2444 }
2445 } else {
2446 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
2447 if (false == pEEPROM->EepromOrEfuse)
2448 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
2449 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
2450 }
2451}
2452
2453void Hal_EfuseParseIDCode(struct adapter *padapter, u8 *hwinfo)
2454{
2455 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2456
2457 u16 EEPROMId;
2458
2459
2460
2461 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
2462 if (EEPROMId != RTL_EEPROM_ID) {
2463 DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
2464 pEEPROM->bautoload_fail_flag = true;
2465 } else
2466 pEEPROM->bautoload_fail_flag = false;
2467
2468 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("EEPROM ID = 0x%04x\n", EEPROMId));
2469}
2470
2471static void Hal_ReadPowerValueFromPROM_8723B(
2472 struct adapter *Adapter,
2473 struct TxPowerInfo24G *pwrInfo24G,
2474 u8 *PROMContent,
2475 bool AutoLoadFail
2476)
2477{
2478 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
2479 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_8723B, group, TxCount = 0;
2480
2481 memset(pwrInfo24G, 0, sizeof(struct TxPowerInfo24G));
2482
2483 if (0xFF == PROMContent[eeAddr+1])
2484 AutoLoadFail = true;
2485
2486 if (AutoLoadFail) {
2487 DBG_871X("%s(): Use Default value!\n", __func__);
2488 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
2489
2490 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
2491 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2492 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2493 }
2494
2495 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2496 if (TxCount == 0) {
2497 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
2498 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2499 } else {
2500 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2501 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2502 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2503 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2504 }
2505 }
2506 }
2507
2508 return;
2509 }
2510
2511 pHalData->bTXPowerDataReadFromEEPORM = true;
2512
2513 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
2514
2515 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
2516 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
2517 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
2518 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2519 }
2520
2521 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
2522 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
2523 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
2524 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
2525 }
2526
2527 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2528 if (TxCount == 0) {
2529 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
2530 if (PROMContent[eeAddr] == 0xFF)
2531 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
2532 else {
2533 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2534 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3)
2535 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2536 }
2537
2538 if (PROMContent[eeAddr] == 0xFF)
2539 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
2540 else {
2541 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2542 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3)
2543 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2544 }
2545 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
2546 eeAddr++;
2547 } else {
2548 if (PROMContent[eeAddr] == 0xFF)
2549 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2550 else {
2551 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2552 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3)
2553 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
2554 }
2555
2556 if (PROMContent[eeAddr] == 0xFF)
2557 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2558 else {
2559 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2560 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3)
2561 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
2562 }
2563 eeAddr++;
2564
2565 if (PROMContent[eeAddr] == 0xFF)
2566 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2567 else {
2568 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
2569 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3)
2570 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
2571 }
2572
2573 if (PROMContent[eeAddr] == 0xFF)
2574 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
2575 else {
2576 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
2577 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3)
2578 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
2579 }
2580 eeAddr++;
2581 }
2582 }
2583 }
2584}
2585
2586
2587void Hal_EfuseParseTxPowerInfo_8723B(
2588 struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail
2589)
2590{
2591 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2592 struct TxPowerInfo24G pwrInfo24G;
2593 u8 rfPath, ch, TxCount = 1;
2594
2595 Hal_ReadPowerValueFromPROM_8723B(padapter, &pwrInfo24G, PROMContent, AutoLoadFail);
2596 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2597 for (ch = 0 ; ch < CHANNEL_MAX_NUMBER; ch++) {
2598 u8 group = 0;
2599
2600 Hal_GetChnlGroup8723B(ch+1, &group);
2601
2602 if (ch == 14-1) {
2603 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][5];
2604 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
2605 } else {
2606 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
2607 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
2608 }
2609#ifdef DEBUG
2610 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======= Path %d, ChannelIndex %d, Group %d =======\n", rfPath, ch, group));
2611 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_CCK_Base[rfPath][ch]));
2612 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch]));
2613#endif
2614 }
2615
2616 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2617 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
2618 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
2619 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
2620 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
2621
2622#ifdef DEBUG
2623 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("--------------------------------------- 2.4G ---------------------------------------\n"));
2624 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CCK_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount]));
2625 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("OFDM_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount]));
2626 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW20_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount]));
2627 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW40_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount]));
2628#endif
2629 }
2630 }
2631
2632
2633 if (!AutoLoadFail) {
2634 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8723B]&0x7);
2635 if (PROMContent[EEPROM_RF_BOARD_OPTION_8723B] == 0xFF)
2636 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7);
2637 } else
2638 pHalData->EEPROMRegulatory = 0;
2639
2640 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory));
2641}
2642
2643void Hal_EfuseParseBTCoexistInfo_8723B(
2644 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2645)
2646{
2647 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2648 u8 tempval;
2649 u32 tmpu4;
2650
2651 if (!AutoLoadFail) {
2652 tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
2653 if (tmpu4 & BT_FUNC_EN)
2654 pHalData->EEPROMBluetoothCoexist = true;
2655 else
2656 pHalData->EEPROMBluetoothCoexist = false;
2657
2658 pHalData->EEPROMBluetoothType = BT_RTL8723B;
2659
2660 tempval = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2661 if (tempval != 0xFF) {
2662 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0);
2663
2664
2665 pHalData->ant_path = (tempval & BIT(6))?ODM_RF_PATH_B:ODM_RF_PATH_A;
2666 } else {
2667 pHalData->EEPROMBluetoothAntNum = Ant_x1;
2668 if (pHalData->PackageType == PACKAGE_QFN68)
2669 pHalData->ant_path = ODM_RF_PATH_B;
2670 else
2671 pHalData->ant_path = ODM_RF_PATH_A;
2672 }
2673 } else {
2674 pHalData->EEPROMBluetoothCoexist = false;
2675 pHalData->EEPROMBluetoothType = BT_RTL8723B;
2676 pHalData->EEPROMBluetoothAntNum = Ant_x1;
2677 pHalData->ant_path = ODM_RF_PATH_A;
2678 }
2679
2680 if (padapter->registrypriv.ant_num > 0) {
2681 DBG_8192C(
2682 "%s: Apply driver defined antenna number(%d) to replace origin(%d)\n",
2683 __func__,
2684 padapter->registrypriv.ant_num,
2685 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1
2686 );
2687
2688 switch (padapter->registrypriv.ant_num) {
2689 case 1:
2690 pHalData->EEPROMBluetoothAntNum = Ant_x1;
2691 break;
2692 case 2:
2693 pHalData->EEPROMBluetoothAntNum = Ant_x2;
2694 break;
2695 default:
2696 DBG_8192C(
2697 "%s: Discard invalid driver defined antenna number(%d)!\n",
2698 __func__,
2699 padapter->registrypriv.ant_num
2700 );
2701 break;
2702 }
2703 }
2704
2705 rtw_btcoex_SetBTCoexist(padapter, pHalData->EEPROMBluetoothCoexist);
2706 rtw_btcoex_SetChipType(padapter, pHalData->EEPROMBluetoothType);
2707 rtw_btcoex_SetPGAntNum(padapter, pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
2708 if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
2709 rtw_btcoex_SetSingleAntPath(padapter, pHalData->ant_path);
2710
2711 DBG_8192C(
2712 "%s: %s BT-coex, ant_num =%d\n",
2713 __func__,
2714 pHalData->EEPROMBluetoothCoexist == true ? "Enable" : "Disable",
2715 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1
2716 );
2717}
2718
2719void Hal_EfuseParseEEPROMVer_8723B(
2720 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2721)
2722{
2723 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2724
2725
2726 if (!AutoLoadFail)
2727 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723B];
2728 else
2729 pHalData->EEPROMVersion = 1;
2730 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
2731 pHalData->EEPROMVersion));
2732}
2733
2734
2735
2736void Hal_EfuseParsePackageType_8723B(
2737 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2738)
2739{
2740 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2741 u8 package;
2742 u8 efuseContent;
2743
2744 Efuse_PowerSwitch(padapter, false, true);
2745 efuse_OneByteRead(padapter, 0x1FB, &efuseContent, false);
2746 DBG_871X("%s phy efuse read 0x1FB =%x\n", __func__, efuseContent);
2747 Efuse_PowerSwitch(padapter, false, false);
2748
2749 package = efuseContent & 0x7;
2750 switch (package) {
2751 case 0x4:
2752 pHalData->PackageType = PACKAGE_TFBGA79;
2753 break;
2754 case 0x5:
2755 pHalData->PackageType = PACKAGE_TFBGA90;
2756 break;
2757 case 0x6:
2758 pHalData->PackageType = PACKAGE_QFN68;
2759 break;
2760 case 0x7:
2761 pHalData->PackageType = PACKAGE_TFBGA80;
2762 break;
2763
2764 default:
2765 pHalData->PackageType = PACKAGE_DEFAULT;
2766 break;
2767 }
2768
2769 DBG_871X("PackageType = 0x%X\n", pHalData->PackageType);
2770}
2771
2772
2773void Hal_EfuseParseVoltage_8723B(
2774 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2775)
2776{
2777 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2778
2779
2780 DBG_871X("%s hwinfo[EEPROM_Voltage_ADDR_8723B] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8723B]);
2781 pEEPROM->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8723B] & 0xf0) >> 4;
2782 DBG_871X("%s pEEPROM->adjuseVoltageVal =%x\n", __func__, pEEPROM->adjuseVoltageVal);
2783}
2784
2785void Hal_EfuseParseChnlPlan_8723B(
2786 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2787)
2788{
2789 padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan(
2790 padapter,
2791 hwinfo ? hwinfo[EEPROM_ChannelPlan_8723B] : 0xFF,
2792 padapter->registrypriv.channel_plan,
2793 RT_CHANNEL_DOMAIN_WORLD_NULL,
2794 AutoLoadFail
2795 );
2796
2797 Hal_ChannelPlanToRegulation(padapter, padapter->mlmepriv.ChannelPlan);
2798
2799 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan));
2800}
2801
2802void Hal_EfuseParseCustomerID_8723B(
2803 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2804)
2805{
2806 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2807
2808
2809 if (!AutoLoadFail)
2810 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723B];
2811 else
2812 pHalData->EEPROMCustomerID = 0;
2813
2814 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID));
2815}
2816
2817void Hal_EfuseParseAntennaDiversity_8723B(
2818 struct adapter *padapter,
2819 u8 *hwinfo,
2820 bool AutoLoadFail
2821)
2822{
2823}
2824
2825void Hal_EfuseParseXtal_8723B(
2826 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
2827)
2828{
2829 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2830
2831
2832 if (!AutoLoadFail) {
2833 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_8723B];
2834 if (pHalData->CrystalCap == 0xFF)
2835 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B;
2836 } else
2837 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B;
2838
2839 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM CrystalCap: 0x%2x\n", pHalData->CrystalCap));
2840}
2841
2842
2843void Hal_EfuseParseThermalMeter_8723B(
2844 struct adapter *padapter, u8 *PROMContent, u8 AutoLoadFail
2845)
2846{
2847 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2848
2849
2850
2851
2852
2853 if (false == AutoLoadFail)
2854 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_8723B];
2855 else
2856 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
2857
2858 if ((pHalData->EEPROMThermalMeter == 0xff) || (true == AutoLoadFail)) {
2859 pHalData->bAPKThermalMeterIgnore = true;
2860 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
2861 }
2862
2863 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
2864}
2865
2866
2867void Hal_ReadRFGainOffset(
2868 struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail
2869)
2870{
2871
2872
2873
2874
2875 if (!AutoloadFail) {
2876 Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET];
2877 DBG_871X("AutoloadFail =%x,\n", AutoloadFail);
2878 Adapter->eeprompriv.EEPROMRFGainVal = EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL);
2879 DBG_871X("Adapter->eeprompriv.EEPROMRFGainVal =%x\n", Adapter->eeprompriv.EEPROMRFGainVal);
2880 } else {
2881 Adapter->eeprompriv.EEPROMRFGainOffset = 0;
2882 Adapter->eeprompriv.EEPROMRFGainVal = 0xFF;
2883 DBG_871X("else AutoloadFail =%x,\n", AutoloadFail);
2884 }
2885 DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset);
2886}
2887
2888u8 BWMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
2889{
2890 u8 BWSettingOfDesc = 0;
2891 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
2892
2893
2894
2895 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
2896 if (pattrib->bwmode == CHANNEL_WIDTH_80)
2897 BWSettingOfDesc = 2;
2898 else if (pattrib->bwmode == CHANNEL_WIDTH_40)
2899 BWSettingOfDesc = 1;
2900 else
2901 BWSettingOfDesc = 0;
2902 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
2903 if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
2904 BWSettingOfDesc = 1;
2905 else
2906 BWSettingOfDesc = 0;
2907 } else
2908 BWSettingOfDesc = 0;
2909
2910
2911
2912
2913 return BWSettingOfDesc;
2914}
2915
2916u8 SCMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
2917{
2918 u8 SCSettingOfDesc = 0;
2919 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
2920
2921
2922
2923 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
2924 if (pattrib->bwmode == CHANNEL_WIDTH_80) {
2925 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2926 } else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
2927 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
2928 SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
2929 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
2930 SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
2931 else
2932 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n");
2933 } else {
2934 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
2935 SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
2936 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
2937 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2938 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
2939 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2940 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
2941 SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
2942 else
2943 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n");
2944 }
2945 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
2946
2947
2948 if (pattrib->bwmode == CHANNEL_WIDTH_40) {
2949 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2950 } else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
2951 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) {
2952 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2953 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) {
2954 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2955 } else {
2956 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2957 }
2958 }
2959 } else {
2960 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
2961 }
2962
2963 return SCSettingOfDesc;
2964}
2965
2966static void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc)
2967{
2968 u16 *usPtr = (u16 *)ptxdesc;
2969 u32 count;
2970 u32 index;
2971 u16 checksum = 0;
2972
2973
2974
2975 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
2976
2977
2978
2979
2980 count = 16;
2981
2982 for (index = 0; index < count; index++) {
2983 checksum |= le16_to_cpu(*(__le16 *)(usPtr + index));
2984 }
2985
2986 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
2987}
2988
2989static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
2990{
2991 u8 sectype = 0;
2992 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
2993 switch (pattrib->encrypt) {
2994
2995 case _WEP40_:
2996 case _WEP104_:
2997 case _TKIP_:
2998 case _TKIP_WTMIC_:
2999 sectype = 1;
3000 break;
3001
3002 case _AES_:
3003 sectype = 3;
3004 break;
3005
3006 case _NO_PRIVACY_:
3007 default:
3008 break;
3009 }
3010 }
3011 return sectype;
3012}
3013
3014static void fill_txdesc_vcs_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc)
3015{
3016
3017
3018 if (pattrib->vcs_mode) {
3019 switch (pattrib->vcs_mode) {
3020 case RTS_CTS:
3021 ptxdesc->rtsen = 1;
3022
3023 ptxdesc->hw_rts_en = 1;
3024 break;
3025
3026 case CTS_TO_SELF:
3027 ptxdesc->cts2self = 1;
3028 break;
3029
3030 case NONE_VCS:
3031 default:
3032 break;
3033 }
3034
3035 ptxdesc->rtsrate = 8;
3036 ptxdesc->rts_ratefb_lmt = 0xF;
3037
3038 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
3039 ptxdesc->rts_short = 1;
3040
3041
3042 if (pattrib->ht_en)
3043 ptxdesc->rts_sc = SCMapping_8723B(padapter, pattrib);
3044 }
3045}
3046
3047static void fill_txdesc_phy_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc)
3048{
3049
3050
3051 if (pattrib->ht_en) {
3052 ptxdesc->data_bw = BWMapping_8723B(padapter, pattrib);
3053
3054 ptxdesc->data_sc = SCMapping_8723B(padapter, pattrib);
3055 }
3056}
3057
3058static void rtl8723b_fill_default_txdesc(
3059 struct xmit_frame *pxmitframe, u8 *pbuf
3060)
3061{
3062 struct adapter *padapter;
3063 struct hal_com_data *pHalData;
3064 struct dm_priv *pdmpriv;
3065 struct mlme_ext_priv *pmlmeext;
3066 struct mlme_ext_info *pmlmeinfo;
3067 struct pkt_attrib *pattrib;
3068 PTXDESC_8723B ptxdesc;
3069 s32 bmcst;
3070
3071 memset(pbuf, 0, TXDESC_SIZE);
3072
3073 padapter = pxmitframe->padapter;
3074 pHalData = GET_HAL_DATA(padapter);
3075 pdmpriv = &pHalData->dmpriv;
3076 pmlmeext = &padapter->mlmeextpriv;
3077 pmlmeinfo = &(pmlmeext->mlmext_info);
3078
3079 pattrib = &pxmitframe->attrib;
3080 bmcst = IS_MCAST(pattrib->ra);
3081
3082 ptxdesc = (PTXDESC_8723B)pbuf;
3083
3084 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
3085 u8 drv_userate = 0;
3086
3087 ptxdesc->macid = pattrib->mac_id;
3088 ptxdesc->rate_id = pattrib->raid;
3089 ptxdesc->qsel = pattrib->qsel;
3090 ptxdesc->seq = pattrib->seqnum;
3091
3092 ptxdesc->sectype = fill_txdesc_sectype(pattrib);
3093 fill_txdesc_vcs_8723b(padapter, pattrib, ptxdesc);
3094
3095 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
3096 drv_userate = 1;
3097
3098 if (
3099 (pattrib->ether_type != 0x888e) &&
3100 (pattrib->ether_type != 0x0806) &&
3101 (pattrib->ether_type != 0x88B4) &&
3102 (pattrib->dhcp_pkt != 1) &&
3103 (drv_userate != 1)
3104#ifdef CONFIG_AUTO_AP_MODE
3105 && (pattrib->pctrl != true)
3106#endif
3107 ) {
3108
3109
3110 if (pattrib->ampdu_en == true) {
3111 ptxdesc->agg_en = 1;
3112 ptxdesc->max_agg_num = 0x1f;
3113 ptxdesc->ampdu_density = pattrib->ampdu_spacing;
3114 } else
3115 ptxdesc->bk = 1;
3116
3117 fill_txdesc_phy_8723b(padapter, pattrib, ptxdesc);
3118
3119 ptxdesc->data_ratefb_lmt = 0x1F;
3120
3121 if (pHalData->fw_ractrl == false) {
3122 ptxdesc->userate = 1;
3123
3124 if (pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & BIT(7))
3125 ptxdesc->data_short = 1;
3126
3127 ptxdesc->datarate = pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & 0x7F;
3128 }
3129
3130 if (padapter->fix_rate != 0xFF) {
3131 ptxdesc->userate = 1;
3132 if (padapter->fix_rate & BIT(7))
3133 ptxdesc->data_short = 1;
3134
3135 ptxdesc->datarate = (padapter->fix_rate & 0x7F);
3136 ptxdesc->disdatafb = 1;
3137 }
3138
3139 if (pattrib->ldpc)
3140 ptxdesc->data_ldpc = 1;
3141 if (pattrib->stbc)
3142 ptxdesc->data_stbc = 1;
3143
3144#ifdef CONFIG_CMCC_TEST
3145 ptxdesc->data_short = 1;
3146#endif
3147 } else {
3148
3149
3150
3151
3152 ptxdesc->bk = 1;
3153 ptxdesc->userate = 1;
3154 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
3155 ptxdesc->data_short = 1;
3156 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
3157 DBG_871X("YJ: %s(): ARP Data: userate =%d, datarate = 0x%x\n", __func__, ptxdesc->userate, ptxdesc->datarate);
3158 }
3159
3160 ptxdesc->usb_txagg_num = pxmitframe->agg_num;
3161 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
3162
3163
3164 ptxdesc->macid = pattrib->mac_id;
3165 ptxdesc->qsel = pattrib->qsel;
3166 ptxdesc->rate_id = pattrib->raid;
3167 ptxdesc->seq = pattrib->seqnum;
3168 ptxdesc->userate = 1;
3169
3170 ptxdesc->mbssid = pattrib->mbssid & 0xF;
3171
3172 ptxdesc->rty_lmt_en = 1;
3173 if (pattrib->retry_ctrl == true) {
3174 ptxdesc->data_rt_lmt = 6;
3175 } else {
3176 ptxdesc->data_rt_lmt = 12;
3177 }
3178
3179 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
3180
3181
3182 if (pxmitframe->ack_report) {
3183 #ifdef DBG_CCX
3184 DBG_8192C("%s set spe_rpt\n", __func__);
3185 #endif
3186 ptxdesc->spe_rpt = 1;
3187 ptxdesc->sw_define = (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no);
3188 }
3189 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
3190 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: TXAGG_FRAMETAG\n", __func__));
3191 } else {
3192 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: frame_tag = 0x%x\n", __func__, pxmitframe->frame_tag));
3193
3194 ptxdesc->macid = pattrib->mac_id;
3195 ptxdesc->rate_id = pattrib->raid;
3196 ptxdesc->qsel = pattrib->qsel;
3197 ptxdesc->seq = pattrib->seqnum;
3198 ptxdesc->userate = 1;
3199 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
3200 }
3201
3202 ptxdesc->pktlen = pattrib->last_txcmdsz;
3203 ptxdesc->offset = TXDESC_SIZE + OFFSET_SZ;
3204
3205 if (bmcst)
3206 ptxdesc->bmc = 1;
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216 if (!pattrib->qos_en)
3217 ptxdesc->en_hwseq = 1;
3218}
3219
3220
3221
3222
3223
3224
3225
3226
3227void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
3228{
3229 struct tx_desc *pdesc;
3230
3231 rtl8723b_fill_default_txdesc(pxmitframe, pbuf);
3232
3233 pdesc = (struct tx_desc *)pbuf;
3234 pdesc->txdw0 = pdesc->txdw0;
3235 pdesc->txdw1 = pdesc->txdw1;
3236 pdesc->txdw2 = pdesc->txdw2;
3237 pdesc->txdw3 = pdesc->txdw3;
3238 pdesc->txdw4 = pdesc->txdw4;
3239 pdesc->txdw5 = pdesc->txdw5;
3240 pdesc->txdw6 = pdesc->txdw6;
3241 pdesc->txdw7 = pdesc->txdw7;
3242 pdesc->txdw8 = pdesc->txdw8;
3243 pdesc->txdw9 = pdesc->txdw9;
3244
3245 rtl8723b_cal_txdesc_chksum(pdesc);
3246}
3247
3248
3249
3250
3251
3252
3253
3254
3255void rtl8723b_fill_fake_txdesc(
3256 struct adapter *padapter,
3257 u8 *pDesc,
3258 u32 BufferLen,
3259 u8 IsPsPoll,
3260 u8 IsBTQosNull,
3261 u8 bDataFrame
3262)
3263{
3264
3265 memset(pDesc, 0, TXDESC_SIZE);
3266
3267 SET_TX_DESC_FIRST_SEG_8723B(pDesc, 1);
3268 SET_TX_DESC_LAST_SEG_8723B(pDesc, 1);
3269
3270 SET_TX_DESC_OFFSET_8723B(pDesc, 0x28);
3271
3272 SET_TX_DESC_PKT_SIZE_8723B(pDesc, BufferLen);
3273 SET_TX_DESC_QUEUE_SEL_8723B(pDesc, QSLT_MGNT);
3274
3275
3276 if (true == IsPsPoll) {
3277 SET_TX_DESC_NAV_USE_HDR_8723B(pDesc, 1);
3278 } else {
3279 SET_TX_DESC_HWSEQ_EN_8723B(pDesc, 1);
3280 SET_TX_DESC_HWSEQ_SEL_8723B(pDesc, 0);
3281 }
3282
3283 if (true == IsBTQosNull) {
3284 SET_TX_DESC_BT_INT_8723B(pDesc, 1);
3285 }
3286
3287 SET_TX_DESC_USE_RATE_8723B(pDesc, 1);
3288 SET_TX_DESC_OWN_8723B((u8 *)pDesc, 1);
3289
3290 SET_TX_DESC_TX_RATE_8723B(pDesc, DESC8723B_RATE1M);
3291
3292
3293
3294
3295 if (true == bDataFrame) {
3296 u32 EncAlg;
3297
3298 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
3299 switch (EncAlg) {
3300 case _NO_PRIVACY_:
3301 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
3302 break;
3303 case _WEP40_:
3304 case _WEP104_:
3305 case _TKIP_:
3306 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x1);
3307 break;
3308 case _SMS4_:
3309 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x2);
3310 break;
3311 case _AES_:
3312 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x3);
3313 break;
3314 default:
3315 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
3316 break;
3317 }
3318 }
3319
3320
3321
3322 rtl8723b_cal_txdesc_chksum((struct tx_desc *)pDesc);
3323}
3324
3325static void hw_var_set_opmode(struct adapter *padapter, u8 variable, u8 *val)
3326{
3327 u8 val8;
3328 u8 mode = *((u8 *)val);
3329
3330 {
3331
3332 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3333 val8 |= DIS_TSF_UDT;
3334 rtw_write8(padapter, REG_BCN_CTRL, val8);
3335
3336
3337 Set_MSR(padapter, mode);
3338 DBG_871X("#### %s() -%d iface_type(0) mode = %d ####\n", __func__, __LINE__, mode);
3339
3340 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
3341 {
3342 StopTxBeacon(padapter);
3343#ifdef CONFIG_INTERRUPT_BASED_TXBCN
3344#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3345 rtw_write8(padapter, REG_DRVERLYINT, 0x05);
3346 UpdateInterruptMask8812AU(padapter, true, 0, IMR_BCNDMAINT0_8723B);
3347#endif
3348
3349#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3350 UpdateInterruptMask8812AU(padapter, true, 0, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B));
3351#endif
3352
3353#endif
3354 }
3355
3356
3357 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_ATIM);
3358
3359 } else if ((mode == _HW_STATE_ADHOC_) ) {
3360 ResumeTxBeacon(padapter);
3361 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_BCNQ_SUB);
3362 } else if (mode == _HW_STATE_AP_) {
3363#ifdef CONFIG_INTERRUPT_BASED_TXBCN
3364#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3365 UpdateInterruptMask8723BU(padapter, true, IMR_BCNDMAINT0_8723B, 0);
3366#endif
3367
3368#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3369 UpdateInterruptMask8723BU(padapter, true, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B), 0);
3370#endif
3371
3372#endif
3373
3374 ResumeTxBeacon(padapter);
3375
3376 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|DIS_BCNQ_SUB);
3377
3378
3379 rtw_write32(padapter, REG_RCR, 0x7000208e);
3380
3381 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
3382
3383 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
3384
3385
3386 rtw_write8(padapter, REG_BCNDMATIM, 0x02);
3387
3388
3389 rtw_write8(padapter, REG_ATIMWND, 0x0a);
3390 rtw_write16(padapter, REG_BCNTCFG, 0x00);
3391 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
3392 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
3393
3394
3395 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
3396
3397
3398
3399 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT|EN_BCN_FUNCTION|EN_TXBCN_RPT|DIS_BCNQ_SUB));
3400
3401
3402
3403 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
3404
3405
3406 rtw_write8(
3407 padapter,
3408 REG_CCK_CHECK_8723B,
3409 (rtw_read8(padapter, REG_CCK_CHECK_8723B)&~BIT_BCN_PORT_SEL)
3410 );
3411
3412
3413 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
3414 val8 |= DIS_ATIM;
3415 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
3416 }
3417 }
3418}
3419
3420static void hw_var_set_macaddr(struct adapter *padapter, u8 variable, u8 *val)
3421{
3422 u8 idx = 0;
3423 u32 reg_macid;
3424
3425 reg_macid = REG_MACID;
3426
3427 for (idx = 0 ; idx < 6; idx++)
3428 rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid+idx), val[idx]);
3429}
3430
3431static void hw_var_set_bssid(struct adapter *padapter, u8 variable, u8 *val)
3432{
3433 u8 idx = 0;
3434 u32 reg_bssid;
3435
3436 reg_bssid = REG_BSSID;
3437
3438 for (idx = 0 ; idx < 6; idx++)
3439 rtw_write8(padapter, (reg_bssid+idx), val[idx]);
3440}
3441
3442static void hw_var_set_bcn_func(struct adapter *padapter, u8 variable, u8 *val)
3443{
3444 u32 bcn_ctrl_reg;
3445
3446 bcn_ctrl_reg = REG_BCN_CTRL;
3447
3448 if (*(u8 *)val)
3449 rtw_write8(padapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
3450 else {
3451 u8 val8;
3452 val8 = rtw_read8(padapter, bcn_ctrl_reg);
3453 val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);
3454
3455
3456 if (REG_BCN_CTRL == bcn_ctrl_reg)
3457 val8 |= EN_BCN_FUNCTION;
3458
3459 rtw_write8(padapter, bcn_ctrl_reg, val8);
3460 }
3461}
3462
3463static void hw_var_set_correct_tsf(struct adapter *padapter, u8 variable, u8 *val)
3464{
3465 u8 val8;
3466 u64 tsf;
3467 struct mlme_ext_priv *pmlmeext;
3468 struct mlme_ext_info *pmlmeinfo;
3469
3470
3471 pmlmeext = &padapter->mlmeextpriv;
3472 pmlmeinfo = &pmlmeext->mlmext_info;
3473
3474 tsf = pmlmeext->TSFValue-rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024))-1024;
3475
3476 if (
3477 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
3478 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
3479 )
3480 StopTxBeacon(padapter);
3481
3482 {
3483
3484 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3485 val8 &= ~EN_BCN_FUNCTION;
3486 rtw_write8(padapter, REG_BCN_CTRL, val8);
3487
3488 rtw_write32(padapter, REG_TSFTR, tsf);
3489 rtw_write32(padapter, REG_TSFTR+4, tsf>>32);
3490
3491
3492 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3493 val8 |= EN_BCN_FUNCTION;
3494 rtw_write8(padapter, REG_BCN_CTRL, val8);
3495 }
3496
3497 if (
3498 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
3499 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
3500 )
3501 ResumeTxBeacon(padapter);
3502}
3503
3504static void hw_var_set_mlme_disconnect(struct adapter *padapter, u8 variable, u8 *val)
3505{
3506 u8 val8;
3507
3508
3509
3510
3511 rtw_write16(padapter, REG_RXFLTMAP2, 0);
3512
3513
3514 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
3515
3516
3517 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3518 val8 |= DIS_TSF_UDT;
3519 rtw_write8(padapter, REG_BCN_CTRL, val8);
3520}
3521
3522static void hw_var_set_mlme_sitesurvey(struct adapter *padapter, u8 variable, u8 *val)
3523{
3524 u32 value_rcr, rcr_clear_bit, reg_bcn_ctl;
3525 u16 value_rxfltmap2;
3526 u8 val8;
3527 struct hal_com_data *pHalData;
3528 struct mlme_priv *pmlmepriv;
3529
3530
3531 pHalData = GET_HAL_DATA(padapter);
3532 pmlmepriv = &padapter->mlmepriv;
3533
3534 reg_bcn_ctl = REG_BCN_CTRL;
3535
3536 rcr_clear_bit = RCR_CBSSID_BCN;
3537
3538
3539 value_rxfltmap2 = 0;
3540
3541 if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == true))
3542 rcr_clear_bit = RCR_CBSSID_BCN;
3543
3544 value_rcr = rtw_read32(padapter, REG_RCR);
3545
3546 if (*((u8 *)val)) {
3547
3548 value_rcr &= ~(rcr_clear_bit);
3549 rtw_write32(padapter, REG_RCR, value_rcr);
3550
3551 rtw_write16(padapter, REG_RXFLTMAP2, value_rxfltmap2);
3552
3553 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
3554
3555 val8 = rtw_read8(padapter, reg_bcn_ctl);
3556 val8 |= DIS_TSF_UDT;
3557 rtw_write8(padapter, reg_bcn_ctl, val8);
3558 }
3559
3560
3561 pHalData->RegRRSR = rtw_read16(padapter, REG_RRSR);
3562 } else {
3563
3564 if (check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)))
3565
3566 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
3567
3568 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
3569
3570 val8 = rtw_read8(padapter, reg_bcn_ctl);
3571 val8 &= ~DIS_TSF_UDT;
3572 rtw_write8(padapter, reg_bcn_ctl, val8);
3573 }
3574
3575 value_rcr |= rcr_clear_bit;
3576 rtw_write32(padapter, REG_RCR, value_rcr);
3577
3578
3579 rtw_write16(padapter, REG_RRSR, pHalData->RegRRSR);
3580 }
3581}
3582
3583static void hw_var_set_mlme_join(struct adapter *padapter, u8 variable, u8 *val)
3584{
3585 u8 val8;
3586 u16 val16;
3587 u32 val32;
3588 u8 RetryLimit;
3589 u8 type;
3590 struct hal_com_data *pHalData;
3591 struct mlme_priv *pmlmepriv;
3592 struct eeprom_priv *pEEPROM;
3593
3594
3595 RetryLimit = 0x30;
3596 type = *(u8 *)val;
3597 pHalData = GET_HAL_DATA(padapter);
3598 pmlmepriv = &padapter->mlmepriv;
3599 pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
3600
3601 if (type == 0) {
3602
3603
3604 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
3605
3606 val32 = rtw_read32(padapter, REG_RCR);
3607 if (padapter->in_cta_test)
3608 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
3609 else
3610 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
3611 rtw_write32(padapter, REG_RCR, val32);
3612
3613 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
3614 RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48;
3615 else
3616 RetryLimit = 0x7;
3617 } else if (type == 1)
3618 rtw_write16(padapter, REG_RXFLTMAP2, 0x00);
3619 else if (type == 2) {
3620
3621 val8 = rtw_read8(padapter, REG_BCN_CTRL);
3622 val8 &= ~DIS_TSF_UDT;
3623 rtw_write8(padapter, REG_BCN_CTRL, val8);
3624
3625 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
3626 RetryLimit = 0x7;
3627 }
3628
3629 val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT);
3630 rtw_write16(padapter, REG_RL, val16);
3631}
3632
3633void CCX_FwC2HTxRpt_8723b(struct adapter *padapter, u8 *pdata, u8 len)
3634{
3635 u8 seq_no;
3636
3637#define GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
3638#define GET_8723B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
3639
3640
3641
3642
3643 seq_no = *(pdata+6);
3644
3645 if (GET_8723B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(pdata)) {
3646 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
3647 }
3648
3649
3650
3651
3652
3653
3654 else
3655 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
3656}
3657
3658s32 c2h_id_filter_ccx_8723b(u8 *buf)
3659{
3660 struct c2h_evt_hdr_88xx *c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
3661 s32 ret = false;
3662 if (c2h_evt->id == C2H_CCX_TX_RPT)
3663 ret = true;
3664
3665 return ret;
3666}
3667
3668
3669s32 c2h_handler_8723b(struct adapter *padapter, u8 *buf)
3670{
3671 struct c2h_evt_hdr_88xx *pC2hEvent = (struct c2h_evt_hdr_88xx *)buf;
3672 s32 ret = _SUCCESS;
3673 u8 index = 0;
3674
3675 if (pC2hEvent == NULL) {
3676 DBG_8192C("%s(): pC2hEventis NULL\n", __func__);
3677 ret = _FAIL;
3678 goto exit;
3679 }
3680
3681 switch (pC2hEvent->id) {
3682 case C2H_AP_RPT_RSP:
3683 break;
3684 case C2H_DBG:
3685 {
3686 RT_TRACE(_module_hal_init_c_, _drv_info_, ("c2h_handler_8723b: %s\n", pC2hEvent->payload));
3687 }
3688 break;
3689
3690 case C2H_CCX_TX_RPT:
3691
3692 break;
3693
3694 case C2H_EXT_RA_RPT:
3695
3696 break;
3697
3698 case C2H_HW_INFO_EXCH:
3699 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n"));
3700 for (index = 0; index < pC2hEvent->plen; index++) {
3701 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, pC2hEvent->payload[index]));
3702 }
3703 break;
3704
3705 case C2H_8723B_BT_INFO:
3706 rtw_btcoex_BtInfoNotify(padapter, pC2hEvent->plen, pC2hEvent->payload);
3707 break;
3708
3709 default:
3710 break;
3711 }
3712
3713
3714
3715
3716
3717exit:
3718 return ret;
3719}
3720
3721static void process_c2h_event(struct adapter *padapter, PC2H_EVT_HDR pC2hEvent, u8 *c2hBuf)
3722{
3723 u8 index = 0;
3724
3725 if (c2hBuf == NULL) {
3726 DBG_8192C("%s c2hbuff is NULL\n", __func__);
3727 return;
3728 }
3729
3730 switch (pC2hEvent->CmdID) {
3731 case C2H_AP_RPT_RSP:
3732 break;
3733 case C2H_DBG:
3734 {
3735 RT_TRACE(_module_hal_init_c_, _drv_info_, ("C2HCommandHandler: %s\n", c2hBuf));
3736 }
3737 break;
3738
3739 case C2H_CCX_TX_RPT:
3740
3741 break;
3742
3743 case C2H_EXT_RA_RPT:
3744
3745 break;
3746
3747 case C2H_HW_INFO_EXCH:
3748 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n"));
3749 for (index = 0; index < pC2hEvent->CmdLen; index++) {
3750 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, c2hBuf[index]));
3751 }
3752 break;
3753
3754 case C2H_8723B_BT_INFO:
3755 rtw_btcoex_BtInfoNotify(padapter, pC2hEvent->CmdLen, c2hBuf);
3756 break;
3757
3758 default:
3759 break;
3760 }
3761}
3762
3763void C2HPacketHandler_8723B(struct adapter *padapter, u8 *pbuffer, u16 length)
3764{
3765 C2H_EVT_HDR C2hEvent;
3766 u8 *tmpBuf = NULL;
3767#ifdef CONFIG_WOWLAN
3768 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
3769
3770 if (pwrpriv->wowlan_mode == true) {
3771 DBG_871X("%s(): return because wowolan_mode ==true! CMDID =%d\n", __func__, pbuffer[0]);
3772 return;
3773 }
3774#endif
3775 C2hEvent.CmdID = pbuffer[0];
3776 C2hEvent.CmdSeq = pbuffer[1];
3777 C2hEvent.CmdLen = length-2;
3778 tmpBuf = pbuffer+2;
3779
3780
3781
3782 RT_PRINT_DATA(_module_hal_init_c_, _drv_notice_, "C2HPacketHandler_8723B(): Command Content:\n", tmpBuf, C2hEvent.CmdLen);
3783
3784 process_c2h_event(padapter, &C2hEvent, tmpBuf);
3785
3786 return;
3787}
3788
3789void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
3790{
3791 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
3792 u8 val8;
3793 u32 val32;
3794
3795 switch (variable) {
3796 case HW_VAR_MEDIA_STATUS:
3797 val8 = rtw_read8(padapter, MSR) & 0x0c;
3798 val8 |= *val;
3799 rtw_write8(padapter, MSR, val8);
3800 break;
3801
3802 case HW_VAR_MEDIA_STATUS1:
3803 val8 = rtw_read8(padapter, MSR) & 0x03;
3804 val8 |= *val << 2;
3805 rtw_write8(padapter, MSR, val8);
3806 break;
3807
3808 case HW_VAR_SET_OPMODE:
3809 hw_var_set_opmode(padapter, variable, val);
3810 break;
3811
3812 case HW_VAR_MAC_ADDR:
3813 hw_var_set_macaddr(padapter, variable, val);
3814 break;
3815
3816 case HW_VAR_BSSID:
3817 hw_var_set_bssid(padapter, variable, val);
3818 break;
3819
3820 case HW_VAR_BASIC_RATE:
3821 {
3822 struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info;
3823 u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
3824 u16 rrsr_2g_force_mask = (RRSR_11M|RRSR_5_5M|RRSR_1M);
3825 u16 rrsr_2g_allow_mask = (RRSR_24M|RRSR_12M|RRSR_6M|RRSR_CCK_RATES);
3826
3827 HalSetBrateCfg(padapter, val, &BrateCfg);
3828 input_b = BrateCfg;
3829
3830
3831 BrateCfg |= rrsr_2g_force_mask;
3832 BrateCfg &= rrsr_2g_allow_mask;
3833 masked = BrateCfg;
3834
3835 #ifdef CONFIG_CMCC_TEST
3836 BrateCfg |= (RRSR_11M|RRSR_5_5M|RRSR_1M);
3837 BrateCfg |= (RRSR_24M|RRSR_18M|RRSR_12M);
3838 #endif
3839
3840
3841 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
3842
3843 if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0)
3844 BrateCfg |= RRSR_6M;
3845 }
3846 ioted = BrateCfg;
3847
3848 pHalData->BasicRateSet = BrateCfg;
3849
3850 DBG_8192C("HW_VAR_BASIC_RATE: %#x -> %#x -> %#x\n", input_b, masked, ioted);
3851
3852
3853 rtw_write16(padapter, REG_RRSR, BrateCfg);
3854 rtw_write8(padapter, REG_RRSR+2, rtw_read8(padapter, REG_RRSR+2)&0xf0);
3855 }
3856 break;
3857
3858 case HW_VAR_TXPAUSE:
3859 rtw_write8(padapter, REG_TXPAUSE, *val);
3860 break;
3861
3862 case HW_VAR_BCN_FUNC:
3863 hw_var_set_bcn_func(padapter, variable, val);
3864 break;
3865
3866 case HW_VAR_CORRECT_TSF:
3867 hw_var_set_correct_tsf(padapter, variable, val);
3868 break;
3869
3870 case HW_VAR_CHECK_BSSID:
3871 {
3872 u32 val32;
3873 val32 = rtw_read32(padapter, REG_RCR);
3874 if (*val)
3875 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
3876 else
3877 val32 &= ~(RCR_CBSSID_DATA|RCR_CBSSID_BCN);
3878 rtw_write32(padapter, REG_RCR, val32);
3879 }
3880 break;
3881
3882 case HW_VAR_MLME_DISCONNECT:
3883 hw_var_set_mlme_disconnect(padapter, variable, val);
3884 break;
3885
3886 case HW_VAR_MLME_SITESURVEY:
3887 hw_var_set_mlme_sitesurvey(padapter, variable, val);
3888
3889 rtw_btcoex_ScanNotify(padapter, *val?true:false);
3890 break;
3891
3892 case HW_VAR_MLME_JOIN:
3893 hw_var_set_mlme_join(padapter, variable, val);
3894
3895 switch (*val) {
3896 case 0:
3897
3898 rtw_btcoex_ConnectNotify(padapter, true);
3899 break;
3900 case 1:
3901
3902 rtw_btcoex_ConnectNotify(padapter, false);
3903 break;
3904 case 2:
3905
3906
3907 break;
3908 }
3909 break;
3910
3911 case HW_VAR_ON_RCR_AM:
3912 val32 = rtw_read32(padapter, REG_RCR);
3913 val32 |= RCR_AM;
3914 rtw_write32(padapter, REG_RCR, val32);
3915 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR));
3916 break;
3917
3918 case HW_VAR_OFF_RCR_AM:
3919 val32 = rtw_read32(padapter, REG_RCR);
3920 val32 &= ~RCR_AM;
3921 rtw_write32(padapter, REG_RCR, val32);
3922 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR));
3923 break;
3924
3925 case HW_VAR_BEACON_INTERVAL:
3926 rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val));
3927 break;
3928
3929 case HW_VAR_SLOT_TIME:
3930 rtw_write8(padapter, REG_SLOT, *val);
3931 break;
3932
3933 case HW_VAR_RESP_SIFS:
3934
3935
3936 rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]);
3937 rtw_write8(padapter, REG_RESP_SIFS_CCK+1, val[1]);
3938
3939 rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]);
3940 rtw_write8(padapter, REG_RESP_SIFS_OFDM+1, val[3]);
3941 break;
3942
3943 case HW_VAR_ACK_PREAMBLE:
3944 {
3945 u8 regTmp;
3946 u8 bShortPreamble = *val;
3947
3948
3949
3950 regTmp = 0;
3951 if (bShortPreamble)
3952 regTmp |= 0x80;
3953 rtw_write8(padapter, REG_RRSR+2, regTmp);
3954 }
3955 break;
3956
3957 case HW_VAR_CAM_EMPTY_ENTRY:
3958 {
3959 u8 ucIndex = *val;
3960 u8 i;
3961 u32 ulCommand = 0;
3962 u32 ulContent = 0;
3963 u32 ulEncAlgo = CAM_AES;
3964
3965 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
3966
3967 if (i == 0) {
3968 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
3969
3970 } else
3971 ulContent = 0;
3972
3973
3974 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
3975 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
3976
3977 rtw_write32(padapter, WCAMI, ulContent);
3978
3979 rtw_write32(padapter, RWCAM, ulCommand);
3980
3981 }
3982 }
3983 break;
3984
3985 case HW_VAR_CAM_INVALID_ALL:
3986 rtw_write32(padapter, RWCAM, BIT(31)|BIT(30));
3987 break;
3988
3989 case HW_VAR_CAM_WRITE:
3990 {
3991 u32 cmd;
3992 u32 *cam_val = (u32 *)val;
3993
3994 rtw_write32(padapter, WCAMI, cam_val[0]);
3995
3996 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
3997 rtw_write32(padapter, RWCAM, cmd);
3998 }
3999 break;
4000
4001 case HW_VAR_AC_PARAM_VO:
4002 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
4003 break;
4004
4005 case HW_VAR_AC_PARAM_VI:
4006 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
4007 break;
4008
4009 case HW_VAR_AC_PARAM_BE:
4010 pHalData->AcParam_BE = ((u32 *)(val))[0];
4011 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
4012 break;
4013
4014 case HW_VAR_AC_PARAM_BK:
4015 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
4016 break;
4017
4018 case HW_VAR_ACM_CTRL:
4019 {
4020 u8 ctrl = *((u8 *)val);
4021 u8 hwctrl = 0;
4022
4023 if (ctrl != 0) {
4024 hwctrl |= AcmHw_HwEn;
4025
4026 if (ctrl & BIT(1))
4027 hwctrl |= AcmHw_BeqEn;
4028
4029 if (ctrl & BIT(2))
4030 hwctrl |= AcmHw_ViqEn;
4031
4032 if (ctrl & BIT(3))
4033 hwctrl |= AcmHw_VoqEn;
4034 }
4035
4036 DBG_8192C("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
4037 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
4038 }
4039 break;
4040
4041 case HW_VAR_AMPDU_FACTOR:
4042 {
4043 u32 AMPDULen = (*((u8 *)val));
4044
4045 if (AMPDULen < HT_AGG_SIZE_32K)
4046 AMPDULen = (0x2000 << (*((u8 *)val)))-1;
4047 else
4048 AMPDULen = 0x7fff;
4049
4050 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, AMPDULen);
4051 }
4052 break;
4053
4054 case HW_VAR_H2C_FW_PWRMODE:
4055 {
4056 u8 psmode = *val;
4057
4058
4059
4060 if (psmode != PS_MODE_ACTIVE) {
4061 ODM_RF_Saving(&pHalData->odmpriv, true);
4062 }
4063
4064
4065
4066
4067
4068
4069 rtl8723b_set_FwPwrMode_cmd(padapter, psmode);
4070 }
4071 break;
4072 case HW_VAR_H2C_PS_TUNE_PARAM:
4073 rtl8723b_set_FwPsTuneParam_cmd(padapter);
4074 break;
4075
4076 case HW_VAR_H2C_FW_JOINBSSRPT:
4077 rtl8723b_set_FwJoinBssRpt_cmd(padapter, *val);
4078 break;
4079
4080 case HW_VAR_INITIAL_GAIN:
4081 {
4082 DIG_T *pDigTable = &pHalData->odmpriv.DM_DigTable;
4083 u32 rx_gain = *(u32 *)val;
4084
4085 if (rx_gain == 0xff) {
4086 ODM_Write_DIG(&pHalData->odmpriv, pDigTable->BackupIGValue);
4087 } else {
4088 pDigTable->BackupIGValue = pDigTable->CurIGValue;
4089 ODM_Write_DIG(&pHalData->odmpriv, rx_gain);
4090 }
4091 }
4092 break;
4093
4094 case HW_VAR_EFUSE_USAGE:
4095 pHalData->EfuseUsedPercentage = *val;
4096 break;
4097
4098 case HW_VAR_EFUSE_BYTES:
4099 pHalData->EfuseUsedBytes = *((u16 *)val);
4100 break;
4101
4102 case HW_VAR_EFUSE_BT_USAGE:
4103#ifdef HAL_EFUSE_MEMORY
4104 pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
4105#endif
4106 break;
4107
4108 case HW_VAR_EFUSE_BT_BYTES:
4109#ifdef HAL_EFUSE_MEMORY
4110 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
4111#else
4112 BTEfuseUsedBytes = *((u16 *)val);
4113#endif
4114 break;
4115
4116 case HW_VAR_FIFO_CLEARN_UP:
4117 {
4118 #define RW_RELEASE_EN BIT(18)
4119 #define RXDMA_IDLE BIT(17)
4120
4121 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
4122 u8 trycnt = 100;
4123
4124
4125 rtw_write8(padapter, REG_TXPAUSE, 0xff);
4126
4127
4128 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
4129
4130 if (pwrpriv->bkeepfwalive != true) {
4131
4132 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4133 val32 |= RW_RELEASE_EN;
4134 rtw_write32(padapter, REG_RXPKT_NUM, val32);
4135 do {
4136 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4137 val32 &= RXDMA_IDLE;
4138 if (val32)
4139 break;
4140
4141 DBG_871X("%s: [HW_VAR_FIFO_CLEARN_UP] val =%x times:%d\n", __func__, val32, trycnt);
4142 } while (--trycnt);
4143
4144 if (trycnt == 0) {
4145 DBG_8192C("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n");
4146 }
4147
4148
4149 rtw_write16(padapter, REG_RQPN_NPQ, 0);
4150 rtw_write32(padapter, REG_RQPN, 0x80000000);
4151 mdelay(2);
4152 }
4153 }
4154 break;
4155
4156 case HW_VAR_APFM_ON_MAC:
4157 pHalData->bMacPwrCtrlOn = *val;
4158 DBG_8192C("%s: bMacPwrCtrlOn =%d\n", __func__, pHalData->bMacPwrCtrlOn);
4159 break;
4160
4161 case HW_VAR_NAV_UPPER:
4162 {
4163 u32 usNavUpper = *((u32 *)val);
4164
4165 if (usNavUpper > HAL_NAV_UPPER_UNIT_8723B * 0xFF) {
4166 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", usNavUpper, HAL_NAV_UPPER_UNIT_8723B));
4167 break;
4168 }
4169
4170
4171
4172 usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8723B - 1) / HAL_NAV_UPPER_UNIT_8723B;
4173 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
4174 }
4175 break;
4176
4177 case HW_VAR_H2C_MEDIA_STATUS_RPT:
4178 {
4179 u16 mstatus_rpt = (*(u16 *)val);
4180 u8 mstatus, macId;
4181
4182 mstatus = (u8) (mstatus_rpt & 0xFF);
4183 macId = (u8)(mstatus_rpt >> 8);
4184 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, mstatus, macId);
4185 }
4186 break;
4187 case HW_VAR_BCN_VALID:
4188 {
4189
4190 val8 = rtw_read8(padapter, REG_TDECTRL+2);
4191 val8 |= BIT(0);
4192 rtw_write8(padapter, REG_TDECTRL+2, val8);
4193 }
4194 break;
4195
4196 case HW_VAR_DL_BCN_SEL:
4197 {
4198
4199 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
4200 val8 &= ~BIT(4);
4201 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8);
4202 }
4203 break;
4204
4205 case HW_VAR_DO_IQK:
4206 pHalData->bNeedIQK = true;
4207 break;
4208
4209 case HW_VAR_DL_RSVD_PAGE:
4210 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)
4211 rtl8723b_download_BTCoex_AP_mode_rsvd_page(padapter);
4212 else
4213 rtl8723b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
4214 break;
4215
4216 case HW_VAR_MACID_SLEEP:
4217
4218 val32 = *(u32 *)val;
4219 if (val32 > 31) {
4220 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] Invalid macid(%d)\n",
4221 FUNC_ADPT_ARG(padapter), val32);
4222 break;
4223 }
4224 val8 = (u8)val32;
4225
4226 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
4227 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid =%d, org MACID_SLEEP = 0x%08X\n",
4228 FUNC_ADPT_ARG(padapter), val8, val32);
4229 if (val32 & BIT(val8))
4230 break;
4231 val32 |= BIT(val8);
4232 rtw_write32(padapter, REG_MACID_SLEEP, val32);
4233 break;
4234
4235 case HW_VAR_MACID_WAKEUP:
4236
4237 val32 = *(u32 *)val;
4238 if (val32 > 31) {
4239 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] Invalid macid(%d)\n",
4240 FUNC_ADPT_ARG(padapter), val32);
4241 break;
4242 }
4243 val8 = (u8)val32;
4244
4245 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
4246 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid =%d, org MACID_SLEEP = 0x%08X\n",
4247 FUNC_ADPT_ARG(padapter), val8, val32);
4248 if (!(val32 & BIT(val8)))
4249 break;
4250 val32 &= ~BIT(val8);
4251 rtw_write32(padapter, REG_MACID_SLEEP, val32);
4252 break;
4253
4254 default:
4255 SetHwReg(padapter, variable, val);
4256 break;
4257 }
4258}
4259
4260void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
4261{
4262 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
4263 u8 val8;
4264 u16 val16;
4265
4266 switch (variable) {
4267 case HW_VAR_TXPAUSE:
4268 *val = rtw_read8(padapter, REG_TXPAUSE);
4269 break;
4270
4271 case HW_VAR_BCN_VALID:
4272 {
4273
4274 val8 = rtw_read8(padapter, REG_TDECTRL+2);
4275 *val = (BIT(0) & val8) ? true : false;
4276 }
4277 break;
4278
4279 case HW_VAR_FWLPS_RF_ON:
4280 {
4281
4282 u32 valRCR;
4283
4284 if (
4285 (padapter->bSurpriseRemoved == true) ||
4286 (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)
4287 ) {
4288
4289
4290 *val = true;
4291 } else {
4292 valRCR = rtw_read32(padapter, REG_RCR);
4293 valRCR &= 0x00070000;
4294 if (valRCR)
4295 *val = false;
4296 else
4297 *val = true;
4298 }
4299 }
4300 break;
4301
4302 case HW_VAR_EFUSE_USAGE:
4303 *val = pHalData->EfuseUsedPercentage;
4304 break;
4305
4306 case HW_VAR_EFUSE_BYTES:
4307 *((u16 *)val) = pHalData->EfuseUsedBytes;
4308 break;
4309
4310 case HW_VAR_EFUSE_BT_USAGE:
4311#ifdef HAL_EFUSE_MEMORY
4312 *val = pHalData->EfuseHal.BTEfuseUsedPercentage;
4313#endif
4314 break;
4315
4316 case HW_VAR_EFUSE_BT_BYTES:
4317#ifdef HAL_EFUSE_MEMORY
4318 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
4319#else
4320 *((u16 *)val) = BTEfuseUsedBytes;
4321#endif
4322 break;
4323
4324 case HW_VAR_APFM_ON_MAC:
4325 *val = pHalData->bMacPwrCtrlOn;
4326 break;
4327 case HW_VAR_CHK_HI_QUEUE_EMPTY:
4328 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
4329 *val = (val16 & BIT(10)) ? true:false;
4330 break;
4331#ifdef CONFIG_WOWLAN
4332 case HW_VAR_RPWM_TOG:
4333 *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1) & BIT7;
4334 break;
4335 case HW_VAR_WAKEUP_REASON:
4336 *val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
4337 if (*val == 0xEA)
4338 *val = 0;
4339 break;
4340 case HW_VAR_SYS_CLKR:
4341 *val = rtw_read8(padapter, REG_SYS_CLKR);
4342 break;
4343#endif
4344 default:
4345 GetHwReg(padapter, variable, val);
4346 break;
4347 }
4348}
4349
4350
4351
4352
4353
4354u8 SetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval)
4355{
4356 struct hal_com_data *pHalData;
4357 u8 bResult;
4358
4359
4360 pHalData = GET_HAL_DATA(padapter);
4361 bResult = _SUCCESS;
4362
4363 switch (variable) {
4364 default:
4365 bResult = SetHalDefVar(padapter, variable, pval);
4366 break;
4367 }
4368
4369 return bResult;
4370}
4371
4372
4373
4374
4375
4376u8 GetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval)
4377{
4378 struct hal_com_data *pHalData;
4379 u8 bResult;
4380
4381
4382 pHalData = GET_HAL_DATA(padapter);
4383 bResult = _SUCCESS;
4384
4385 switch (variable) {
4386 case HAL_DEF_MAX_RECVBUF_SZ:
4387 *((u32 *)pval) = MAX_RECVBUF_SZ;
4388 break;
4389
4390 case HAL_DEF_RX_PACKET_OFFSET:
4391 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ*8;
4392 break;
4393
4394 case HW_VAR_MAX_RX_AMPDU_FACTOR:
4395
4396
4397
4398 *(u32 *)pval = MAX_AMPDU_FACTOR_16K;
4399 break;
4400 case HAL_DEF_TX_LDPC:
4401 case HAL_DEF_RX_LDPC:
4402 *((u8 *)pval) = false;
4403 break;
4404 case HAL_DEF_TX_STBC:
4405 *((u8 *)pval) = 0;
4406 break;
4407 case HAL_DEF_RX_STBC:
4408 *((u8 *)pval) = 1;
4409 break;
4410 case HAL_DEF_EXPLICIT_BEAMFORMER:
4411 case HAL_DEF_EXPLICIT_BEAMFORMEE:
4412 *((u8 *)pval) = false;
4413 break;
4414
4415 case HW_DEF_RA_INFO_DUMP:
4416 {
4417 u8 mac_id = *(u8 *)pval;
4418 u32 cmd;
4419 u32 ra_info1, ra_info2;
4420 u32 rate_mask1, rate_mask2;
4421 u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
4422
4423 DBG_8192C("============ RA status check Mac_id:%d ===================\n", mac_id);
4424
4425 cmd = 0x40000100 | mac_id;
4426 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
4427 msleep(10);
4428 ra_info1 = rtw_read32(padapter, 0x2F0);
4429 curr_tx_rate = ra_info1&0x7F;
4430 curr_tx_sgi = (ra_info1>>7)&0x01;
4431 DBG_8192C("[ ra_info1:0x%08x ] =>cur_tx_rate = %s, cur_sgi:%d, PWRSTS = 0x%02x \n",
4432 ra_info1,
4433 HDATA_RATE(curr_tx_rate),
4434 curr_tx_sgi,
4435 (ra_info1>>8) & 0x07);
4436
4437 cmd = 0x40000400 | mac_id;
4438 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
4439 msleep(10);
4440 ra_info1 = rtw_read32(padapter, 0x2F0);
4441 ra_info2 = rtw_read32(padapter, 0x2F4);
4442 rate_mask1 = rtw_read32(padapter, 0x2F8);
4443 rate_mask2 = rtw_read32(padapter, 0x2FC);
4444 hight_rate = ra_info2&0xFF;
4445 lowest_rate = (ra_info2>>8) & 0xFF;
4446
4447 DBG_8192C("[ ra_info1:0x%08x ] =>RSSI =%d, BW_setting = 0x%02x, DISRA = 0x%02x, VHT_EN = 0x%02x\n",
4448 ra_info1,
4449 ra_info1&0xFF,
4450 (ra_info1>>8) & 0xFF,
4451 (ra_info1>>16) & 0xFF,
4452 (ra_info1>>24) & 0xFF);
4453
4454 DBG_8192C("[ ra_info2:0x%08x ] =>hight_rate =%s, lowest_rate =%s, SGI = 0x%02x, RateID =%d\n",
4455 ra_info2,
4456 HDATA_RATE(hight_rate),
4457 HDATA_RATE(lowest_rate),
4458 (ra_info2>>16) & 0xFF,
4459 (ra_info2>>24) & 0xFF);
4460
4461 DBG_8192C("rate_mask2 = 0x%08x, rate_mask1 = 0x%08x\n", rate_mask2, rate_mask1);
4462
4463 }
4464 break;
4465
4466 case HAL_DEF_TX_PAGE_BOUNDARY:
4467 if (!padapter->registrypriv.wifi_spec) {
4468 *(u8 *)pval = TX_PAGE_BOUNDARY_8723B;
4469 } else {
4470 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
4471 }
4472 break;
4473
4474 case HAL_DEF_MACID_SLEEP:
4475 *(u8 *)pval = true;
4476 break;
4477
4478 default:
4479 bResult = GetHalDefVar(padapter, variable, pval);
4480 break;
4481 }
4482
4483 return bResult;
4484}
4485
4486#ifdef CONFIG_WOWLAN
4487void Hal_DetectWoWMode(struct adapter *padapter)
4488{
4489 adapter_to_pwrctl(padapter)->bSupportRemoteWakeup = true;
4490 DBG_871X("%s\n", __func__);
4491}
4492#endif
4493
4494void rtl8723b_start_thread(struct adapter *padapter)
4495{
4496#ifndef CONFIG_SDIO_TX_TASKLET
4497 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
4498
4499 xmitpriv->SdioXmitThread = kthread_run(rtl8723bs_xmit_thread, padapter, "RTWHALXT");
4500 if (IS_ERR(xmitpriv->SdioXmitThread)) {
4501 RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8723bs_xmit_thread FAIL!!\n", __func__));
4502 }
4503#endif
4504}
4505
4506void rtl8723b_stop_thread(struct adapter *padapter)
4507{
4508#ifndef CONFIG_SDIO_TX_TASKLET
4509 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
4510
4511
4512 if (xmitpriv->SdioXmitThread) {
4513 up(&xmitpriv->SdioXmitSema);
4514 down(&xmitpriv->SdioXmitTerminateSema);
4515 xmitpriv->SdioXmitThread = NULL;
4516 }
4517#endif
4518}
4519
4520#if defined(CONFIG_CHECK_BT_HANG)
4521extern void check_bt_status_work(void *data);
4522void rtl8723bs_init_checkbthang_workqueue(struct adapter *adapter)
4523{
4524 adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0);
4525 INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work);
4526}
4527
4528void rtl8723bs_free_checkbthang_workqueue(struct adapter *adapter)
4529{
4530 if (adapter->priv_checkbt_wq) {
4531 cancel_delayed_work_sync(&adapter->checkbt_work);
4532 flush_workqueue(adapter->priv_checkbt_wq);
4533 destroy_workqueue(adapter->priv_checkbt_wq);
4534 adapter->priv_checkbt_wq = NULL;
4535 }
4536}
4537
4538void rtl8723bs_cancle_checkbthang_workqueue(struct adapter *adapter)
4539{
4540 if (adapter->priv_checkbt_wq)
4541 cancel_delayed_work_sync(&adapter->checkbt_work);
4542}
4543
4544void rtl8723bs_hal_check_bt_hang(struct adapter *adapter)
4545{
4546 if (adapter->priv_checkbt_wq)
4547 queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0);
4548}
4549#endif
4550