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15#ifndef __HAL_INTF_H__
16#define __HAL_INTF_H__
17
18
19enum RTL871X_HCI_TYPE {
20 RTW_PCIE = BIT0,
21 RTW_USB = BIT1,
22 RTW_SDIO = BIT2,
23 RTW_GSPI = BIT3,
24};
25
26enum HW_VARIABLES {
27 HW_VAR_MEDIA_STATUS,
28 HW_VAR_MEDIA_STATUS1,
29 HW_VAR_SET_OPMODE,
30 HW_VAR_MAC_ADDR,
31 HW_VAR_BSSID,
32 HW_VAR_INIT_RTS_RATE,
33 HW_VAR_BASIC_RATE,
34 HW_VAR_TXPAUSE,
35 HW_VAR_BCN_FUNC,
36 HW_VAR_CORRECT_TSF,
37 HW_VAR_CHECK_BSSID,
38 HW_VAR_MLME_DISCONNECT,
39 HW_VAR_MLME_SITESURVEY,
40 HW_VAR_MLME_JOIN,
41 HW_VAR_ON_RCR_AM,
42 HW_VAR_OFF_RCR_AM,
43 HW_VAR_BEACON_INTERVAL,
44 HW_VAR_SLOT_TIME,
45 HW_VAR_RESP_SIFS,
46 HW_VAR_ACK_PREAMBLE,
47 HW_VAR_SEC_CFG,
48 HW_VAR_SEC_DK_CFG,
49 HW_VAR_BCN_VALID,
50 HW_VAR_RF_TYPE,
51 HW_VAR_DM_FLAG,
52 HW_VAR_DM_FUNC_OP,
53 HW_VAR_DM_FUNC_SET,
54 HW_VAR_DM_FUNC_CLR,
55 HW_VAR_CAM_EMPTY_ENTRY,
56 HW_VAR_CAM_INVALID_ALL,
57 HW_VAR_CAM_WRITE,
58 HW_VAR_CAM_READ,
59 HW_VAR_AC_PARAM_VO,
60 HW_VAR_AC_PARAM_VI,
61 HW_VAR_AC_PARAM_BE,
62 HW_VAR_AC_PARAM_BK,
63 HW_VAR_ACM_CTRL,
64 HW_VAR_AMPDU_MIN_SPACE,
65 HW_VAR_AMPDU_FACTOR,
66 HW_VAR_RXDMA_AGG_PG_TH,
67 HW_VAR_SET_RPWM,
68 HW_VAR_CPWM,
69 HW_VAR_H2C_FW_PWRMODE,
70 HW_VAR_H2C_PS_TUNE_PARAM,
71 HW_VAR_H2C_FW_JOINBSSRPT,
72 HW_VAR_FWLPS_RF_ON,
73 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
74 HW_VAR_TDLS_WRCR,
75 HW_VAR_TDLS_INIT_CH_SEN,
76 HW_VAR_TDLS_RS_RCR,
77 HW_VAR_TDLS_DONE_CH_SEN,
78 HW_VAR_INITIAL_GAIN,
79 HW_VAR_TRIGGER_GPIO_0,
80 HW_VAR_BT_SET_COEXIST,
81 HW_VAR_BT_ISSUE_DELBA,
82 HW_VAR_CURRENT_ANTENNA,
83 HW_VAR_ANTENNA_DIVERSITY_LINK,
84 HW_VAR_ANTENNA_DIVERSITY_SELECT,
85 HW_VAR_SWITCH_EPHY_WoWLAN,
86 HW_VAR_EFUSE_USAGE,
87 HW_VAR_EFUSE_BYTES,
88 HW_VAR_EFUSE_BT_USAGE,
89 HW_VAR_EFUSE_BT_BYTES,
90 HW_VAR_FIFO_CLEARN_UP,
91 HW_VAR_CHECK_TXBUF,
92 HW_VAR_PCIE_STOP_TX_DMA,
93 HW_VAR_APFM_ON_MAC,
94
95
96#ifdef CONFIG_WOWLAN
97 HW_VAR_WOWLAN,
98 HW_VAR_WAKEUP_REASON,
99 HW_VAR_RPWM_TOG,
100#endif
101#ifdef CONFIG_AP_WOWLAN
102 HW_VAR_AP_WOWLAN,
103#endif
104 HW_VAR_SYS_CLKR,
105 HW_VAR_NAV_UPPER,
106 HW_VAR_C2H_HANDLE,
107 HW_VAR_RPT_TIMER_SETTING,
108 HW_VAR_TX_RPT_MAX_MACID,
109 HW_VAR_H2C_MEDIA_STATUS_RPT,
110 HW_VAR_CHK_HI_QUEUE_EMPTY,
111 HW_VAR_DL_BCN_SEL,
112 HW_VAR_AMPDU_MAX_TIME,
113 HW_VAR_WIRELESS_MODE,
114 HW_VAR_USB_MODE,
115 HW_VAR_PORT_SWITCH,
116 HW_VAR_DO_IQK,
117 HW_VAR_DM_IN_LPS,
118 HW_VAR_SET_REQ_FW_PS,
119 HW_VAR_FW_PS_STATE,
120 HW_VAR_SOUNDING_ENTER,
121 HW_VAR_SOUNDING_LEAVE,
122 HW_VAR_SOUNDING_RATE,
123 HW_VAR_SOUNDING_STATUS,
124 HW_VAR_SOUNDING_FW_NDPA,
125 HW_VAR_SOUNDING_CLK,
126 HW_VAR_DL_RSVD_PAGE,
127 HW_VAR_MACID_SLEEP,
128 HW_VAR_MACID_WAKEUP,
129};
130
131enum HAL_DEF_VARIABLE {
132 HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
133 HAL_DEF_IS_SUPPORT_ANT_DIV,
134 HAL_DEF_CURRENT_ANTENNA,
135 HAL_DEF_DRVINFO_SZ,
136 HAL_DEF_MAX_RECVBUF_SZ,
137 HAL_DEF_RX_PACKET_OFFSET,
138 HAL_DEF_DBG_DUMP_RXPKT,
139 HAL_DEF_DBG_DM_FUNC,
140 HAL_DEF_RA_DECISION_RATE,
141 HAL_DEF_RA_SGI,
142 HAL_DEF_PT_PWR_STATUS,
143 HAL_DEF_TX_LDPC,
144 HAL_DEF_RX_LDPC,
145 HAL_DEF_TX_STBC,
146 HAL_DEF_RX_STBC,
147 HAL_DEF_EXPLICIT_BEAMFORMER,
148 HAL_DEF_EXPLICIT_BEAMFORMEE,
149 HW_VAR_MAX_RX_AMPDU_FACTOR,
150 HW_DEF_RA_INFO_DUMP,
151 HAL_DEF_DBG_DUMP_TXPKT,
152 HW_DEF_FA_CNT_DUMP,
153 HW_DEF_ODM_DBG_FLAG,
154 HW_DEF_ODM_DBG_LEVEL,
155 HAL_DEF_TX_PAGE_SIZE,
156 HAL_DEF_TX_PAGE_BOUNDARY,
157 HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
158 HAL_DEF_ANT_DETECT,
159 HAL_DEF_PCI_SUUPORT_L1_BACKDOOR,
160 HAL_DEF_PCI_AMD_L1_SUPPORT,
161 HAL_DEF_PCI_ASPM_OSC,
162 HAL_DEF_MACID_SLEEP,
163 HAL_DEF_DBG_RX_INFO_DUMP,
164};
165
166enum HAL_ODM_VARIABLE {
167 HAL_ODM_STA_INFO,
168 HAL_ODM_P2P_STATE,
169 HAL_ODM_WIFI_DISPLAY_STATE,
170 HAL_ODM_NOISE_MONITOR,
171};
172
173enum HAL_INTF_PS_FUNC {
174 HAL_USB_SELECT_SUSPEND,
175 HAL_MAX_ID,
176};
177
178typedef s32 (*c2h_id_filter)(u8 *c2h_evt);
179
180struct hal_ops {
181 u32 (*hal_power_on)(struct adapter *padapter);
182 void (*hal_power_off)(struct adapter *padapter);
183 u32 (*hal_init)(struct adapter *padapter);
184 u32 (*hal_deinit)(struct adapter *padapter);
185
186 void (*free_hal_data)(struct adapter *padapter);
187
188 u32 (*inirp_init)(struct adapter *padapter);
189 u32 (*inirp_deinit)(struct adapter *padapter);
190 void (*irp_reset)(struct adapter *padapter);
191
192 s32 (*init_xmit_priv)(struct adapter *padapter);
193 void (*free_xmit_priv)(struct adapter *padapter);
194
195 s32 (*init_recv_priv)(struct adapter *padapter);
196 void (*free_recv_priv)(struct adapter *padapter);
197
198 void (*dm_init)(struct adapter *padapter);
199 void (*dm_deinit)(struct adapter *padapter);
200 void (*read_chip_version)(struct adapter *padapter);
201
202 void (*init_default_value)(struct adapter *padapter);
203
204 void (*intf_chip_configure)(struct adapter *padapter);
205
206 void (*read_adapter_info)(struct adapter *padapter);
207
208 void (*enable_interrupt)(struct adapter *padapter);
209 void (*disable_interrupt)(struct adapter *padapter);
210 u8 (*check_ips_status)(struct adapter *padapter);
211 s32 (*interrupt_handler)(struct adapter *padapter);
212 void (*clear_interrupt)(struct adapter *padapter);
213 void (*set_bwmode_handler)(struct adapter *padapter, enum CHANNEL_WIDTH Bandwidth, u8 Offset);
214 void (*set_channel_handler)(struct adapter *padapter, u8 channel);
215 void (*set_chnl_bw_handler)(struct adapter *padapter, u8 channel, enum CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80);
216
217 void (*set_tx_power_level_handler)(struct adapter *padapter, u8 channel);
218 void (*get_tx_power_level_handler)(struct adapter *padapter, s32 *powerlevel);
219
220 void (*hal_dm_watchdog)(struct adapter *padapter);
221 void (*hal_dm_watchdog_in_lps)(struct adapter *padapter);
222
223
224 void (*SetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val);
225 void (*GetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val);
226
227 void (*SetHwRegHandlerWithBuf)(struct adapter *padapter, u8 variable, u8 *pbuf, int len);
228
229 u8 (*GetHalDefVarHandler)(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
230 u8 (*SetHalDefVarHandler)(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
231
232 void (*GetHalODMVarHandler)(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
233 void (*SetHalODMVarHandler)(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, bool bSet);
234
235 void (*UpdateRAMaskHandler)(struct adapter *padapter, u32 mac_id, u8 rssi_level);
236 void (*SetBeaconRelatedRegistersHandler)(struct adapter *padapter);
237
238 void (*Add_RateATid)(struct adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level);
239
240 void (*run_thread)(struct adapter *padapter);
241 void (*cancel_thread)(struct adapter *padapter);
242
243 u8 (*interface_ps_func)(struct adapter *padapter, enum HAL_INTF_PS_FUNC efunc_id, u8 *val);
244
245 s32 (*hal_xmit)(struct adapter *padapter, struct xmit_frame *pxmitframe);
246
247
248
249 s32 (*mgnt_xmit)(struct adapter *padapter, struct xmit_frame *pmgntframe);
250 s32 (*hal_xmitframe_enqueue)(struct adapter *padapter, struct xmit_frame *pxmitframe);
251
252 u32 (*read_bbreg)(struct adapter *padapter, u32 RegAddr, u32 BitMask);
253 void (*write_bbreg)(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
254 u32 (*read_rfreg)(struct adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask);
255 void (*write_rfreg)(struct adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
256
257 void (*EfusePowerSwitch)(struct adapter *padapter, u8 bWrite, u8 PwrState);
258 void (*BTEfusePowerSwitch)(struct adapter *padapter, u8 bWrite, u8 PwrState);
259 void (*ReadEFuse)(struct adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest);
260 void (*EFUSEGetEfuseDefinition)(struct adapter *padapter, u8 efuseType, u8 type, void *pOut, bool bPseudoTest);
261 u16 (*EfuseGetCurrentSize)(struct adapter *padapter, u8 efuseType, bool bPseudoTest);
262 int (*Efuse_PgPacketRead)(struct adapter *padapter, u8 offset, u8 *data, bool bPseudoTest);
263 int (*Efuse_PgPacketWrite)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest);
264 u8 (*Efuse_WordEnableDataWrite)(struct adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest);
265 bool (*Efuse_PgPacketWrite_BT)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest);
266
267 s32 (*xmit_thread_handler)(struct adapter *padapter);
268 void (*hal_notch_filter)(struct adapter * adapter, bool enable);
269 void (*hal_reset_security_engine)(struct adapter * adapter);
270 s32 (*c2h_handler)(struct adapter *padapter, u8 *c2h_evt);
271 c2h_id_filter c2h_id_filter_ccx;
272
273 s32 (*fill_h2c_cmd)(struct adapter *, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
274};
275
276enum RT_EEPROM_TYPE {
277 EEPROM_93C46,
278 EEPROM_93C56,
279 EEPROM_BOOT_EFUSE,
280};
281
282#define RF_CHANGE_BY_INIT 0
283#define RF_CHANGE_BY_IPS BIT28
284#define RF_CHANGE_BY_PS BIT29
285#define RF_CHANGE_BY_HW BIT30
286#define RF_CHANGE_BY_SW BIT31
287
288#define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv)
289#define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse)
290
291enum wowlan_subcode {
292 WOWLAN_PATTERN_MATCH = 1,
293 WOWLAN_MAGIC_PACKET = 2,
294 WOWLAN_UNICAST = 3,
295 WOWLAN_SET_PATTERN = 4,
296 WOWLAN_DUMP_REG = 5,
297 WOWLAN_ENABLE = 6,
298 WOWLAN_DISABLE = 7,
299 WOWLAN_STATUS = 8,
300 WOWLAN_DEBUG_RELOAD_FW = 9,
301 WOWLAN_DEBUG_1 = 10,
302 WOWLAN_DEBUG_2 = 11,
303 WOWLAN_AP_ENABLE = 12,
304 WOWLAN_AP_DISABLE = 13
305};
306
307struct wowlan_ioctl_param{
308 unsigned int subcode;
309 unsigned int subcode_value;
310 unsigned int wakeup_reason;
311 unsigned int len;
312 unsigned char pattern[0];
313};
314
315#define Rx_Pairwisekey 0x01
316#define Rx_GTK 0x02
317#define Rx_DisAssoc 0x04
318#define Rx_DeAuth 0x08
319#define Rx_ARPReq 0x09
320#define FWDecisionDisconnect 0x10
321#define Rx_MagicPkt 0x21
322#define Rx_UnicastPkt 0x22
323#define Rx_PatternPkt 0x23
324#define RX_PNOWakeUp 0x55
325#define AP_WakeUp 0x66
326
327void rtw_hal_def_value_init(struct adapter *padapter);
328
329void rtw_hal_free_data(struct adapter *padapter);
330
331void rtw_hal_dm_init(struct adapter *padapter);
332void rtw_hal_dm_deinit(struct adapter *padapter);
333
334uint rtw_hal_init(struct adapter *padapter);
335uint rtw_hal_deinit(struct adapter *padapter);
336void rtw_hal_stop(struct adapter *padapter);
337void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val);
338void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val);
339
340void rtw_hal_set_hwreg_with_buf(struct adapter *padapter, u8 variable, u8 *pbuf, int len);
341
342void rtw_hal_chip_configure(struct adapter *padapter);
343void rtw_hal_read_chip_info(struct adapter *padapter);
344void rtw_hal_read_chip_version(struct adapter *padapter);
345
346u8 rtw_hal_set_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
347u8 rtw_hal_get_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue);
348
349void rtw_hal_set_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, bool bSet);
350void rtw_hal_get_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
351
352void rtw_hal_enable_interrupt(struct adapter *padapter);
353void rtw_hal_disable_interrupt(struct adapter *padapter);
354
355u8 rtw_hal_check_ips_status(struct adapter *padapter);
356
357s32 rtw_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe);
358s32 rtw_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
359s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
360
361s32 rtw_hal_init_xmit_priv(struct adapter *padapter);
362void rtw_hal_free_xmit_priv(struct adapter *padapter);
363
364s32 rtw_hal_init_recv_priv(struct adapter *padapter);
365void rtw_hal_free_recv_priv(struct adapter *padapter);
366
367void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level);
368void rtw_hal_add_ra_tid(struct adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level);
369
370void rtw_hal_start_thread(struct adapter *padapter);
371void rtw_hal_stop_thread(struct adapter *padapter);
372
373void rtw_hal_bcn_related_reg_setting(struct adapter *padapter);
374
375u32 rtw_hal_read_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask);
376void rtw_hal_write_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
377u32 rtw_hal_read_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
378void rtw_hal_write_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
379
380#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))
381#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))
382#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
383#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
384
385#define PHY_SetMacReg PHY_SetBBReg
386#define PHY_QueryMacReg PHY_QueryBBReg
387
388void rtw_hal_set_chan(struct adapter *padapter, u8 channel);
389void rtw_hal_set_chnl_bw(struct adapter *padapter, u8 channel, enum CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80);
390void rtw_hal_dm_watchdog(struct adapter *padapter);
391void rtw_hal_dm_watchdog_in_lps(struct adapter *padapter);
392
393s32 rtw_hal_xmit_thread_handler(struct adapter *padapter);
394
395void rtw_hal_notch_filter(struct adapter * adapter, bool enable);
396void rtw_hal_reset_security_engine(struct adapter * adapter);
397
398bool rtw_hal_c2h_valid(struct adapter *adapter, u8 *buf);
399s32 rtw_hal_c2h_evt_read(struct adapter *adapter, u8 *buf);
400s32 rtw_hal_c2h_handler(struct adapter *adapter, u8 *c2h_evt);
401c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter);
402
403s32 rtw_hal_is_disable_sw_channel_plan(struct adapter *padapter);
404
405s32 rtw_hal_macid_sleep(struct adapter *padapter, u32 macid);
406s32 rtw_hal_macid_wakeup(struct adapter *padapter, u32 macid);
407
408s32 rtw_hal_fill_h2c_cmd(struct adapter *, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
409
410#endif
411
