1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *******************************************************************************/ 15#ifndef __RTL8723B_SPEC_H__ 16#define __RTL8723B_SPEC_H__ 17 18#include <autoconf.h> 19 20#define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ 21 22/* */ 23/* */ 24/* 0x0000h ~ 0x00FFh System Configuration */ 25/* */ 26/* */ 27#define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ 28#define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038 29#define REG_HSISR_8723B 0x005c 30#define REG_PAD_CTRL1_8723B 0x0064 31#define REG_AFE_CTRL_4_8723B 0x0078 32#define REG_HMEBOX_DBG_0_8723B 0x0088 33#define REG_HMEBOX_DBG_1_8723B 0x008A 34#define REG_HMEBOX_DBG_2_8723B 0x008C 35#define REG_HMEBOX_DBG_3_8723B 0x008E 36#define REG_HIMR0_8723B 0x00B0 37#define REG_HISR0_8723B 0x00B4 38#define REG_HIMR1_8723B 0x00B8 39#define REG_HISR1_8723B 0x00BC 40#define REG_PMC_DBG_CTRL2_8723B 0x00CC 41 42/* */ 43/* */ 44/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 45/* */ 46/* */ 47#define REG_C2HEVT_CMD_ID_8723B 0x01A0 48#define REG_C2HEVT_CMD_LEN_8723B 0x01AE 49#define REG_WOWLAN_WAKE_REASON 0x01C7 50#define REG_WOWLAN_GTK_DBG1 0x630 51#define REG_WOWLAN_GTK_DBG2 0x634 52 53#define REG_HMEBOX_EXT0_8723B 0x01F0 54#define REG_HMEBOX_EXT1_8723B 0x01F4 55#define REG_HMEBOX_EXT2_8723B 0x01F8 56#define REG_HMEBOX_EXT3_8723B 0x01FC 57 58/* */ 59/* */ 60/* 0x0200h ~ 0x027Fh TXDMA Configuration */ 61/* */ 62/* */ 63 64/* */ 65/* */ 66/* 0x0280h ~ 0x02FFh RXDMA Configuration */ 67/* */ 68/* */ 69#define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ 70#define REG_RXDMA_MODE_CTRL_8723B 0x0290 71 72/* */ 73/* */ 74/* 0x0300h ~ 0x03FFh PCIe */ 75/* */ 76/* */ 77#define REG_PCIE_CTRL_REG_8723B 0x0300 78#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ 79#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ 80#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ 81#define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ 82#define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ 83#define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ 84#define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ 85#define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ 86#define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ 87#define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ 88#define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ 89#define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ 90#define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ 91#define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ 92#define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ 93#define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ 94#define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ 95#define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ 96#define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ 97#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ 98 99/* */ 100/* */ 101/* 0x0400h ~ 0x047Fh Protocol Configuration */ 102/* */ 103/* */ 104#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 105#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 106#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D 107#ifdef CONFIG_WOWLAN 108#define REG_TXPKTBUF_IV_LOW 0x0484 109#define REG_TXPKTBUF_IV_HIGH 0x0488 110#endif 111#define REG_AMPDU_BURST_MODE_8723B 0x04BC 112 113/* */ 114/* */ 115/* 0x0500h ~ 0x05FFh EDCA Configuration */ 116/* */ 117/* */ 118#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 119 120/* */ 121/* */ 122/* 0x0600h ~ 0x07FFh WMAC Configuration */ 123/* */ 124/* */ 125 126/* */ 127/* SDIO Bus Specification */ 128/* */ 129 130/* */ 131/* SDIO CMD Address Mapping */ 132/* */ 133 134/* */ 135/* I/O bus domain (Host) */ 136/* */ 137 138/* */ 139/* SDIO register */ 140/* */ 141#define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ 142 143/* */ 144/* 8723 Register Bit and Content definition */ 145/* */ 146 147/* 2 HSISR */ 148/* interrupt mask which needs to clear */ 149#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ 150 HSISR_SPS_OCP_INT |\ 151 HSISR_RON_INT |\ 152 HSISR_PDNINT |\ 153 HSISR_GPIO9_INT) 154 155/* */ 156/* */ 157/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 158/* */ 159/* */ 160 161/* */ 162/* */ 163/* 0x0200h ~ 0x027Fh TXDMA Configuration */ 164/* */ 165/* */ 166 167/* */ 168/* */ 169/* 0x0280h ~ 0x02FFh RXDMA Configuration */ 170/* */ 171/* */ 172#define BIT_USB_RXDMA_AGG_EN BIT(31) 173#define RXDMA_AGG_MODE_EN BIT(1) 174 175#ifdef CONFIG_WOWLAN 176#define RXPKT_RELEASE_POLL BIT(16) 177#define RXDMA_IDLE BIT(17) 178#define RW_RELEASE_EN BIT(18) 179#endif 180 181/* */ 182/* */ 183/* 0x0400h ~ 0x047Fh Protocol Configuration */ 184/* */ 185/* */ 186 187/* */ 188/* 8723B REG_CCK_CHECK (offset 0x454) */ 189/* */ 190#define BIT_BCN_PORT_SEL BIT5 191 192/* */ 193/* */ 194/* 0x0500h ~ 0x05FFh EDCA Configuration */ 195/* */ 196/* */ 197 198/* */ 199/* */ 200/* 0x0600h ~ 0x07FFh WMAC Configuration */ 201/* */ 202/* */ 203#define EEPROM_RF_GAIN_OFFSET 0xC1 204#define EEPROM_RF_GAIN_VAL 0x1F6 205 206/* */ 207/* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ 208/* */ 209#define IMR_DISABLED_8723B 0 210/* IMR DW0(0x00B0-00B3) Bit 0-31 */ 211#define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ 212#define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ 213#define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ 214#define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 215#define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 216#define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ 217#define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ 218#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 219#define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ 220#define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ 221#define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 222#define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 223#define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ 224#define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 225#define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 226#define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 227#define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ 228#define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ 229#define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ 230#define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ 231#define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ 232#define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ 233#define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ 234#define IMR_ROK_8723B BIT0 /* Receive DMA OK */ 235 236/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 237#define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ 238#define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ 239#define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ 240#define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ 241#define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ 242#define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ 243#define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ 244#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ 245#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ 246#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ 247#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ 248#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ 249#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ 250#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ 251#define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ 252#define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ 253#define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ 254#define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ 255#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ 256 257#endif 258