LXR linux/drivers/staging/rtlwifi/phydm/phydm

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2016  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * The full GNU General Public License is included in this distribution in the
  15 * file called LICENSE.
  16 *
  17 * Contact Information:
  18 * wlanfae <wlanfae@realtek.com>
  19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20 * Hsinchu 300, Taiwan.
  21 *
  22 * Larry Finger <Larry.Finger@lwfinger.net>
  23 *
  24 *****************************************************************************/
  25
  26#ifndef __HALHWOUTSRC_H__
  27#define __HALHWOUTSRC_H__
  28
  29/*--------------------------Define -------------------------------------------*/
  30#define CCK_RSSI_INIT_COUNT 5
  31
  32#define RA_RSSI_STATE_INIT 0
  33#define RA_RSSI_STATE_SEND 1
  34#define RA_RSSI_STATE_HOLD 2
  35
  36#define CFO_HW_RPT_2_MHZ(val) ((val << 1) + (val >> 1))
  37/* ((X* 3125)  / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1  */
  38
  39#define AGC_DIFF_CONFIG_MP(ic, band)                                           \
  40        (odm_read_and_config_mp_##ic##_agc_tab_diff(                           \
  41                dm, array_mp_##ic##_agc_tab_diff_##band,                       \
  42                sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
  43#define AGC_DIFF_CONFIG_TC(ic, band)                                           \
  44        (odm_read_and_config_tc_##ic##_agc_tab_diff(                           \
  45                dm, array_tc_##ic##_agc_tab_diff_##band,                       \
  46                sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
  47
  48#define AGC_DIFF_CONFIG(ic, band)                                              \
  49        do {                                                                   \
  50                if (dm->is_mp_chip)                                            \
  51                        AGC_DIFF_CONFIG_MP(ic, band);                          \
  52                else                                                           \
  53                        AGC_DIFF_CONFIG_TC(ic, band);                          \
  54        } while (0)
  55
  56/* ************************************************************
  57 * structure and define
  58 * *************************************************************/
  59
  60struct phy_rx_agc_info {
  61#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  62        u8 gain : 7, trsw : 1;
  63#else
  64        u8 trsw : 1, gain : 7;
  65#endif
  66};
  67
  68struct phy_status_rpt_8192cd {
  69        struct phy_rx_agc_info path_agc[2];
  70        u8 ch_corr[2];
  71        u8 cck_sig_qual_ofdm_pwdb_all;
  72        u8 cck_agc_rpt_ofdm_cfosho_a;
  73        u8 cck_rpt_b_ofdm_cfosho_b;
  74        u8 rsvd_1; /*ch_corr_msb;*/
  75        u8 noise_power_db_msb;
  76        s8 path_cfotail[2];
  77        u8 pcts_mask[2];
  78        s8 stream_rxevm[2];
  79        u8 path_rxsnr[2];
  80        u8 noise_power_db_lsb;
  81        u8 rsvd_2[3];
  82        u8 stream_csi[2];
  83        u8 stream_target_csi[2];
  84        s8 sig_evm;
  85        u8 rsvd_3;
  86
  87#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  88        u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
  89        u8 sgi_en : 1;
  90        u8 rxsc : 2;
  91        u8 idle_long : 1;
  92        u8 r_ant_train_en : 1;
  93        u8 ant_sel_b : 1;
  94        u8 ant_sel : 1;
  95#else /*_BIG_ENDIAN_    */
  96        u8 ant_sel : 1;
  97        u8 ant_sel_b : 1;
  98        u8 r_ant_train_en : 1;
  99        u8 idle_long : 1;
 100        u8 rxsc : 2;
 101        u8 sgi_en : 1;
 102        u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
 103#endif
 104};
 105
 106struct phy_status_rpt_8812 {
 107        /*      DWORD 0*/
 108        u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
 109        u8 chl_num_LSB; /*channel number[7:0]*/
 110#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 111        u8 chl_num_MSB : 2; /*channel number[9:8]*/
 112        u8 sub_chnl : 4; /*sub-channel location[3:0]*/
 113        u8 r_RFMOD : 2; /*RF mode[1:0]*/
 114#else /*_BIG_ENDIAN_    */
 115        u8 r_RFMOD : 2;
 116        u8 sub_chnl : 4;
 117        u8 chl_num_MSB : 2;
 118#endif
 119
 120        /*      DWORD 1*/
 121        u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/
 122        s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 */
 123/*CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
 124#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 125        /*this should be checked again
 126         *because the definition of 8812 and 8814 is different
 127         */
 128        u8 resvd_0 : 6;
 129        u8 bt_RF_ch_MSB : 2; /*8812A:2'b0, 8814A: bt rf channel keep[7:6]*/
 130#else /*_BIG_ENDIAN_*/
 131        u8 bt_RF_ch_MSB : 2;
 132        u8 resvd_0 : 6;
 133#endif
 134
 135/*      DWORD 2*/
 136#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 137        u8 ant_div_sw_a : 1; /*8812A: ant_div_sw_a, 8814A: 1'b0*/
 138        u8 ant_div_sw_b : 1; /*8812A: ant_div_sw_b, 8814A: 1'b0*/
 139        u8 bt_RF_ch_LSB : 6; /*8812A: 6'b0, 8814A: bt rf channel keep[5:0]*/
 140#else /*_BIG_ENDIAN_    */
 141        u8 bt_RF_ch_LSB : 6;
 142        u8 ant_div_sw_b : 1;
 143        u8 ant_div_sw_a : 1;
 144#endif
 145        s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2  path-A and path-B CFO tail*/
 146        u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
 147        u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
 148
 149        /*      DWORD 3*/
 150        s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2    stream 1 and stream 2 RX EVM*/
 151        s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0    path-A and path-B RX SNR*/
 152
 153        /*      DWORD 4*/
 154        u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
 155#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 156        u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
 157        u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
 158        u8 resvd_1 : 1; /*1'b0*/
 159#else /*_BIG_ENDIAN_*/
 160        u8 resvd_1 : 1;
 161        u8 pcts_rpt_valid : 1;
 162        u8 PCTS_MSK_RPT_3 : 6;
 163#endif
 164        s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 */
 165        /* 8812A: 16'b0, 8814A: stream 3 and stream 4 RX EVM*/
 166
 167        /*      DWORD 5*/
 168        u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 */
 169        /* 8812A: stream 1 and 2 CSI, 8814A: path-C and path-D RX SNR*/
 170        u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 */
 171        /* path-C and path-D {TRSW, gain[6:0] }*/
 172
 173        /*      DWORD 6*/
 174        s8 sigevm; /*signal field EVM*/
 175#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 176        u8 antidx_antc : 3; /*8812A: 3'b0       8814A: antidx_antc[2:0]*/
 177        u8 antidx_antd : 3; /*8812A: 3'b0       8814A: antidx_antd[2:0]*/
 178        u8 dpdt_ctrl_keep : 1; /*8812A: 1'b0    8814A: dpdt_ctrl_keep*/
 179        u8 GNT_BT_keep : 1; /*8812A: 1'b0       8814A: GNT_BT_keep*/
 180#else /*_BIG_ENDIAN_*/
 181        u8 GNT_BT_keep : 1;
 182        u8 dpdt_ctrl_keep : 1;
 183        u8 antidx_antd : 3;
 184        u8 antidx_antc : 3;
 185#endif
 186#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 187        u8 antidx_anta : 3; /*antidx_anta[2:0]*/
 188        u8 antidx_antb : 3; /*antidx_antb[2:0]*/
 189        u8 hw_antsw_occur : 2; /*1'b0*/
 190#else /*_BIG_ENDIAN_*/
 191        u8 hw_antsw_occur : 2;
 192        u8 antidx_antb : 3;
 193        u8 antidx_anta : 3;
 194#endif
 195};
 196
 197void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id);
 198
 199void odm_init_rssi_for_dm(struct phy_dm_struct *dm);
 200
 201void odm_phy_status_query(struct phy_dm_struct *dm,
 202                          struct dm_phy_status_info *phy_info, u8 *phy_status,
 203                          struct dm_per_pkt_info *pktinfo);
 204
 205void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
 206                          bool is_packet_match_bssid, bool is_packet_to_self,
 207                          bool is_packet_beacon);
 208
 209enum hal_status
 210odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm);
 211
 212enum hal_status
 213odm_config_rf_with_header_file(struct phy_dm_struct *dm,
 214                               enum odm_rf_config_type config_type,
 215                               enum odm_rf_radio_path e_rf_path);
 216
 217enum hal_status
 218odm_config_bb_with_header_file(struct phy_dm_struct *dm,
 219                               enum odm_bb_config_type config_type);
 220
 221enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm);
 222
 223enum hal_status
 224odm_config_fw_with_header_file(struct phy_dm_struct *dm,
 225                               enum odm_fw_config_type config_type,
 226                               u8 *p_firmware, u32 *size);
 227
 228u32 odm_get_hw_img_version(struct phy_dm_struct *dm);
 229
 230s32 odm_signal_scale_mapping(struct phy_dm_struct *dm, s32 curr_sig);
 231
 232/*For 8822B only!! need to move to FW finally */
 233/*==============================================*/
 234void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
 235                                  struct dm_per_pkt_info *pktinfo,
 236                                  struct dm_phy_status_info *phy_info);
 237
 238bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
 239                           u8 *p_data_rate, u8 *p_gid);
 240
 241struct phy_status_rpt_jaguar2_type0 {
 242        /* DW0 */
 243        u8 page_num;
 244        u8 pwdb;
 245#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 246        u8 gain : 6;
 247        u8 rsvd_0 : 1;
 248        u8 trsw : 1;
 249#else
 250        u8 trsw : 1;
 251        u8 rsvd_0 : 1;
 252        u8 gain : 6;
 253#endif
 254        u8 rsvd_1;
 255
 256        /* DW1 */
 257        u8 rsvd_2;
 258#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 259        u8 rxsc : 4;
 260        u8 agc_table : 4;
 261#else
 262        u8 agc_table : 4;
 263        u8 rxsc : 4;
 264#endif
 265        u8 channel;
 266        u8 band;
 267
 268        /* DW2 */
 269        u16 length;
 270#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 271        u8 antidx_a : 3;
 272        u8 antidx_b : 3;
 273        u8 rsvd_3 : 2;
 274        u8 antidx_c : 3;
 275        u8 antidx_d : 3;
 276        u8 rsvd_4 : 2;
 277#else
 278        u8 rsvd_3 : 2;
 279        u8 antidx_b : 3;
 280        u8 antidx_a : 3;
 281        u8 rsvd_4 : 2;
 282        u8 antidx_d : 3;
 283        u8 antidx_c : 3;
 284#endif
 285
 286        /* DW3 */
 287        u8 signal_quality;
 288#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 289        u8 vga : 5;
 290        u8 lna_l : 3;
 291        u8 bb_power : 6;
 292        u8 rsvd_9 : 1;
 293        u8 lna_h : 1;
 294#else
 295        u8 lna_l : 3;
 296        u8 vga : 5;
 297        u8 lna_h : 1;
 298        u8 rsvd_9 : 1;
 299        u8 bb_power : 6;
 300#endif
 301        u8 rsvd_5;
 302
 303        /* DW4 */
 304        u32 rsvd_6;
 305
 306        /* DW5 */
 307        u32 rsvd_7;
 308
 309        /* DW6 */
 310        u32 rsvd_8;
 311};
 312
 313struct phy_status_rpt_jaguar2_type1 {
 314        /* DW0 and DW1 */
 315        u8 page_num;
 316        u8 pwdb[4];
 317#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 318        u8 l_rxsc : 4;
 319        u8 ht_rxsc : 4;
 320#else
 321        u8 ht_rxsc : 4;
 322        u8 l_rxsc : 4;
 323#endif
 324        u8 channel;
 325#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 326        u8 band : 2;
 327        u8 rsvd_0 : 1;
 328        u8 hw_antsw_occu : 1;
 329        u8 gnt_bt : 1;
 330        u8 ldpc : 1;
 331        u8 stbc : 1;
 332        u8 beamformed : 1;
 333#else
 334        u8 beamformed : 1;
 335        u8 stbc : 1;
 336        u8 ldpc : 1;
 337        u8 gnt_bt : 1;
 338        u8 hw_antsw_occu : 1;
 339        u8 rsvd_0 : 1;
 340        u8 band : 2;
 341#endif
 342
 343        /* DW2 */
 344        u16 lsig_length;
 345#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 346        u8 antidx_a : 3;
 347        u8 antidx_b : 3;
 348        u8 rsvd_1 : 2;
 349        u8 antidx_c : 3;
 350        u8 antidx_d : 3;
 351        u8 rsvd_2 : 2;
 352#else
 353        u8 rsvd_1 : 2;
 354        u8 antidx_b : 3;
 355        u8 antidx_a : 3;
 356        u8 rsvd_2 : 2;
 357        u8 antidx_d : 3;
 358        u8 antidx_c : 3;
 359#endif
 360
 361        /* DW3 */
 362        u8 paid;
 363#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 364        u8 paid_msb : 1;
 365        u8 gid : 6;
 366        u8 rsvd_3 : 1;
 367#else
 368        u8 rsvd_3 : 1;
 369        u8 gid : 6;
 370        u8 paid_msb : 1;
 371#endif
 372        u8 intf_pos;
 373#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 374        u8 intf_pos_msb : 1;
 375        u8 rsvd_4 : 2;
 376        u8 nb_intf_flag : 1;
 377        u8 rf_mode : 2;
 378        u8 rsvd_5 : 2;
 379#else
 380        u8 rsvd_5 : 2;
 381        u8 rf_mode : 2;
 382        u8 nb_intf_flag : 1;
 383        u8 rsvd_4 : 2;
 384        u8 intf_pos_msb : 1;
 385#endif
 386
 387        /* DW4 */
 388        s8 rxevm[4]; /* s(8,1) */
 389
 390        /* DW5 */
 391        s8 cfo_tail[4]; /* s(8,7) */
 392
 393        /* DW6 */
 394        s8 rxsnr[4]; /* s(8,1) */
 395};
 396
 397struct phy_status_rpt_jaguar2_type2 {
 398        /* DW0 ane DW1 */
 399        u8 page_num;
 400        u8 pwdb[4];
 401#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 402        u8 l_rxsc : 4;
 403        u8 ht_rxsc : 4;
 404#else
 405        u8 ht_rxsc : 4;
 406        u8 l_rxsc : 4;
 407#endif
 408        u8 channel;
 409#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 410        u8 band : 2;
 411        u8 rsvd_0 : 1;
 412        u8 hw_antsw_occu : 1;
 413        u8 gnt_bt : 1;
 414        u8 ldpc : 1;
 415        u8 stbc : 1;
 416        u8 beamformed : 1;
 417#else
 418        u8 beamformed : 1;
 419        u8 stbc : 1;
 420        u8 ldpc : 1;
 421        u8 gnt_bt : 1;
 422        u8 hw_antsw_occu : 1;
 423        u8 rsvd_0 : 1;
 424        u8 band : 2;
 425#endif
 426
 427/* DW2 */
 428#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 429        u8 shift_l_map : 6;
 430        u8 rsvd_1 : 2;
 431#else
 432        u8 rsvd_1 : 2;
 433        u8 shift_l_map : 6;
 434#endif
 435        u8 cnt_pw2cca;
 436#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 437        u8 agc_table_a : 4;
 438        u8 agc_table_b : 4;
 439        u8 agc_table_c : 4;
 440        u8 agc_table_d : 4;
 441#else
 442        u8 agc_table_b : 4;
 443        u8 agc_table_a : 4;
 444        u8 agc_table_d : 4;
 445        u8 agc_table_c : 4;
 446#endif
 447
 448        /* DW3 ~ DW6*/
 449        u8 cnt_cca2agc_rdy;
 450#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 451        u8 gain_a : 6;
 452        u8 rsvd_2 : 1;
 453        u8 trsw_a : 1;
 454        u8 gain_b : 6;
 455        u8 rsvd_3 : 1;
 456        u8 trsw_b : 1;
 457        u8 gain_c : 6;
 458        u8 rsvd_4 : 1;
 459        u8 trsw_c : 1;
 460        u8 gain_d : 6;
 461        u8 rsvd_5 : 1;
 462        u8 trsw_d : 1;
 463        u8 aagc_step_a : 2;
 464        u8 aagc_step_b : 2;
 465        u8 aagc_step_c : 2;
 466        u8 aagc_step_d : 2;
 467#else
 468        u8 trsw_a : 1;
 469        u8 rsvd_2 : 1;
 470        u8 gain_a : 6;
 471        u8 trsw_b : 1;
 472        u8 rsvd_3 : 1;
 473        u8 gain_b : 6;
 474        u8 trsw_c : 1;
 475        u8 rsvd_4 : 1;
 476        u8 gain_c : 6;
 477        u8 trsw_d : 1;
 478        u8 rsvd_5 : 1;
 479        u8 gain_d : 6;
 480        u8 aagc_step_d : 2;
 481        u8 aagc_step_c : 2;
 482        u8 aagc_step_b : 2;
 483        u8 aagc_step_a : 2;
 484#endif
 485        u8 ht_aagc_gain[4];
 486        u8 dagc_gain[4];
 487#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 488        u8 counter : 6;
 489        u8 rsvd_6 : 2;
 490        u8 syn_count : 5;
 491        u8 rsvd_7 : 3;
 492#else
 493        u8 rsvd_6 : 2;
 494        u8 counter : 6;
 495        u8 rsvd_7 : 3;
 496        u8 syn_count : 5;
 497#endif
 498};
 499
 500u32 query_phydm_trx_capability(struct phy_dm_struct *dm);
 501
 502u32 query_phydm_stbc_capability(struct phy_dm_struct *dm);
 503
 504u32 query_phydm_ldpc_capability(struct phy_dm_struct *dm);
 505
 506u32 query_phydm_txbf_parameters(struct phy_dm_struct *dm);
 507
 508u32 query_phydm_txbf_capability(struct phy_dm_struct *dm);
 509
 510#endif /*#ifndef        __HALHWOUTSRC_H__*/
 511