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26#include "../wifi.h"
27#include "../efuse.h"
28#include "../base.h"
29#include "../regd.h"
30#include "../cam.h"
31#include "../ps.h"
32#include "../pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "fw.h"
37#include "led.h"
38#include "hw.h"
39
40#define LLT_CONFIG 5
41
42u8 rtl_channel5g[CHANNEL_MAX_NUMBER_5G] = {
43 36, 38, 40, 42, 44, 46, 48,
44 52, 54, 56, 58, 60, 62, 64,
45 100, 102, 104, 106, 108, 110, 112,
46 116, 118, 120, 122, 124, 126, 128,
47 132, 134, 136, 138, 140, 142, 144,
48 149, 151, 153, 155, 157, 159, 161,
49 165, 167, 169, 171, 173, 175, 177};
50u8 rtl_channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122,
51 138, 155, 171};
52
53static void _rtl8822be_set_bcn_ctrl_reg(struct ieee80211_hw *hw, u8 set_bits,
54 u8 clear_bits)
55{
56 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
57 struct rtl_priv *rtlpriv = rtl_priv(hw);
58
59 rtlpci->reg_bcn_ctrl_val |= set_bits;
60 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
61
62 rtl_write_byte(rtlpriv, REG_BCN_CTRL_8822B,
63 (u8)rtlpci->reg_bcn_ctrl_val);
64}
65
66static void _rtl8822be_stop_tx_beacon(struct ieee80211_hw *hw)
67{
68 struct rtl_priv *rtlpriv = rtl_priv(hw);
69 u8 tmp;
70
71 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
72 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2, tmp & (~BIT(6)));
73 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 1, 0x64);
74 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2);
75 tmp &= ~(BIT(0));
76 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2, tmp);
77}
78
79static void _rtl8822be_resume_tx_beacon(struct ieee80211_hw *hw)
80{
81 struct rtl_priv *rtlpriv = rtl_priv(hw);
82 u8 tmp;
83
84 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
85 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2, tmp | BIT(6));
86 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 1, 0xff);
87 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2);
88 tmp |= BIT(0);
89 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2, tmp);
90}
91
92static void _rtl8822be_enable_bcn_sub_func(struct ieee80211_hw *hw)
93{
94 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(1));
95}
96
97static void _rtl8822be_disable_bcn_sub_func(struct ieee80211_hw *hw)
98{
99 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(1), 0);
100}
101
102static void _rtl8822be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
103 bool b_need_turn_off_ckk)
104{
105 struct rtl_priv *rtlpriv = rtl_priv(hw);
106 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
107 u32 count = 0, isr_regaddr, content;
108 bool b_schedule_timer = b_need_turn_off_ckk;
109
110 if (!rtlhal->fw_ready)
111 return;
112 if (!rtlpriv->psc.fw_current_inpsmode)
113 return;
114
115 while (1) {
116 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
117 if (rtlhal->fw_clk_change_in_progress) {
118 while (rtlhal->fw_clk_change_in_progress) {
119 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
120 count++;
121 udelay(100);
122 if (count > 1000)
123 return;
124 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
125 }
126 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
127 } else {
128 rtlhal->fw_clk_change_in_progress = false;
129 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
130 break;
131 }
132 }
133
134 if (IS_IN_LOW_POWER_STATE_8822B(rtlhal->fw_ps_state)) {
135 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
136 (u8 *)(&rpwm_val));
137 if (FW_PS_IS_ACK(rpwm_val)) {
138 isr_regaddr = REG_HISR0_8822B;
139 content = rtl_read_dword(rtlpriv, isr_regaddr);
140 while (!(content & IMR_CPWM) && (count < 500)) {
141 udelay(50);
142 count++;
143 content = rtl_read_dword(rtlpriv, isr_regaddr);
144 }
145
146 if (content & IMR_CPWM) {
147 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
148 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8822B;
149 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
150 "Receive CPWM INT!!! PSState = %X\n",
151 rtlhal->fw_ps_state);
152 }
153 }
154
155 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
156 rtlhal->fw_clk_change_in_progress = false;
157 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
158 if (b_schedule_timer) {
159 mod_timer(&rtlpriv->works.fw_clockoff_timer,
160 jiffies + MSECS(10));
161 }
162
163 } else {
164 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
165 rtlhal->fw_clk_change_in_progress = false;
166 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
167 }
168}
169
170static void _rtl8822be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
171{
172 struct rtl_priv *rtlpriv = rtl_priv(hw);
173 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
174 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
175 struct rtl8192_tx_ring *ring;
176 enum rf_pwrstate rtstate;
177 bool b_schedule_timer = false;
178 u8 queue;
179
180 if (!rtlhal->fw_ready)
181 return;
182 if (!rtlpriv->psc.fw_current_inpsmode)
183 return;
184 if (!rtlhal->allow_sw_to_change_hwclc)
185 return;
186
187 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
188 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
189 return;
190
191 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
192 ring = &rtlpci->tx_ring[queue];
193 if (skb_queue_len(&ring->queue)) {
194 b_schedule_timer = true;
195 break;
196 }
197 }
198
199 if (b_schedule_timer) {
200 mod_timer(&rtlpriv->works.fw_clockoff_timer,
201 jiffies + MSECS(10));
202 return;
203 }
204
205 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
206 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
207 if (!rtlhal->fw_clk_change_in_progress) {
208 rtlhal->fw_clk_change_in_progress = true;
209 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
210 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
211 rtl_write_word(rtlpriv, REG_HISR0_8822B, 0x0100);
212 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
213 (u8 *)(&rpwm_val));
214 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
215 rtlhal->fw_clk_change_in_progress = false;
216 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
217 } else {
218 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
219 mod_timer(&rtlpriv->works.fw_clockoff_timer,
220 jiffies + MSECS(10));
221 }
222 }
223}
224
225static void _rtl8822be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
226{
227 u8 rpwm_val = 0;
228
229 rpwm_val |= (FW_PS_STATE_RF_OFF_8822B | FW_PS_ACK);
230 _rtl8822be_set_fw_clock_on(hw, rpwm_val, true);
231}
232
233static void _rtl8822be_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
234{
235 u8 rpwm_val = 0;
236
237 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
238 _rtl8822be_set_fw_clock_off(hw, rpwm_val);
239}
240
241void rtl8822be_fw_clk_off_timer_callback(unsigned long data)
242{
243 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
244
245 _rtl8822be_set_fw_ps_rf_off_low_power(hw);
246}
247
248static void _rtl8822be_fwlps_leave(struct ieee80211_hw *hw)
249{
250 struct rtl_priv *rtlpriv = rtl_priv(hw);
251 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
252 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
253 bool fw_current_inps = false;
254 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
255
256 if (ppsc->low_power_enable) {
257 rpwm_val = (FW_PS_STATE_ALL_ON_8822B | FW_PS_ACK);
258 _rtl8822be_set_fw_clock_on(hw, rpwm_val, false);
259 rtlhal->allow_sw_to_change_hwclc = false;
260 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
261 (u8 *)(&fw_pwrmode));
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
263 (u8 *)(&fw_current_inps));
264 } else {
265 rpwm_val = FW_PS_STATE_ALL_ON_8822B;
266 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
267 (u8 *)(&rpwm_val));
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
269 (u8 *)(&fw_pwrmode));
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
271 (u8 *)(&fw_current_inps));
272 }
273}
274
275static void _rtl8822be_fwlps_enter(struct ieee80211_hw *hw)
276{
277 struct rtl_priv *rtlpriv = rtl_priv(hw);
278 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
279 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
280 bool fw_current_inps = true;
281 u8 rpwm_val;
282
283 if (ppsc->low_power_enable) {
284 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;
285 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
286 (u8 *)(&fw_current_inps));
287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
288 (u8 *)(&ppsc->fwctrl_psmode));
289 rtlhal->allow_sw_to_change_hwclc = true;
290 _rtl8822be_set_fw_clock_off(hw, rpwm_val);
291 } else {
292 rpwm_val = FW_PS_STATE_RF_OFF_8822B;
293 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
294 (u8 *)(&fw_current_inps));
295 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
296 (u8 *)(&ppsc->fwctrl_psmode));
297 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
298 (u8 *)(&rpwm_val));
299 }
300}
301
302void rtl8822be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
303{
304 struct rtl_priv *rtlpriv = rtl_priv(hw);
305 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
306 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
307
308 switch (variable) {
309 case HW_VAR_RCR:
310 *((u32 *)(val)) = rtlpci->receive_config;
311 break;
312 case HW_VAR_RF_STATE:
313 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
314 break;
315 case HW_VAR_FWLPS_RF_ON: {
316 enum rf_pwrstate rf_state;
317 u32 val_rcr;
318
319 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
320 (u8 *)(&rf_state));
321 if (rf_state == ERFOFF) {
322 *((bool *)(val)) = true;
323 } else {
324 val_rcr = rtl_read_dword(rtlpriv, REG_RCR_8822B);
325 val_rcr &= 0x00070000;
326 if (val_rcr)
327 *((bool *)(val)) = false;
328 else
329 *((bool *)(val)) = true;
330 }
331 } break;
332 case HW_VAR_FW_PSMODE_STATUS:
333 *((bool *)(val)) = ppsc->fw_current_inpsmode;
334 break;
335 case HW_VAR_CORRECT_TSF: {
336 u64 tsf;
337 u32 *ptsf_low = (u32 *)&tsf;
338 u32 *ptsf_high = ((u32 *)&tsf) + 1;
339
340 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR_8822B + 4));
341 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR_8822B);
342
343 *((u64 *)(val)) = tsf;
344
345 } break;
346 default:
347 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
348 "switch case not process %x\n", variable);
349 break;
350 }
351}
352
353static void _rtl8822be_download_rsvd_page(struct ieee80211_hw *hw)
354{
355 struct rtl_priv *rtlpriv = rtl_priv(hw);
356 u8 tmp_regcr, tmp_reg422;
357 u8 bcnvalid_reg ;
358 u8 count = 0, dlbcn_count = 0;
359 bool b_recover = false;
360
361
362 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR_8822B + 1);
363 rtl_write_byte(rtlpriv, REG_CR_8822B + 1, tmp_regcr | BIT(0));
364
365
366
367
368
369
370 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(3));
371 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(4), 0);
372
373
374
375
376 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
377 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2,
378 tmp_reg422 & (~BIT(6)));
379
380 if (tmp_reg422 & BIT(6))
381 b_recover = true;
382
383 do {
384
385 bcnvalid_reg =
386 rtl_read_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
387 bcnvalid_reg = bcnvalid_reg | BIT(7);
388 rtl_write_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1,
389 bcnvalid_reg);
390
391
392 rtl8822be_set_fw_rsvdpagepkt(hw, false);
393
394
395 bcnvalid_reg =
396 rtl_read_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
397
398 count = 0;
399 while (!(BIT(7) & bcnvalid_reg) && count < 20) {
400 count++;
401 udelay(50);
402 bcnvalid_reg = rtl_read_byte(
403 rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
404 }
405
406 dlbcn_count++;
407 } while (!(BIT(7) & bcnvalid_reg) && dlbcn_count < 5);
408
409 if (!(BIT(7) & bcnvalid_reg))
410 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
411 "Download RSVD page failed!\n");
412
413
414 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
415 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(4));
416
417 if (b_recover)
418 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2,
419 tmp_reg422);
420}
421
422void rtl8822be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
423{
424 struct rtl_priv *rtlpriv = rtl_priv(hw);
425 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
426 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
427 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
428 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
429
430 switch (variable) {
431 case HW_VAR_ETHER_ADDR:
432 rtlpriv->halmac.ops->halmac_set_mac_address(rtlpriv, 0, val);
433 break;
434 case HW_VAR_BASIC_RATE: {
435 u16 b_rate_cfg = ((u16 *)val)[0];
436
437 b_rate_cfg = b_rate_cfg & 0x15f;
438 b_rate_cfg |= 0x01;
439 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
440 rtl_write_byte(rtlpriv, REG_RRSR_8822B, b_rate_cfg & 0xff);
441 rtl_write_byte(rtlpriv, REG_RRSR_8822B + 1,
442 (b_rate_cfg >> 8) & 0xff);
443 } break;
444 case HW_VAR_BSSID:
445 rtlpriv->halmac.ops->halmac_set_bssid(rtlpriv, 0, val);
446 break;
447 case HW_VAR_SIFS:
448 rtl_write_byte(rtlpriv, REG_SIFS_8822B + 1, val[0]);
449 rtl_write_byte(rtlpriv, REG_SIFS_TRX_8822B + 1, val[1]);
450
451 rtl_write_byte(rtlpriv, REG_SPEC_SIFS_8822B + 1, val[0]);
452 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS_8822B + 1, val[0]);
453
454 if (!mac->ht_enable)
455 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM_8822B,
456 0x0e0e);
457 else
458 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM_8822B,
459 *((u16 *)val));
460 break;
461 case HW_VAR_SLOT_TIME: {
462 u8 e_aci;
463
464 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE, "HW_VAR_SLOT_TIME %x\n",
465 val[0]);
466
467 rtl_write_byte(rtlpriv, REG_SLOT_8822B, val[0]);
468
469 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
470 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
471 (u8 *)(&e_aci));
472 }
473 } break;
474 case HW_VAR_ACK_PREAMBLE: {
475 u8 reg_tmp;
476 u8 short_preamble = (bool)(*(u8 *)val);
477
478 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
479 if (short_preamble)
480 reg_tmp |= 0x80;
481 rtl_write_byte(rtlpriv, REG_RRSR_8822B + 2, reg_tmp);
482 rtlpriv->mac80211.short_preamble = short_preamble;
483 } break;
484 case HW_VAR_WPA_CONFIG:
485 rtl_write_byte(rtlpriv, REG_SECCFG_8822B, *((u8 *)val));
486 break;
487 case HW_VAR_AMPDU_FACTOR: {
488 u32 ampdu_len = (*((u8 *)val));
489
490 ampdu_len = (0x2000 << ampdu_len) - 1;
491 rtl_write_dword(rtlpriv, REG_AMPDU_MAX_LENGTH_8822B, ampdu_len);
492 } break;
493 case HW_VAR_AC_PARAM: {
494 u8 e_aci = *((u8 *)val);
495
496 if (mac->vif && mac->vif->bss_conf.assoc && !mac->act_scanning)
497 rtl8822be_set_qos(hw, e_aci);
498
499 if (rtlpci->acm_method != EACMWAY2_SW)
500 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
501 (u8 *)(&e_aci));
502 } break;
503 case HW_VAR_ACM_CTRL: {
504 u8 e_aci = *((u8 *)val);
505 union aci_aifsn *aifs = (union aci_aifsn *)&mac->ac[0].aifs;
506
507 u8 acm = aifs->f.acm;
508 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL_8822B);
509
510 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
511
512 if (acm) {
513 switch (e_aci) {
514 case AC0_BE:
515 acm_ctrl |= ACMHW_BEQ_EN;
516 break;
517 case AC2_VI:
518 acm_ctrl |= ACMHW_VIQ_EN;
519 break;
520 case AC3_VO:
521 acm_ctrl |= ACMHW_VOQ_EN;
522 break;
523 default:
524 RT_TRACE(
525 rtlpriv, COMP_ERR, DBG_WARNING,
526 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
527 acm);
528 break;
529 }
530 } else {
531 switch (e_aci) {
532 case AC0_BE:
533 acm_ctrl &= (~ACMHW_BEQ_EN);
534 break;
535 case AC2_VI:
536 acm_ctrl &= (~ACMHW_VIQ_EN);
537 break;
538 case AC3_VO:
539 acm_ctrl &= (~ACMHW_VOQ_EN);
540 break;
541 default:
542 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
543 "switch case not process\n");
544 break;
545 }
546 }
547
548 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
549 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
550 acm_ctrl);
551 rtl_write_byte(rtlpriv, REG_ACMHWCTRL_8822B, acm_ctrl);
552 } break;
553 case HW_VAR_RCR: {
554 rtl_write_dword(rtlpriv, REG_RCR_8822B, ((u32 *)(val))[0]);
555 rtlpci->receive_config = ((u32 *)(val))[0];
556 } break;
557 case HW_VAR_RETRY_LIMIT: {
558 u8 retry_limit = ((u8 *)(val))[0];
559
560 rtl_write_word(rtlpriv, REG_RETRY_LIMIT_8822B,
561 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
562 retry_limit << RETRY_LIMIT_LONG_SHIFT);
563 } break;
564 case HW_VAR_DUAL_TSF_RST:
565 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST_8822B,
566 (BIT(0) | BIT(1)));
567 break;
568 case HW_VAR_EFUSE_BYTES:
569 efuse->efuse_usedbytes = *((u16 *)val);
570 break;
571 case HW_VAR_EFUSE_USAGE:
572 efuse->efuse_usedpercentage = *((u8 *)val);
573 break;
574 case HW_VAR_IO_CMD:
575 rtl8822be_phy_set_io_cmd(hw, (*(enum io_type *)val));
576 break;
577 case HW_VAR_SET_RPWM:
578 break;
579 case HW_VAR_H2C_FW_PWRMODE:
580 rtl8822be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
581 break;
582 case HW_VAR_FW_PSMODE_STATUS:
583 ppsc->fw_current_inpsmode = *((bool *)val);
584 break;
585 case HW_VAR_RESUME_CLK_ON:
586 _rtl8822be_set_fw_ps_rf_on(hw);
587 break;
588 case HW_VAR_FW_LPS_ACTION: {
589 bool b_enter_fwlps = *((bool *)val);
590
591 if (b_enter_fwlps)
592 _rtl8822be_fwlps_enter(hw);
593 else
594 _rtl8822be_fwlps_leave(hw);
595 } break;
596 case HW_VAR_H2C_FW_JOINBSSRPT: {
597 u8 mstatus = (*(u8 *)val);
598
599 if (mstatus == RT_MEDIA_CONNECT) {
600 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
601 _rtl8822be_download_rsvd_page(hw);
602 }
603 rtl8822be_set_default_port_id_cmd(hw);
604 rtl8822be_set_fw_media_status_rpt_cmd(hw, mstatus);
605 } break;
606 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
607 rtl8822be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
608 break;
609 case HW_VAR_AID: {
610 u16 u2btmp;
611
612 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT_8822B);
613 u2btmp &= 0xC000;
614 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT_8822B,
615 (u2btmp | mac->assoc_id));
616 } break;
617 case HW_VAR_CORRECT_TSF: {
618 u8 btype_ibss = ((u8 *)(val))[0];
619
620 if (btype_ibss)
621 _rtl8822be_stop_tx_beacon(hw);
622
623 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(3));
624
625 rtl_write_dword(rtlpriv, REG_TSFTR_8822B,
626 (u32)(mac->tsf & 0xffffffff));
627 rtl_write_dword(rtlpriv, REG_TSFTR_8822B + 4,
628 (u32)((mac->tsf >> 32) & 0xffffffff));
629
630 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
631
632 if (btype_ibss)
633 _rtl8822be_resume_tx_beacon(hw);
634 } break;
635 case HW_VAR_KEEP_ALIVE: {
636 u8 array[2];
637
638 array[0] = 0xff;
639 array[1] = *((u8 *)val);
640 rtl8822be_fill_h2c_cmd(hw, H2C_8822B_KEEP_ALIVE_CTRL, 2, array);
641 } break;
642 default:
643 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
644 "switch case not process %x\n", variable);
645 break;
646 }
647}
648
649static void _rtl8822be_gen_refresh_led_state(struct ieee80211_hw *hw)
650{
651 struct rtl_priv *rtlpriv = rtl_priv(hw);
652 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
653 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
654 struct rtl_led *led0 = &pcipriv->ledctl.sw_led0;
655
656 if (rtlpriv->rtlhal.up_first_time)
657 return;
658
659 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
660 rtl8822be_sw_led_on(hw, led0);
661 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
662 rtl8822be_sw_led_on(hw, led0);
663 else
664 rtl8822be_sw_led_off(hw, led0);
665}
666
667static bool _rtl8822be_init_trxbd(struct ieee80211_hw *hw)
668{
669 struct rtl_priv *rtlpriv = rtl_priv(hw);
670 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
671
672
673 u8 bytetmp;
674
675 u32 dwordtmp;
676
677
678 if (!rtlpriv->cfg->mod_params->dma64)
679 goto dma64_end;
680
681 rtl_write_dword(rtlpriv, REG_H2CQ_TXBD_DESA_8822B + 4,
682 ((u64)rtlpci->tx_ring[H2C_QUEUE].buffer_desc_dma) >>
683 32);
684 rtl_write_dword(rtlpriv, REG_BCNQ_TXBD_DESA_8822B + 4,
685 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >>
686 32);
687 rtl_write_dword(rtlpriv, REG_MGQ_TXBD_DESA_8822B + 4,
688 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma >> 32);
689 rtl_write_dword(rtlpriv, REG_VOQ_TXBD_DESA_8822B + 4,
690 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma >> 32);
691 rtl_write_dword(rtlpriv, REG_VIQ_TXBD_DESA_8822B + 4,
692 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma >> 32);
693 rtl_write_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B + 4,
694 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma >> 32);
695 rtl_write_dword(rtlpriv, REG_BKQ_TXBD_DESA_8822B + 4,
696 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma >> 32);
697 rtl_write_dword(rtlpriv, REG_HI0Q_TXBD_DESA_8822B + 4,
698 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma >> 32);
699
700 rtl_write_dword(rtlpriv, REG_RXQ_RXBD_DESA_8822B + 4,
701 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma >> 32);
702
703dma64_end:
704
705 rtl_write_dword(rtlpriv, REG_H2CQ_TXBD_DESA_8822B,
706 ((u64)rtlpci->tx_ring[H2C_QUEUE].buffer_desc_dma) &
707 DMA_BIT_MASK(32));
708 rtl_write_dword(rtlpriv, REG_BCNQ_TXBD_DESA_8822B,
709 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
710 DMA_BIT_MASK(32));
711 rtl_write_dword(rtlpriv, REG_MGQ_TXBD_DESA_8822B,
712 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
713 DMA_BIT_MASK(32));
714 rtl_write_dword(rtlpriv, REG_VOQ_TXBD_DESA_8822B,
715 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
716 DMA_BIT_MASK(32));
717 rtl_write_dword(rtlpriv, REG_VIQ_TXBD_DESA_8822B,
718 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
719 DMA_BIT_MASK(32));
720 rtl_write_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B,
721 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
722 DMA_BIT_MASK(32));
723 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B);
724 rtl_write_dword(rtlpriv, REG_BKQ_TXBD_DESA_8822B,
725 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
726 DMA_BIT_MASK(32));
727 rtl_write_dword(rtlpriv, REG_HI0Q_TXBD_DESA_8822B,
728 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
729 DMA_BIT_MASK(32));
730
731 rtl_write_dword(rtlpriv, REG_RXQ_RXBD_DESA_8822B,
732 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
733 DMA_BIT_MASK(32));
734
735
736 rtl_write_dword(rtlpriv, REG_BD_RWPTR_CLR_8822B, 0x3fffffff);
737
738
739 dwordtmp = rtl_read_dword(rtlpriv, REG_H2CQ_CSR_8822B);
740 rtl_write_dword(rtlpriv, REG_H2CQ_CSR_8822B,
741 (dwordtmp | BIT(8) | BIT(16)));
742
743 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 3);
744 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 3, bytetmp | 0xF7);
745
746 rtl_write_dword(rtlpriv, REG_INT_MIG_8822B, 0);
747
748 rtl_write_dword(rtlpriv, REG_MCUTST_I_8822B, 0x0);
749
750 rtl_write_word(rtlpriv, REG_H2CQ_TXBD_NUM_8822B,
751 TX_DESC_NUM_8822B |
752 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
753 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM_8822B,
754 TX_DESC_NUM_8822B |
755 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
756 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM_8822B,
757 TX_DESC_NUM_8822B |
758 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
759 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM_8822B,
760 TX_DESC_NUM_8822B |
761 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
762 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM_8822B,
763 TX_DESC_NUM_8822B |
764 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
765 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM_8822B,
766 TX_DESC_NUM_8822B |
767 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
768 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM_8822B,
769 TX_DESC_NUM_8822B |
770 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
771 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM_8822B,
772 TX_DESC_NUM_8822B |
773 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
774 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM_8822B,
775 TX_DESC_NUM_8822B |
776 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
777 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM_8822B,
778 TX_DESC_NUM_8822B |
779 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
780 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM_8822B,
781 TX_DESC_NUM_8822B |
782 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
783 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM_8822B,
784 TX_DESC_NUM_8822B |
785 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
786 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM_8822B,
787 TX_DESC_NUM_8822B |
788 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
789 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM_8822B,
790 TX_DESC_NUM_8822B |
791 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
792 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM_8822B,
793 TX_DESC_NUM_8822B |
794 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
795
796 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM_8822B,
797 RX_DESC_NUM_8822BE |
798 ((RTL8822BE_SEG_NUM << 13) & 0x6000) | 0x8000);
799
800 rtl_write_dword(rtlpriv, REG_BD_RWPTR_CLR_8822B, 0XFFFFFFFF);
801
802 _rtl8822be_gen_refresh_led_state(hw);
803
804 return true;
805}
806
807static void _rtl8822be_enable_aspm_back_door(struct ieee80211_hw *hw)
808{
809 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
810 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
811 u8 tmp;
812
813 if (!ppsc->support_backdoor)
814 return;
815
816 pci_read_config_byte(rtlpci->pdev, 0x70f, &tmp);
817 pci_write_config_byte(rtlpci->pdev, 0x70f, tmp | BIT(7));
818
819 pci_read_config_byte(rtlpci->pdev, 0x719, &tmp);
820 pci_write_config_byte(rtlpci->pdev, 0x719, tmp | BIT(3) | BIT(4));
821}
822
823void rtl8822be_enable_hw_security_config(struct ieee80211_hw *hw)
824{
825 struct rtl_priv *rtlpriv = rtl_priv(hw);
826 u8 sec_reg_value;
827 u8 tmp;
828
829 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
830 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
831 rtlpriv->sec.pairwise_enc_algorithm,
832 rtlpriv->sec.group_enc_algorithm);
833
834 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
835 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
836 "not open hw encryption\n");
837 return;
838 }
839
840 sec_reg_value = SCR_TX_ENC_ENABLE | SRC_RX_DEC_ENABLE;
841
842 if (rtlpriv->sec.use_defaultkey) {
843 sec_reg_value |= SCR_TX_USE_DK;
844 sec_reg_value |= SCR_RX_USE_DK;
845 }
846
847 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
848
849 tmp = rtl_read_byte(rtlpriv, REG_CR_8822B + 1);
850 rtl_write_byte(rtlpriv, REG_CR_8822B + 1, tmp | BIT(1));
851
852 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "The SECR-value %x\n",
853 sec_reg_value);
854
855 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
856}
857
858static bool _rtl8822be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
859{
860 u8 tmp;
861
862
863 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3);
864 if (!(tmp & BIT(2))) {
865 rtl_write_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3,
866 (tmp | BIT(2)));
867 mdelay(100);
868 }
869
870
871
872
873 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3);
874 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
875 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
876 "CheckPcieDMAHang8822BE(): true!!\n");
877 return true;
878 } else {
879 return false;
880 }
881}
882
883static void _rtl8822be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
884 bool mac_power_on)
885{
886 u8 tmp;
887 bool release_mac_rx_pause;
888 u8 backup_pcie_dma_pause;
889
890 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
891 "ResetPcieInterfaceDMA8822BE()\n");
892
893
894
895
896
897
898
899
900
901
902 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL_8822B);
903 tmp &= ~(BIT(1) | BIT(0));
904 rtl_write_byte(rtlpriv, REG_RSV_CTRL_8822B, tmp);
905 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B);
906 tmp |= BIT(2);
907 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B, tmp);
908
909
910
911
912
913 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL_8822B);
914 if (tmp & BIT(2)) {
915
916 release_mac_rx_pause = false;
917 } else {
918 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL_8822B,
919 (tmp | BIT(2)));
920 release_mac_rx_pause = true;
921 }
922
923 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1);
924 if (backup_pcie_dma_pause != 0xFF)
925 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1, 0xFF);
926
927 if (mac_power_on) {
928
929
930
931 rtl_write_byte(rtlpriv, REG_CR_8822B, 0);
932 }
933
934
935
936
937 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1);
938 tmp &= ~(BIT(0));
939 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1, tmp);
940
941
942
943
944 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1);
945 tmp |= BIT(0);
946 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1, tmp);
947
948 if (mac_power_on) {
949
950
951
952 rtl_write_byte(rtlpriv, REG_CR_8822B, 0xFF);
953
954
955
956
957
958 }
959
960
961
962
963 tmp = rtl_read_byte(rtlpriv, REG_SYS_STATUS2_8822B + 2);
964 tmp |= BIT(1);
965 rtl_write_byte(rtlpriv, REG_SYS_STATUS2_8822B + 2, tmp);
966
967
968
969
970
971
972 if (!mac_power_on) {
973
974
975
976
977 if (release_mac_rx_pause) {
978 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL_8822B);
979 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL_8822B,
980 (tmp & (~BIT(2))));
981 }
982 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1,
983 backup_pcie_dma_pause);
984 }
985
986
987
988
989 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B);
990 tmp &= ~(BIT(2));
991 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B, tmp);
992}
993
994int rtl8822be_hw_init(struct ieee80211_hw *hw)
995{
996 struct rtl_priv *rtlpriv = rtl_priv(hw);
997 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
998 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
999 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1000 struct rtl_phy *rtlphy = &rtlpriv->phy;
1001 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1002 int err = 0;
1003 u8 tmp_u1b;
1004
1005 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8822BE hw init\n");
1006 rtlpriv->rtlhal.being_init_adapter = true;
1007 rtlpriv->intf_ops->disable_aspm(hw);
1008
1009 if (_rtl8822be_check_pcie_dma_hang(rtlpriv)) {
1010 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "8822be dma hang!\n");
1011 _rtl8822be_reset_pcie_interface_dma(rtlpriv,
1012 rtlhal->mac_func_enable);
1013 rtlhal->mac_func_enable = false;
1014 }
1015
1016
1017 _rtl8822be_init_trxbd(hw);
1018
1019
1020 err = rtlpriv->halmac.ops->halmac_init_hal(rtlpriv);
1021 if (err) {
1022 pr_err("halmac_init_hal failed\n");
1023 rtlhal->fw_ready = false;
1024 return err;
1025 }
1026
1027 rtlhal->fw_ready = true;
1028
1029
1030 tmp_u1b = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 2);
1031 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 2, (tmp_u1b | BIT(4)));
1032
1033
1034 rtlhal->rx_tag = 0;
1035
1036 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ_8822B, 0x4);
1037
1038
1039 ppsc->fw_current_inpsmode = false;
1040 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8822B;
1041 rtlhal->fw_clk_change_in_progress = false;
1042 rtlhal->allow_sw_to_change_hwclc = false;
1043 rtlhal->last_hmeboxnum = 0;
1044
1045 rtlphy->rfreg_chnlval[0] =
1046 rtl_get_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK);
1047 rtlphy->rfreg_chnlval[1] =
1048 rtl_get_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK);
1049 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1050 RFREG_OFFSET_MASK);
1051 rtlphy->rfreg_chnlval[0] =
1052 (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) | BIT(10) | BIT(11);
1053
1054 rtlhal->mac_func_enable = true;
1055
1056 if (rtlpriv->cfg->ops->get_btc_status())
1057 rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
1058
1059
1060 rtl_cam_reset_all_entry(hw);
1061 rtl8822be_enable_hw_security_config(hw);
1062
1063
1064 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1065 rtl_write_dword(rtlpriv, REG_RCR_8822B, rtlpci->receive_config);
1066
1067
1068 rtl_write_word(rtlpriv, REG_RXFLTMAP1_8822B, 0);
1069
1070 ppsc->rfpwr_state = ERFON;
1071
1072 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1073 _rtl8822be_enable_aspm_back_door(hw);
1074 rtlpriv->intf_ops->enable_aspm(hw);
1075
1076 if (rtlpriv->cfg->ops->get_btc_status())
1077 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
1078 else
1079 rtlpriv->btcoexist.btc_ops->btc_init_hw_config_wifi_only(
1080 rtlpriv);
1081
1082 rtlpriv->rtlhal.being_init_adapter = false;
1083
1084 rtlpriv->phydm.ops->phydm_init_dm(rtlpriv);
1085
1086
1087 rtl_write_dword(rtlpriv, REG_HISR0_8822B,
1088 rtl_read_dword(rtlpriv, REG_HISR0_8822B));
1089
1090 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "end of Rtl8822BE hw init %x\n",
1091 err);
1092 return 0;
1093}
1094
1095static u32 _rtl8822be_read_chip_version(struct ieee80211_hw *hw)
1096{
1097 struct rtl_priv *rtlpriv = rtl_priv(hw);
1098 struct rtl_phy *rtlphy = &rtlpriv->phy;
1099
1100 u32 version;
1101 u32 value32;
1102
1103 rtlphy->rf_type = RF_2T2R;
1104
1105 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1_8822B);
1106
1107 version = value32;
1108
1109 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1110 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1111
1112 return version;
1113}
1114
1115static int _rtl8822be_set_media_status(struct ieee80211_hw *hw,
1116 enum nl80211_iftype type)
1117{
1118 struct rtl_priv *rtlpriv = rtl_priv(hw);
1119 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1120 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1121 u8 mode = MSR_NOLINK;
1122
1123 bt_msr &= 0xfc;
1124
1125 switch (type) {
1126 case NL80211_IFTYPE_UNSPECIFIED:
1127 mode = MSR_NOLINK;
1128 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1129 "Set Network type to NO LINK!\n");
1130 break;
1131 case NL80211_IFTYPE_ADHOC:
1132 case NL80211_IFTYPE_MESH_POINT:
1133 mode = MSR_ADHOC;
1134 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1135 "Set Network type to Ad Hoc!\n");
1136 break;
1137 case NL80211_IFTYPE_STATION:
1138 mode = MSR_INFRA;
1139 ledaction = LED_CTL_LINK;
1140 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1141 "Set Network type to STA!\n");
1142 break;
1143 case NL80211_IFTYPE_AP:
1144 mode = MSR_AP;
1145 ledaction = LED_CTL_LINK;
1146 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1147 "Set Network type to AP!\n");
1148 break;
1149 default:
1150 pr_err("Network type %d not support!\n", type);
1151 return 1;
1152 }
1153
1154
1155
1156
1157
1158
1159
1160 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1161 mode = MSR_NOLINK;
1162 ledaction = LED_CTL_NO_LINK;
1163 }
1164
1165 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1166 _rtl8822be_stop_tx_beacon(hw);
1167 _rtl8822be_enable_bcn_sub_func(hw);
1168 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1169 _rtl8822be_resume_tx_beacon(hw);
1170 _rtl8822be_disable_bcn_sub_func(hw);
1171 } else {
1172 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1173 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1174 mode);
1175 }
1176
1177 rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1178 rtlpriv->cfg->ops->led_control(hw, ledaction);
1179 if (mode == MSR_AP)
1180 rtl_write_byte(rtlpriv, REG_BCNTCFG_8822B + 1, 0x00);
1181 else
1182 rtl_write_byte(rtlpriv, REG_BCNTCFG_8822B + 1, 0x66);
1183 return 0;
1184}
1185
1186void rtl8822be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1187{
1188 struct rtl_priv *rtlpriv = rtl_priv(hw);
1189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1190 u32 reg_rcr = rtlpci->receive_config;
1191
1192 if (rtlpriv->psc.rfpwr_state != ERFON)
1193 return;
1194
1195 if (check_bssid) {
1196 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1197 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1198 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1199 } else if (!check_bssid) {
1200 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1201 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1202 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1203 }
1204}
1205
1206int rtl8822be_set_network_type(struct ieee80211_hw *hw,
1207 enum nl80211_iftype type)
1208{
1209 struct rtl_priv *rtlpriv = rtl_priv(hw);
1210
1211 if (_rtl8822be_set_media_status(hw, type))
1212 return -EOPNOTSUPP;
1213
1214 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1215 if (type != NL80211_IFTYPE_AP &&
1216 type != NL80211_IFTYPE_MESH_POINT)
1217 rtl8822be_set_check_bssid(hw, true);
1218 } else {
1219 rtl8822be_set_check_bssid(hw, false);
1220 }
1221
1222 return 0;
1223}
1224
1225void rtl8822be_set_qos(struct ieee80211_hw *hw, int aci)
1226{
1227 struct rtl_priv *rtlpriv = rtl_priv(hw);
1228 struct rtl_mac *mac = rtl_mac(rtlpriv);
1229 u32 ac_param;
1230
1231 ac_param = rtl_get_hal_edca_param(hw, mac->vif, mac->mode,
1232 &mac->edca_param[aci]);
1233
1234 switch (aci) {
1235 case AC1_BK:
1236 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM_8822B, ac_param);
1237 break;
1238 case AC0_BE:
1239 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM_8822B, ac_param);
1240 break;
1241 case AC2_VI:
1242 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM_8822B, ac_param);
1243 break;
1244 case AC3_VO:
1245 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM_8822B, ac_param);
1246 break;
1247 default:
1248 WARN_ONCE(true, "invalid aci: %d !\n", aci);
1249 break;
1250 }
1251}
1252
1253void rtl8822be_enable_interrupt(struct ieee80211_hw *hw)
1254{
1255 struct rtl_priv *rtlpriv = rtl_priv(hw);
1256 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1257
1258 rtl_write_dword(rtlpriv, REG_HIMR0_8822B,
1259 rtlpci->irq_mask[0] & 0xFFFFFFFF);
1260 rtl_write_dword(rtlpriv, REG_HIMR1_8822B,
1261 rtlpci->irq_mask[1] & 0xFFFFFFFF);
1262 rtl_write_dword(rtlpriv, REG_HIMR3_8822B,
1263 rtlpci->irq_mask[3] & 0xFFFFFFFF);
1264 rtlpci->irq_enabled = true;
1265}
1266
1267void rtl8822be_disable_interrupt(struct ieee80211_hw *hw)
1268{
1269 struct rtl_priv *rtlpriv = rtl_priv(hw);
1270 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1271
1272 rtl_write_dword(rtlpriv, REG_HIMR0_8822B, IMR_DISABLED);
1273 rtl_write_dword(rtlpriv, REG_HIMR1_8822B, IMR_DISABLED);
1274 rtl_write_dword(rtlpriv, REG_HIMR3_8822B, IMR_DISABLED);
1275 rtlpci->irq_enabled = false;
1276
1277}
1278
1279void rtl8822be_card_disable(struct ieee80211_hw *hw)
1280{
1281 struct rtl_priv *rtlpriv = rtl_priv(hw);
1282 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1283 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1284 enum nl80211_iftype opmode;
1285
1286 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8822be card disable\n");
1287
1288 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1289
1290 mac->link_state = MAC80211_NOLINK;
1291 opmode = NL80211_IFTYPE_UNSPECIFIED;
1292
1293 _rtl8822be_set_media_status(hw, opmode);
1294
1295 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1296 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1297 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1298
1299 rtlpriv->phydm.ops->phydm_deinit_dm(rtlpriv);
1300
1301 rtlpriv->halmac.ops->halmac_deinit_hal(rtlpriv);
1302
1303
1304 if (!rtlpriv->cfg->ops->get_btc_status())
1305 rtlpriv->phy.iqk_initialized = false;
1306}
1307
1308void rtl8822be_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1309 u32 *p_intb, u32 *p_intc, u32 *p_intd)
1310{
1311 struct rtl_priv *rtlpriv = rtl_priv(hw);
1312 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1313
1314 *p_inta =
1315 rtl_read_dword(rtlpriv, REG_HISR0_8822B) & rtlpci->irq_mask[0];
1316 rtl_write_dword(rtlpriv, REG_HISR0_8822B, *p_inta);
1317
1318 *p_intb =
1319 rtl_read_dword(rtlpriv, REG_HISR1_8822B) & rtlpci->irq_mask[1];
1320 rtl_write_dword(rtlpriv, REG_HISR1_8822B, *p_intb);
1321
1322 *p_intd =
1323 rtl_read_dword(rtlpriv, REG_HISR3_8822B) & rtlpci->irq_mask[3];
1324 rtl_write_dword(rtlpriv, REG_HISR3_8822B, *p_intd);
1325}
1326
1327void rtl8822be_set_beacon_related_registers(struct ieee80211_hw *hw)
1328{
1329 struct rtl_priv *rtlpriv = rtl_priv(hw);
1330 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1331 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1332 u16 bcn_interval, atim_window;
1333
1334 bcn_interval = mac->beacon_interval;
1335 atim_window = 2;
1336 rtl8822be_disable_interrupt(hw);
1337 rtl_write_word(rtlpriv, REG_ATIMWND_8822B, atim_window);
1338 rtl_write_word(rtlpriv, REG_MBSSID_BCN_SPACE_8822B, bcn_interval);
1339 rtl_write_word(rtlpriv, REG_BCNTCFG_8822B, 0x660f);
1340 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK_8822B, 0x18);
1341 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM_8822B, 0x18);
1342 rtl_write_byte(rtlpriv, 0x606, 0x30);
1343 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1344 rtl_write_byte(rtlpriv, REG_BCN_CTRL_8822B,
1345 (u8)rtlpci->reg_bcn_ctrl_val);
1346}
1347
1348void rtl8822be_set_beacon_interval(struct ieee80211_hw *hw)
1349{
1350 struct rtl_priv *rtlpriv = rtl_priv(hw);
1351 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1352 u16 bcn_interval = mac->beacon_interval;
1353
1354 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1355 bcn_interval);
1356 rtl_write_word(rtlpriv, REG_MBSSID_BCN_SPACE_8822B, bcn_interval);
1357}
1358
1359void rtl8822be_update_interrupt_mask(struct ieee80211_hw *hw, u32 add_msr,
1360 u32 rm_msr)
1361{
1362 struct rtl_priv *rtlpriv = rtl_priv(hw);
1363 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1364
1365 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1366 add_msr, rm_msr);
1367
1368 if (add_msr)
1369 rtlpci->irq_mask[0] |= add_msr;
1370 if (rm_msr)
1371 rtlpci->irq_mask[0] &= (~rm_msr);
1372 rtl8822be_disable_interrupt(hw);
1373 rtl8822be_enable_interrupt(hw);
1374}
1375
1376static bool _rtl8822be_get_chnl_group(u8 chnl, u8 *group)
1377{
1378 bool in_24g;
1379
1380 if (chnl <= 14) {
1381 in_24g = true;
1382
1383 if (chnl >= 1 && chnl <= 2)
1384 *group = 0;
1385 else if (chnl >= 3 && chnl <= 5)
1386 *group = 1;
1387 else if (chnl >= 6 && chnl <= 8)
1388 *group = 2;
1389 else if (chnl >= 9 && chnl <= 11)
1390 *group = 3;
1391 else if (chnl >= 12 && chnl <= 14)
1392 *group = 4;
1393 } else {
1394 in_24g = false;
1395
1396 if (chnl >= 36 && chnl <= 42)
1397 *group = 0;
1398 else if (chnl >= 44 && chnl <= 48)
1399 *group = 1;
1400 else if (chnl >= 50 && chnl <= 58)
1401 *group = 2;
1402 else if (chnl >= 60 && chnl <= 64)
1403 *group = 3;
1404 else if (chnl >= 100 && chnl <= 106)
1405 *group = 4;
1406 else if (chnl >= 108 && chnl <= 114)
1407 *group = 5;
1408 else if (chnl >= 116 && chnl <= 122)
1409 *group = 6;
1410 else if (chnl >= 124 && chnl <= 130)
1411 *group = 7;
1412 else if (chnl >= 132 && chnl <= 138)
1413 *group = 8;
1414 else if (chnl >= 140 && chnl <= 144)
1415 *group = 9;
1416 else if (chnl >= 149 && chnl <= 155)
1417 *group = 10;
1418 else if (chnl >= 157 && chnl <= 161)
1419 *group = 11;
1420 else if (chnl >= 165 && chnl <= 171)
1421 *group = 12;
1422 else if (chnl >= 173 && chnl <= 177)
1423 *group = 13;
1424 }
1425 return in_24g;
1426}
1427
1428static inline bool power_valid(u8 power)
1429{
1430 if (power <= 63)
1431 return true;
1432
1433 return false;
1434}
1435
1436static inline s8 power_diff(s8 diff)
1437{
1438
1439 if (diff & BIT(3))
1440 diff |= 0xF0;
1441
1442 return diff;
1443}
1444
1445static void _rtl8822be_read_power_value_fromprom(struct ieee80211_hw *hw,
1446 struct txpower_info_2g *pwr2g,
1447 struct txpower_info_5g *pwr5g,
1448 bool autoload_fail, u8 *hwinfo)
1449{
1450 struct rtl_priv *rtlpriv = rtl_priv(hw);
1451 u32 rf, addr = EEPROM_TX_PWR_INX_8822B, group, i = 0;
1452 u8 power;
1453 s8 diff;
1454
1455 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1456 "hal_ReadPowerValueFromPROM8822B(): PROMContent[0x%x]=0x%x\n",
1457 (addr + 1), hwinfo[addr + 1]);
1458 if (hwinfo[addr + 1] == 0xFF)
1459 autoload_fail = true;
1460
1461 memset(pwr2g, 0, sizeof(struct txpower_info_2g));
1462 memset(pwr5g, 0, sizeof(struct txpower_info_5g));
1463
1464 if (autoload_fail) {
1465 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1466 "auto load fail : Use Default value!\n");
1467 for (rf = 0; rf < MAX_RF_PATH; rf++) {
1468
1469 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1470 pwr2g->index_cck_base[rf][group] = 0x2D;
1471 pwr2g->index_bw40_base[rf][group] = 0x2D;
1472 }
1473 for (i = 0; i < MAX_TX_COUNT; i++) {
1474 if (i == 0) {
1475 pwr2g->bw20_diff[rf][0] = 0x02;
1476 pwr2g->ofdm_diff[rf][0] = 0x04;
1477 } else {
1478 pwr2g->bw20_diff[rf][i] = 0xFE;
1479 pwr2g->bw40_diff[rf][i] = 0xFE;
1480 pwr2g->cck_diff[rf][i] = 0xFE;
1481 pwr2g->ofdm_diff[rf][i] = 0xFE;
1482 }
1483 }
1484
1485
1486 for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
1487 pwr5g->index_bw40_base[rf][group] = 0x2A;
1488
1489 for (i = 0; i < MAX_TX_COUNT; i++) {
1490 if (i == 0) {
1491 pwr5g->ofdm_diff[rf][0] = 0x04;
1492 pwr5g->bw20_diff[rf][0] = 0x00;
1493 pwr5g->bw80_diff[rf][0] = 0xFE;
1494 pwr5g->bw160_diff[rf][0] = 0xFE;
1495 } else {
1496 pwr5g->ofdm_diff[rf][i] = 0xFE;
1497 pwr5g->bw20_diff[rf][i] = 0xFE;
1498 pwr5g->bw40_diff[rf][i] = 0xFE;
1499 pwr5g->bw80_diff[rf][i] = 0xFE;
1500 pwr5g->bw160_diff[rf][i] = 0xFE;
1501 }
1502 }
1503 }
1504 return;
1505 }
1506
1507 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
1508
1509 for (rf = 0; rf < 2 ; rf++) {
1510
1511 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1512 power = hwinfo[addr++];
1513 if (power_valid(power))
1514 pwr2g->index_cck_base[rf][group] = power;
1515 }
1516 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1517 power = hwinfo[addr++];
1518 if (power_valid(power))
1519 pwr2g->index_bw40_base[rf][group] = power;
1520 }
1521 for (i = 0; i < MAX_TX_COUNT; i++) {
1522 if (i == 0) {
1523 pwr2g->bw40_diff[rf][i] = 0;
1524
1525 diff = (hwinfo[addr] & 0xF0) >> 4;
1526 pwr2g->bw20_diff[rf][i] = power_diff(diff);
1527
1528 diff = hwinfo[addr] & 0x0F;
1529 pwr2g->ofdm_diff[rf][i] = power_diff(diff);
1530
1531 pwr2g->cck_diff[rf][i] = 0;
1532
1533 addr++;
1534 } else {
1535 diff = (hwinfo[addr] & 0xF0) >> 4;
1536 pwr2g->bw40_diff[rf][i] = power_diff(diff);
1537
1538 diff = hwinfo[addr] & 0x0F;
1539 pwr2g->bw20_diff[rf][i] = power_diff(diff);
1540
1541 addr++;
1542
1543 diff = (hwinfo[addr] & 0xF0) >> 4;
1544 pwr2g->ofdm_diff[rf][i] = power_diff(diff);
1545
1546 diff = hwinfo[addr] & 0x0F;
1547 pwr2g->cck_diff[rf][i] = power_diff(diff);
1548
1549 addr++;
1550 }
1551 }
1552
1553
1554 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1555 power = hwinfo[addr++];
1556 if (power_valid(power))
1557 pwr5g->index_bw40_base[rf][group] = power;
1558 }
1559
1560 for (i = 0; i < MAX_TX_COUNT; i++) {
1561 if (i == 0) {
1562 pwr5g->bw40_diff[rf][i] = 0;
1563
1564 diff = (hwinfo[addr] & 0xF0) >> 4;
1565 pwr5g->bw20_diff[rf][i] = power_diff(diff);
1566
1567 diff = hwinfo[addr] & 0x0F;
1568 pwr5g->ofdm_diff[rf][i] = power_diff(diff);
1569
1570 addr++;
1571 } else {
1572 diff = (hwinfo[addr] & 0xF0) >> 4;
1573 pwr5g->bw40_diff[rf][i] = power_diff(diff);
1574
1575 diff = hwinfo[addr] & 0x0F;
1576 pwr5g->bw20_diff[rf][i] = power_diff(diff);
1577
1578 addr++;
1579 }
1580 }
1581
1582 diff = (hwinfo[addr] & 0xF0) >> 4;
1583 pwr5g->ofdm_diff[rf][1] = power_diff(diff);
1584
1585 diff = hwinfo[addr] & 0x0F;
1586 pwr5g->ofdm_diff[rf][2] = power_diff(diff);
1587
1588 addr++;
1589
1590 diff = hwinfo[addr] & 0x0F;
1591 pwr5g->ofdm_diff[rf][3] = power_diff(diff);
1592
1593 addr++;
1594
1595 for (i = 0; i < MAX_TX_COUNT; i++) {
1596 diff = (hwinfo[addr] & 0xF0) >> 4;
1597 pwr5g->bw80_diff[rf][i] = power_diff(diff);
1598
1599 diff = hwinfo[addr] & 0x0F;
1600 pwr5g->bw160_diff[rf][i] = power_diff(diff);
1601
1602 addr++;
1603 }
1604 }
1605}
1606
1607static void _rtl8822be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1608 bool autoload_fail,
1609 u8 *hwinfo)
1610{
1611 struct rtl_priv *rtlpriv = rtl_priv(hw);
1612 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
1613 struct txpower_info_2g pwr2g;
1614 struct txpower_info_5g pwr5g;
1615 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
1616 36, 38, 40, 42, 44, 46, 48,
1617 52, 54, 56, 58, 60, 62, 64,
1618 100, 102, 104, 106, 108, 110, 112,
1619 116, 118, 120, 122, 124, 126, 128,
1620 132, 134, 136, 138, 140, 142, 144,
1621 149, 151, 153, 155, 157, 159, 161,
1622 165, 167, 169, 171, 173, 175, 177};
1623 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122,
1624 138, 155, 171};
1625 u8 rf, group;
1626 u8 i;
1627
1628 _rtl8822be_read_power_value_fromprom(hw, &pwr2g, &pwr5g, autoload_fail,
1629 hwinfo);
1630
1631 for (rf = 0; rf < MAX_RF_PATH; rf++) {
1632 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
1633 _rtl8822be_get_chnl_group(i + 1, &group);
1634
1635 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
1636 efu->txpwrlevel_cck[rf][i] =
1637 pwr2g.index_cck_base[rf][5];
1638 efu->txpwrlevel_ht40_1s[rf][i] =
1639 pwr2g.index_bw40_base[rf][group];
1640 } else {
1641 efu->txpwrlevel_cck[rf][i] =
1642 pwr2g.index_cck_base[rf][group];
1643 efu->txpwrlevel_ht40_1s[rf][i] =
1644 pwr2g.index_bw40_base[rf][group];
1645 }
1646 }
1647 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
1648 _rtl8822be_get_chnl_group(channel5g[i], &group);
1649 efu->txpwr_5g_bw40base[rf][i] =
1650 pwr5g.index_bw40_base[rf][group];
1651 }
1652 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
1653 u8 upper, lower;
1654
1655 _rtl8822be_get_chnl_group(channel5g_80m[i], &group);
1656 upper = pwr5g.index_bw40_base[rf][group];
1657 lower = pwr5g.index_bw40_base[rf][group + 1];
1658
1659 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
1660 }
1661 for (i = 0; i < MAX_TX_COUNT; i++) {
1662 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
1663 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
1664 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
1665 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
1666
1667 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
1668 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
1669 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
1670 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
1671 }
1672 }
1673
1674 if (!autoload_fail)
1675 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_8822B];
1676 else
1677 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1678
1679 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
1680 efu->apk_thermalmeterignore = true;
1681 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1682 }
1683
1684 efu->thermalmeter[0] = efu->eeprom_thermalmeter;
1685 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "thermalmeter = 0x%x\n",
1686 efu->eeprom_thermalmeter);
1687
1688 if (!autoload_fail) {
1689 efu->eeprom_regulatory =
1690 hwinfo[EEPROM_RF_BOARD_OPTION_8822B] & 0x07;
1691 if (hwinfo[EEPROM_RF_BOARD_OPTION_8822B] == 0xFF)
1692 efu->eeprom_regulatory = 0;
1693 } else {
1694 efu->eeprom_regulatory = 0;
1695 }
1696 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "eeprom_regulatory = 0x%x\n",
1697 efu->eeprom_regulatory);
1698}
1699
1700static void _rtl8822be_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
1701 bool autoload_fail)
1702{
1703 struct rtl_priv *rtlpriv = rtl_priv(hw);
1704 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1705
1706 if (!autoload_fail) {
1707 rtlhal->pa_type_2g = hwinfo[EEPROM_2G_5G_PA_TYPE_8822B];
1708 rtlhal->lna_type_2g =
1709 hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B];
1710 if (rtlhal->pa_type_2g == 0xFF)
1711 rtlhal->pa_type_2g = 0;
1712 if (rtlhal->lna_type_2g == 0xFF)
1713 rtlhal->lna_type_2g = 0;
1714
1715 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(4)) ? 1 : 0;
1716 rtlhal->external_lna_2g =
1717 (rtlhal->lna_type_2g & BIT(3)) ? 1 : 0;
1718
1719 rtlhal->pa_type_5g = hwinfo[EEPROM_2G_5G_PA_TYPE_8822B];
1720 rtlhal->lna_type_5g =
1721 hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B];
1722 if (rtlhal->pa_type_5g == 0xFF)
1723 rtlhal->pa_type_5g = 0;
1724 if (rtlhal->lna_type_5g == 0xFF)
1725 rtlhal->lna_type_5g = 0;
1726
1727 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(0)) ? 1 : 0;
1728 rtlhal->external_lna_5g =
1729 (rtlhal->lna_type_5g & BIT(3)) ? 1 : 0;
1730 } else {
1731 rtlhal->external_pa_2g = 0;
1732 rtlhal->external_lna_2g = 0;
1733 rtlhal->external_pa_5g = 0;
1734 rtlhal->external_lna_5g = 0;
1735 }
1736}
1737
1738static void _rtl8822be_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
1739 bool autoload_fail)
1740{
1741 struct rtl_priv *rtlpriv = rtl_priv(hw);
1742 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1743
1744 u8 ext_type_pa_2g_a =
1745 (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(2)) >>
1746 2;
1747 u8 ext_type_pa_2g_b =
1748 (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(6)) >>
1749 6;
1750 u8 ext_type_pa_5g_a =
1751 (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(2)) >>
1752 2;
1753 u8 ext_type_pa_5g_b =
1754 (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(6)) >>
1755 6;
1756 u8 ext_type_lna_2g_a = (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1757 (BIT(1) | BIT(0))) >>
1758 0;
1759 u8 ext_type_lna_2g_b = (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1760 (BIT(5) | BIT(4))) >>
1761 4;
1762 u8 ext_type_lna_5g_a = (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1763 (BIT(1) | BIT(0))) >>
1764 0;
1765 u8 ext_type_lna_5g_b = (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1766 (BIT(5) | BIT(4))) >>
1767 4;
1768
1769 _rtl8822be_read_pa_type(hw, hwinfo, autoload_fail);
1770
1771
1772 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
1773 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a;
1774
1775
1776 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
1777 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a;
1778
1779
1780 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
1781 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
1782
1783
1784 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
1785 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
1786}
1787
1788static void _rtl8822be_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
1789 bool autoload_fail)
1790{
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1793
1794 if (!autoload_fail)
1795 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION_8822B];
1796 else
1797 rtlhal->rfe_type = 0;
1798
1799 if (rtlhal->rfe_type == 0xFF)
1800 rtlhal->rfe_type = 0;
1801
1802 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RFE Type: 0x%2x\n",
1803 rtlhal->rfe_type);
1804}
1805
1806static void _rtl8822be_read_adapter_info(struct ieee80211_hw *hw)
1807{
1808 struct rtl_priv *rtlpriv = rtl_priv(hw);
1809 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1810 struct rtl_halmac_ops *halmac_ops = rtlpriv->halmac.ops;
1811 u16 i, usvalue;
1812 u8 *hwinfo;
1813 u16 eeprom_id;
1814 u32 efuse_size;
1815 int err;
1816
1817 if (rtlefuse->epromtype != EEPROM_BOOT_EFUSE) {
1818 pr_err("RTL8822B Not boot from efuse!!");
1819 return;
1820 }
1821
1822
1823 err = halmac_ops->halmac_get_logical_efuse_size(rtlpriv, &efuse_size);
1824
1825 if (err || !efuse_size) {
1826 pr_err("halmac_get_logical_efuse_size err=%d efuse_size=0x%X",
1827 err, efuse_size);
1828 efuse_size = HWSET_MAX_SIZE;
1829 }
1830
1831 if (efuse_size > HWSET_MAX_SIZE) {
1832 pr_err("halmac_get_logical_efuse_size efuse_size=0x%X > 0x%X",
1833 efuse_size, HWSET_MAX_SIZE);
1834 efuse_size = HWSET_MAX_SIZE;
1835 }
1836
1837
1838 hwinfo = kzalloc(efuse_size, GFP_KERNEL);
1839
1840 err = halmac_ops->halmac_read_logical_efuse_map(rtlpriv, hwinfo,
1841 efuse_size);
1842 if (err) {
1843 pr_err("%s: <ERROR> fail to get efuse map!\n", __func__);
1844 goto label_end;
1845 }
1846
1847
1848 memcpy(&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], hwinfo,
1849 EFUSE_MAX_LOGICAL_SIZE);
1850 memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0], hwinfo,
1851 EFUSE_MAX_LOGICAL_SIZE);
1852
1853
1854 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n", hwinfo,
1855 HWSET_MAX_SIZE);
1856
1857 eeprom_id = *((u16 *)&hwinfo[0]);
1858 if (eeprom_id != RTL8822B_EEPROM_ID) {
1859 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1860 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1861 rtlefuse->autoload_failflag = true;
1862 } else {
1863 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1864 rtlefuse->autoload_failflag = false;
1865 }
1866
1867 if (rtlefuse->autoload_failflag)
1868 goto label_end;
1869
1870
1871 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1872 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1873 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1874 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1875 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
1876 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM VID = 0x%4x\n",
1877 rtlefuse->eeprom_vid);
1878 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM DID = 0x%4x\n",
1879 rtlefuse->eeprom_did);
1880 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM SVID = 0x%4x\n",
1881 rtlefuse->eeprom_svid);
1882 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM SMID = 0x%4x\n",
1883 rtlefuse->eeprom_smid);
1884
1885 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOM_ID_8822B];
1886 if (rtlefuse->eeprom_oemid == 0xFF)
1887 rtlefuse->eeprom_oemid = 0;
1888
1889 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
1890 rtlefuse->eeprom_oemid);
1891
1892 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION_8822B];
1893
1894 for (i = 0; i < 6; i += 2) {
1895 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_8822BE + i];
1896 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1897 }
1898
1899 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "dev_addr: %pM\n",
1900 rtlefuse->dev_addr);
1901
1902
1903 rtlefuse->eeprom_channelplan =
1904 *(u8 *)&hwinfo[EEPROM_CHANNEL_PLAN_8822B];
1905
1906
1907 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1908 if (rtlefuse->channel_plan == 0xFF)
1909 rtlefuse->channel_plan = 0x7f;
1910
1911
1912 _rtl8822be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1913 hwinfo);
1914
1915 rtl8822be_read_bt_coexist_info_from_hwpg(
1916 hw, rtlefuse->autoload_failflag, hwinfo);
1917
1918
1919 _rtl8822be_read_amplifier_type(hw, hwinfo, rtlefuse->autoload_failflag);
1920
1921
1922 _rtl8822be_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
1923
1924
1925 rtlefuse->board_type =
1926 (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_8822B]) & 0xE0) >> 5);
1927 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_8822B]) == 0xFF)
1928 rtlefuse->board_type = 0;
1929
1930 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
1931 rtlefuse->board_type |= BIT(2);
1932
1933
1934 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "board_type = 0x%x\n",
1935 rtlefuse->board_type);
1936
1937 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8822B];
1938 if (hwinfo[EEPROM_XTAL_8822B] == 0xFF)
1939 rtlefuse->crystalcap = 0;
1940
1941
1942 rtlefuse->antenna_div_type = 0;
1943 rtlefuse->antenna_div_cfg = 0;
1944
1945label_end:
1946 kfree(hwinfo);
1947}
1948
1949static void _rtl8822be_hal_customized_behavior(struct ieee80211_hw *hw)
1950{
1951 struct rtl_priv *rtlpriv = rtl_priv(hw);
1952 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1953 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1954
1955 pcipriv->ledctl.led_opendrain = true;
1956
1957 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
1958 rtlhal->oem_id);
1959}
1960
1961static void _rtl8822be_read_pa_bias(struct ieee80211_hw *hw,
1962 struct rtl_phydm_params *params)
1963{
1964 struct rtl_priv *rtlpriv = rtl_priv(hw);
1965 struct rtl_halmac_ops *halmac_ops = rtlpriv->halmac.ops;
1966 u32 size;
1967 u8 *map = NULL;
1968
1969
1970 params->efuse0x3d7 = 0xFF;
1971 params->efuse0x3d8 = 0xFF;
1972
1973 if (halmac_ops->halmac_get_physical_efuse_size(rtlpriv, &size))
1974 goto err;
1975
1976 map = kmalloc(size, GFP_KERNEL);
1977 if (!map)
1978 goto err;
1979
1980 if (halmac_ops->halmac_read_physical_efuse_map(rtlpriv, map, size))
1981 goto err;
1982
1983 params->efuse0x3d7 = map[0x3d7];
1984 params->efuse0x3d8 = map[0x3d8];
1985
1986 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1987 "efuse0x3d7 = 0x%2x, efuse0x3d8 = 0x%2x\n",
1988 params->efuse0x3d7, params->efuse0x3d8);
1989
1990err:
1991 kfree(map);
1992}
1993
1994void rtl8822be_read_eeprom_info(struct ieee80211_hw *hw,
1995 struct rtl_phydm_params *params)
1996{
1997 struct rtl_priv *rtlpriv = rtl_priv(hw);
1998 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1999 struct rtl_phy *rtlphy = &rtlpriv->phy;
2000 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2001 u8 tmp_u1b;
2002
2003 rtlhal->version = _rtl8822be_read_chip_version(hw);
2004
2005 params->mp_chip = (rtlhal->version & BIT_RTL_ID_8822B) ? 0 : 1;
2006 params->fab_ver = BIT_GET_VENDOR_ID_8822B(rtlhal->version) >> 2;
2007 params->cut_ver = BIT_GET_CHIP_VER_8822B(rtlhal->version);
2008
2009
2010 if (params->fab_ver == 2)
2011 params->fab_ver = 1;
2012 else if (params->fab_ver == 1)
2013 params->fab_ver = 2;
2014
2015
2016 _rtl8822be_read_pa_bias(hw, params);
2017
2018 if (get_rf_type(rtlphy) == RF_1T1R)
2019 rtlpriv->dm.rfpath_rxenable[0] = true;
2020 else
2021 rtlpriv->dm.rfpath_rxenable[0] =
2022 rtlpriv->dm.rfpath_rxenable[1] = true;
2023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2024 rtlhal->version);
2025 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_EEPROM_CTRL_8822B);
2026 if (tmp_u1b & BIT(4)) {
2027 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2028 rtlefuse->epromtype = EEPROM_93C46;
2029 } else {
2030 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2031 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2032 }
2033 if (tmp_u1b & BIT(5)) {
2034 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2035 rtlefuse->autoload_failflag = false;
2036 _rtl8822be_read_adapter_info(hw);
2037 } else {
2038 pr_err("Autoload ERR!!\n");
2039 }
2040 _rtl8822be_hal_customized_behavior(hw);
2041
2042 rtlphy->rfpath_rx_enable[0] = true;
2043 if (rtlphy->rf_type == RF_2T2R)
2044 rtlphy->rfpath_rx_enable[1] = true;
2045}
2046
2047void rtl8822be_read_eeprom_info_dummy(struct ieee80211_hw *hw)
2048{
2049
2050
2051
2052
2053
2054}
2055
2056static u32 _rtl8822be_rate_to_bitmap_2ssvht(__le16 vht_rate)
2057{
2058 u8 i, j, tmp_rate;
2059 u32 rate_bitmap = 0;
2060
2061 for (i = j = 0; i < 4; i += 2, j += 10) {
2062 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
2063
2064 switch (tmp_rate) {
2065 case 2:
2066 rate_bitmap = rate_bitmap | (0x03ff << j);
2067 break;
2068
2069 case 1:
2070 rate_bitmap = rate_bitmap | (0x01ff << j);
2071 break;
2072
2073 case 0:
2074 rate_bitmap = rate_bitmap | (0x00ff << j);
2075 break;
2076
2077 default:
2078 break;
2079 }
2080 }
2081
2082 return rate_bitmap;
2083}
2084
2085static u8 _rtl8822be_get_vht_en(enum wireless_mode wirelessmode,
2086 u32 ratr_bitmap)
2087{
2088 u8 ret = 0;
2089
2090 if (wirelessmode < WIRELESS_MODE_N_24G) {
2091 ret = 0;
2092 } else if (wirelessmode == WIRELESS_MODE_AC_24G) {
2093 if (ratr_bitmap & 0xfff00000)
2094 ret = 3;
2095 else
2096 ret = 2;
2097 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
2098 ret = 1;
2099 }
2100
2101 return ret << 4;
2102}
2103
2104static u8 _rtl8822be_get_ra_ldpc(struct ieee80211_hw *hw, u8 mac_id,
2105 struct rtl_sta_info *sta_entry,
2106 enum wireless_mode wirelessmode)
2107{
2108 u8 b_ldpc = 0;
2109
2110 return b_ldpc << 2;
2111}
2112
2113static u8 _rtl8822be_get_ra_rftype(struct ieee80211_hw *hw,
2114 enum wireless_mode wirelessmode,
2115 u32 ratr_bitmap)
2116{
2117 struct rtl_priv *rtlpriv = rtl_priv(hw);
2118 struct rtl_phy *rtlphy = &rtlpriv->phy;
2119 u8 rf_type = RF_1T1R;
2120
2121 if (rtlphy->rf_type == RF_1T1R) {
2122 rf_type = RF_1T1R;
2123 } else if (wirelessmode == WIRELESS_MODE_AC_5G ||
2124 wirelessmode == WIRELESS_MODE_AC_24G ||
2125 wirelessmode == WIRELESS_MODE_AC_ONLY) {
2126 if (ratr_bitmap & 0xffc00000)
2127 rf_type = RF_2T2R;
2128 } else if (wirelessmode == WIRELESS_MODE_N_5G ||
2129 wirelessmode == WIRELESS_MODE_N_24G) {
2130 if (ratr_bitmap & 0xfff00000)
2131 rf_type = RF_2T2R;
2132 }
2133
2134 return rf_type;
2135}
2136
2137static bool _rtl8822be_get_ra_shortgi(struct ieee80211_hw *hw,
2138 struct ieee80211_sta *sta, u8 mac_id)
2139{
2140 bool b_short_gi = false;
2141 u8 b_curshortgi_40mhz =
2142 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
2143 u8 b_curshortgi_20mhz =
2144 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1 : 0;
2145 u8 b_curshortgi_80mhz = 0;
2146
2147 b_curshortgi_80mhz =
2148 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
2149
2150 if (mac_id == 99 )
2151 b_short_gi = false;
2152
2153 if (b_curshortgi_40mhz || b_curshortgi_80mhz || b_curshortgi_20mhz)
2154 b_short_gi = true;
2155
2156 return b_short_gi;
2157}
2158
2159static void rtl8822be_update_hal_rate_mask(struct ieee80211_hw *hw,
2160 struct ieee80211_sta *sta,
2161 u8 rssi_level, bool update_bw)
2162{
2163 struct rtl_priv *rtlpriv = rtl_priv(hw);
2164 struct rtl_phy *rtlphy = &rtlpriv->phy;
2165 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2166 struct rtl_sta_info *sta_entry = NULL;
2167 u32 ratr_bitmap, ratr_bitmap_msb = 0;
2168 u8 ratr_index;
2169 enum wireless_mode wirelessmode = 0;
2170 u8 curtxbw_40mhz =
2171 (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2172 bool b_shortgi = false;
2173 u8 rate_mask[7];
2174 u8 macid = 0;
2175 u8 rf_type;
2176
2177 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2178 wirelessmode = sta_entry->wireless_mode;
2179
2180 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, "wireless mode = 0x%x\n",
2181 wirelessmode);
2182 if (mac->opmode == NL80211_IFTYPE_STATION ||
2183 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2184 curtxbw_40mhz = mac->bw_40;
2185 } else if (mac->opmode == NL80211_IFTYPE_AP ||
2186 mac->opmode == NL80211_IFTYPE_ADHOC)
2187 macid = sta->aid + 1;
2188 if (wirelessmode == WIRELESS_MODE_N_5G ||
2189 wirelessmode == WIRELESS_MODE_AC_5G ||
2190 wirelessmode == WIRELESS_MODE_A)
2191 ratr_bitmap = (sta->supp_rates[NL80211_BAND_5GHZ]) << 4;
2192 else
2193 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
2194
2195 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2196 ratr_bitmap = 0xfff;
2197
2198 if (wirelessmode == WIRELESS_MODE_N_24G ||
2199 wirelessmode == WIRELESS_MODE_N_5G)
2200 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2201 sta->ht_cap.mcs.rx_mask[0] << 12);
2202 else if (wirelessmode == WIRELESS_MODE_AC_24G ||
2203 wirelessmode == WIRELESS_MODE_AC_5G ||
2204 wirelessmode == WIRELESS_MODE_AC_ONLY)
2205 ratr_bitmap |= _rtl8822be_rate_to_bitmap_2ssvht(
2206 sta->vht_cap.vht_mcs.rx_mcs_map)
2207 << 12;
2208
2209 b_shortgi = _rtl8822be_get_ra_shortgi(hw, sta, macid);
2210 rf_type = _rtl8822be_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
2211
2212 ratr_index = rtlpriv->phydm.ops->phydm_rate_id_mapping(
2213 rtlpriv, wirelessmode, rf_type, rtlphy->current_chan_bw);
2214 sta_entry->ratr_index = ratr_index;
2215
2216 rtlpriv->phydm.ops->phydm_get_ra_bitmap(
2217 rtlpriv, wirelessmode, rf_type, rtlphy->current_chan_bw,
2218 rssi_level, &ratr_bitmap_msb, &ratr_bitmap);
2219
2220 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, "ratr_bitmap :%x\n",
2221 ratr_bitmap);
2222
2223 rate_mask[0] = macid;
2224 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2225 rate_mask[2] =
2226 rtlphy->current_chan_bw | ((!update_bw) << 3) |
2227 _rtl8822be_get_vht_en(wirelessmode, ratr_bitmap) |
2228 _rtl8822be_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
2229
2230 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2231 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2232 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2233 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2234
2235 RT_TRACE(
2236 rtlpriv, COMP_RATR, DBG_DMESG,
2237 "Rate_index:%x, ratr_val:%08x, %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
2238 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2239 rate_mask[2], rate_mask[3], rate_mask[4], rate_mask[5],
2240 rate_mask[6]);
2241 rtl8822be_fill_h2c_cmd(hw, H2C_8822B_MACID_CFG, 7, rate_mask);
2242
2243
2244
2245
2246 memset(rate_mask + 3, 0, 4);
2247
2248 rtl8822be_fill_h2c_cmd(hw, H2C_8822B_MACID_CFG_3SS, 7, rate_mask);
2249
2250 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2251}
2252
2253void rtl8822be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2254 struct ieee80211_sta *sta, u8 rssi_level,
2255 bool update_bw)
2256{
2257 struct rtl_priv *rtlpriv = rtl_priv(hw);
2258
2259 if (rtlpriv->dm.useramask)
2260 rtl8822be_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2261}
2262
2263void rtl8822be_update_channel_access_setting(struct ieee80211_hw *hw)
2264{
2265 struct rtl_priv *rtlpriv = rtl_priv(hw);
2266 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2267 u16 sifs_timer;
2268
2269 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2270 (u8 *)&mac->slot_time);
2271 if (!mac->ht_enable)
2272 sifs_timer = 0x0a0a;
2273 else
2274 sifs_timer = 0x0e0e;
2275 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2276}
2277
2278bool rtl8822be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2279{
2280 *valid = 1;
2281 return true;
2282}
2283
2284void rtl8822be_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2285 bool is_group, u8 enc_algo, bool is_wepkey,
2286 bool clear_all)
2287{
2288 struct rtl_priv *rtlpriv = rtl_priv(hw);
2289 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2290 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2291 u8 *macaddr = p_macaddr;
2292 u32 entry_id = 0;
2293 bool is_pairwise = false;
2294
2295 static u8 cam_const_addr[4][6] = {
2296 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2297 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2298 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2299 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03},
2300 };
2301 static u8 cam_const_broad[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2302
2303 if (clear_all) {
2304 u8 idx = 0;
2305 u8 cam_offset = 0;
2306 u8 clear_number = 5;
2307
2308 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2309
2310 for (idx = 0; idx < clear_number; idx++) {
2311 rtl_cam_mark_invalid(hw, cam_offset + idx);
2312 rtl_cam_empty_entry(hw, cam_offset + idx);
2313
2314 if (idx < 5) {
2315 memset(rtlpriv->sec.key_buf[idx], 0,
2316 MAX_KEY_LEN);
2317 rtlpriv->sec.key_len[idx] = 0;
2318 }
2319 }
2320
2321 return;
2322 }
2323
2324 switch (enc_algo) {
2325 case WEP40_ENCRYPTION:
2326 enc_algo = CAM_WEP40;
2327 break;
2328 case WEP104_ENCRYPTION:
2329 enc_algo = CAM_WEP104;
2330 break;
2331 case TKIP_ENCRYPTION:
2332 enc_algo = CAM_TKIP;
2333 break;
2334 case AESCCMP_ENCRYPTION:
2335 enc_algo = CAM_AES;
2336 break;
2337 default:
2338 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2339 "switch case %#x not processed\n", enc_algo);
2340 enc_algo = CAM_TKIP;
2341 break;
2342 }
2343
2344 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2345 macaddr = cam_const_addr[key_index];
2346 entry_id = key_index;
2347 } else {
2348 if (is_group) {
2349 macaddr = cam_const_broad;
2350 entry_id = key_index;
2351 } else {
2352 if (mac->opmode == NL80211_IFTYPE_AP) {
2353 entry_id =
2354 rtl_cam_get_free_entry(hw, p_macaddr);
2355 if (entry_id >= TOTAL_CAM_ENTRY) {
2356 pr_err("Can not find free hwsecurity cam entry\n");
2357 return;
2358 }
2359 } else {
2360 entry_id = CAM_PAIRWISE_KEY_POSITION;
2361 }
2362
2363 key_index = PAIRWISE_KEYIDX;
2364 is_pairwise = true;
2365 }
2366 }
2367
2368 if (rtlpriv->sec.key_len[key_index] == 0) {
2369 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2370 "delete one entry, entry_id is %d\n", entry_id);
2371 if (mac->opmode == NL80211_IFTYPE_AP)
2372 rtl_cam_del_entry(hw, p_macaddr);
2373 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2374 } else {
2375 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "add one entry\n");
2376 if (is_pairwise) {
2377 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2378 "set Pairwise key\n");
2379
2380 rtl_cam_add_one_entry(hw, macaddr, key_index, entry_id,
2381 enc_algo, CAM_CONFIG_NO_USEDK,
2382 rtlpriv->sec.key_buf[key_index]);
2383 } else {
2384 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2385 "set group key\n");
2386
2387 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2388 rtl_cam_add_one_entry(
2389 hw, rtlefuse->dev_addr, PAIRWISE_KEYIDX,
2390 CAM_PAIRWISE_KEY_POSITION, enc_algo,
2391 CAM_CONFIG_NO_USEDK,
2392 rtlpriv->sec.key_buf[entry_id]);
2393 }
2394
2395 rtl_cam_add_one_entry(hw, macaddr, key_index, entry_id,
2396 enc_algo, CAM_CONFIG_NO_USEDK,
2397 rtlpriv->sec.key_buf[entry_id]);
2398 }
2399 }
2400}
2401
2402void rtl8822be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2403 bool auto_load_fail, u8 *hwinfo)
2404{
2405 struct rtl_priv *rtlpriv = rtl_priv(hw);
2406 u8 value;
2407 u32 val32;
2408
2409 val32 = rtl_read_dword(rtlpriv, REG_WL_BT_PWR_CTRL_8822B);
2410 if (val32 & BIT_BT_FUNC_EN_8822B)
2411 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2412 else
2413 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2414
2415 if (!auto_load_fail) {
2416 value = hwinfo[EEPROM_RF_BT_SETTING_8822B];
2417
2418 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8822B;
2419 rtlpriv->btcoexist.btc_info.ant_num =
2420 (value & BIT(0) ? ANT_TOTAL_X1 : ANT_TOTAL_X2);
2421 } else {
2422 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8822B;
2423 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2424 }
2425}
2426
2427void rtl8822be_bt_reg_init(struct ieee80211_hw *hw)
2428{
2429 struct rtl_priv *rtlpriv = rtl_priv(hw);
2430
2431
2432 rtlpriv->btcoexist.reg_bt_iso = 2;
2433
2434 rtlpriv->btcoexist.reg_bt_sco = 3;
2435
2436 rtlpriv->btcoexist.reg_bt_sco = 0;
2437}
2438
2439void rtl8822be_suspend(struct ieee80211_hw *hw) {}
2440
2441void rtl8822be_resume(struct ieee80211_hw *hw) {}
2442
