linux/drivers/staging/rtlwifi/rtl8822be/sw.c
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   1/******************************************************************************
   2 *
   3 * Copyright(c) 2016  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * The full GNU General Public License is included in this distribution in the
  15 * file called LICENSE.
  16 *
  17 * Contact Information:
  18 * wlanfae <wlanfae@realtek.com>
  19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20 * Hsinchu 300, Taiwan.
  21 *
  22 * Larry Finger <Larry.Finger@lwfinger.net>
  23 *
  24 *****************************************************************************/
  25
  26#include "../wifi.h"
  27#include "../core.h"
  28#include "../pci.h"
  29#include "../base.h"
  30#include "reg.h"
  31#include "def.h"
  32#include "phy.h"
  33#include "hw.h"
  34#include "sw.h"
  35#include "fw.h"
  36#include "trx.h"
  37#include "led.h"
  38#include "../btcoexist/rtl_btc.h"
  39#include "../halmac/rtl_halmac.h"
  40#include "../phydm/rtl_phydm.h"
  41#include <linux/vmalloc.h>
  42#include <linux/module.h>
  43
  44static void rtl8822be_init_aspm_vars(struct ieee80211_hw *hw)
  45{
  46        struct rtl_priv *rtlpriv = rtl_priv(hw);
  47        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  48
  49        /*close ASPM for AMD defaultly */
  50        rtlpci->const_amdpci_aspm = 0;
  51
  52        /*
  53         * ASPM PS mode.
  54         * 0 - Disable ASPM,
  55         * 1 - Enable ASPM without Clock Req,
  56         * 2 - Enable ASPM with Clock Req,
  57         * 3 - Alwyas Enable ASPM with Clock Req,
  58         * 4 - Always Enable ASPM without Clock Req.
  59         * set default to RTL8822BE:3 RTL8822B:2
  60         *
  61         */
  62        rtlpci->const_pci_aspm = 3;
  63
  64        /*Setting for PCI-E device */
  65        rtlpci->const_devicepci_aspm_setting = 0x03;
  66
  67        /*Setting for PCI-E bridge */
  68        rtlpci->const_hostpci_aspm_setting = 0x02;
  69
  70        /*
  71         * In Hw/Sw Radio Off situation.
  72         * 0 - Default,
  73         * 1 - From ASPM setting without low Mac Pwr,
  74         * 2 - From ASPM setting with low Mac Pwr,
  75         * 3 - Bus D3
  76         * set default to RTL8822BE:0 RTL8192SE:2
  77         */
  78        rtlpci->const_hwsw_rfoff_d3 = 0;
  79
  80        /*
  81         * This setting works for those device with
  82         * backdoor ASPM setting such as EPHY setting.
  83         * 0 - Not support ASPM,
  84         * 1 - Support ASPM,
  85         * 2 - According to chipset.
  86         */
  87        rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
  88}
  89
  90int rtl8822be_init_sw_vars(struct ieee80211_hw *hw)
  91{
  92        int err = 0;
  93        struct rtl_priv *rtlpriv = rtl_priv(hw);
  94        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  95        const char *fw_name;
  96        struct rtl_phydm_params params;
  97
  98        rtl8822be_bt_reg_init(hw);
  99        rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
 100        rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
 101        rtlpriv->halmac.ops = rtl_halmac_get_ops_pointer();
 102        rtlpriv->halmac.ops->halmac_init_adapter(rtlpriv);
 103
 104        /* should after halmac_init_adapter() */
 105        rtl8822be_read_eeprom_info(hw, &params);
 106
 107        /* need eeprom info */
 108        rtlpriv->phydm.ops = rtl_phydm_get_ops_pointer();
 109        rtlpriv->phydm.ops->phydm_init_priv(rtlpriv, &params);
 110
 111        rtlpriv->dm.dm_initialgain_enable = 1;
 112        rtlpriv->dm.dm_flag = 0;
 113        rtlpriv->dm.disable_framebursting = 0;
 114        /*rtlpriv->dm.thermalvalue = 0;*/
 115        rtlpriv->dm.useramask = 1; /* turn on RA */
 116        rtlpci->transmit_config = CFENDFORM | BIT(15);
 117
 118        rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 119        /*following 2 is for register 5G band, refer to _rtl_init_mac80211()*/
 120        rtlpriv->rtlhal.bandset = BAND_ON_BOTH;
 121        rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 122
 123        rtlpci->receive_config = (RCR_APPFCS                    |
 124                                  RCR_APP_MIC                   |
 125                                  RCR_APP_ICV                   |
 126                                  RCR_APP_PHYST_RXFF            |
 127                                  RCR_VHT_DACK                  |
 128                                  RCR_HTC_LOC_CTRL              |
 129                                  /*RCR_AMF                     |*/
 130                                  RCR_CBSSID_BCN                |
 131                                  RCR_CBSSID_DATA               |
 132                                  /*RCR_ACF                     |*/
 133                                  /*RCR_ADF                     |*/
 134                                  /*RCR_AICV                    |*/
 135                                  /*RCR_ACRC32                  |*/
 136                                  RCR_AB                        |
 137                                  RCR_AM                        |
 138                                  RCR_APM                       |
 139                                  0);
 140
 141        rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT               |
 142                                    /*IMR_TBDER                 |*/
 143                                    /*IMR_TBDOK                 |*/
 144                                    /*IMR_BCNDMAINT0            |*/
 145                                    IMR_GTINT3                  |
 146                                    IMR_HSISR_IND_ON_INT        |
 147                                    IMR_C2HCMD                  |
 148                                    IMR_HIGHDOK                 |
 149                                    IMR_MGNTDOK                 |
 150                                    IMR_BKDOK                   |
 151                                    IMR_BEDOK                   |
 152                                    IMR_VIDOK                   |
 153                                    IMR_VODOK                   |
 154                                    IMR_RDU                     |
 155                                    IMR_ROK                     |
 156                                    0);
 157
 158        rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | IMR_TXFOVW | 0);
 159        rtlpci->irq_mask[3] = (u32)(BIT_SETH2CDOK_MASK | 0);
 160
 161        /* for LPS & IPS */
 162        rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 163        rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 164        rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 165        rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
 166        if (rtlpriv->cfg->mod_params->disable_watchdog)
 167                pr_info("watchdog disabled\n");
 168        rtlpriv->psc.reg_fwctrl_lps = 2;
 169        rtlpriv->psc.reg_max_lps_awakeintvl = 2;
 170        /* for ASPM, you can close aspm through
 171         * set const_support_pciaspm = 0
 172         */
 173        rtl8822be_init_aspm_vars(hw);
 174
 175        if (rtlpriv->psc.reg_fwctrl_lps == 1)
 176                rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 177        else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 178                rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 179        else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 180                rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 181
 182        /* for early mode */
 183        rtlpriv->rtlhal.earlymode_enable = false;
 184
 185        /*low power */
 186        rtlpriv->psc.low_power_enable = false;
 187
 188        /* for firmware buf */
 189        rtlpriv->rtlhal.pfirmware = vzalloc(0x40000);
 190        if (!rtlpriv->rtlhal.pfirmware) {
 191                /*pr_err("Can't alloc buffer for fw\n");*/
 192                return 1;
 193        }
 194
 195        /* request fw */
 196        fw_name = "rtlwifi/rtl8822befw.bin";
 197
 198        rtlpriv->max_fw_size = 0x40000;
 199        pr_info("Using firmware %s\n", fw_name);
 200        err = request_firmware_nowait(THIS_MODULE, 1, fw_name, rtlpriv->io.dev,
 201                                      GFP_KERNEL, hw, rtl_fw_cb);
 202        if (err) {
 203                pr_err("Failed to request firmware!\n");
 204                return 1;
 205        }
 206
 207        /* init table of tx power by rate & limit */
 208        rtl8822be_load_txpower_by_rate(hw);
 209        rtl8822be_load_txpower_limit(hw);
 210
 211        return 0;
 212}
 213
 214void rtl8822be_deinit_sw_vars(struct ieee80211_hw *hw)
 215{
 216        struct rtl_priv *rtlpriv = rtl_priv(hw);
 217
 218        rtlpriv->halmac.ops->halmac_deinit_adapter(rtlpriv);
 219        rtlpriv->phydm.ops->phydm_deinit_priv(rtlpriv);
 220
 221        if (rtlpriv->rtlhal.pfirmware) {
 222                vfree(rtlpriv->rtlhal.pfirmware);
 223                rtlpriv->rtlhal.pfirmware = NULL;
 224        }
 225}
 226
 227/* get bt coexist status */
 228bool rtl8822be_get_btc_status(void)
 229{
 230        return true;
 231}
 232
 233static void rtl8822be_phydm_watchdog(struct ieee80211_hw *hw)
 234{
 235        struct rtl_priv *rtlpriv = rtl_priv(hw);
 236        u32 tmp;
 237
 238        tmp = rtl_read_dword(rtlpriv, 0xc00);
 239        if (tmp & 0xFF000000) { /* Recover 0xC00: 0xF800000C --> 0x0000000C */
 240                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 241                         "found regaddr_c00=%08X\n", tmp);
 242                tmp &= ~0xFF000000;
 243                rtl_write_dword(rtlpriv, 0xc00, tmp);
 244                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 245                         "apply regaddr_c00=%08X\n", tmp);
 246        }
 247
 248        rtlpriv->phydm.ops->phydm_watchdog(rtlpriv);
 249}
 250
 251static struct rtl_hal_ops rtl8822be_hal_ops = {
 252        .init_sw_vars = rtl8822be_init_sw_vars,
 253        .deinit_sw_vars = rtl8822be_deinit_sw_vars,
 254        .read_eeprom_info = rtl8822be_read_eeprom_info_dummy,
 255        .interrupt_recognized = rtl8822be_interrupt_recognized,
 256        .hw_init = rtl8822be_hw_init,
 257        .hw_disable = rtl8822be_card_disable,
 258        .hw_suspend = rtl8822be_suspend,
 259        .hw_resume = rtl8822be_resume,
 260        .enable_interrupt = rtl8822be_enable_interrupt,
 261        .disable_interrupt = rtl8822be_disable_interrupt,
 262        .set_network_type = rtl8822be_set_network_type,
 263        .set_chk_bssid = rtl8822be_set_check_bssid,
 264        .set_qos = rtl8822be_set_qos,
 265        .set_bcn_reg = rtl8822be_set_beacon_related_registers,
 266        .set_bcn_intv = rtl8822be_set_beacon_interval,
 267        .update_interrupt_mask = rtl8822be_update_interrupt_mask,
 268        .get_hw_reg = rtl8822be_get_hw_reg,
 269        .set_hw_reg = rtl8822be_set_hw_reg,
 270        .update_rate_tbl = rtl8822be_update_hal_rate_tbl,
 271        .pre_fill_tx_bd_desc = rtl8822be_pre_fill_tx_bd_desc,
 272        .rx_desc_buff_remained_cnt = rtl8822be_rx_desc_buff_remained_cnt,
 273        .rx_check_dma_ok = rtl8822be_rx_check_dma_ok,
 274        .fill_tx_desc = rtl8822be_tx_fill_desc,
 275        .fill_tx_special_desc = rtl8822be_tx_fill_special_desc,
 276        .query_rx_desc = rtl8822be_rx_query_desc,
 277        .radio_onoff_checking = rtl8822be_gpio_radio_on_off_checking,
 278        .switch_channel = rtl8822be_phy_sw_chnl,
 279        .set_channel_access = rtl8822be_update_channel_access_setting,
 280        .set_bw_mode = rtl8822be_phy_set_bw_mode,
 281        .dm_watchdog = rtl8822be_phydm_watchdog,
 282        .scan_operation_backup = rtl8822be_phy_scan_operation_backup,
 283        .set_rf_power_state = rtl8822be_phy_set_rf_power_state,
 284        .led_control = rtl8822be_led_control,
 285        .set_desc = rtl8822be_set_desc,
 286        .get_desc = rtl8822be_get_desc,
 287        .is_tx_desc_closed = rtl8822be_is_tx_desc_closed,
 288        .get_available_desc = rtl8822be_get_available_desc,
 289        .tx_polling = rtl8822be_tx_polling,
 290        .enable_hw_sec = rtl8822be_enable_hw_security_config,
 291        .set_key = rtl8822be_set_key,
 292        .init_sw_leds = rtl8822be_init_sw_leds,
 293        .get_bbreg = rtl8822be_phy_query_bb_reg,
 294        .set_bbreg = rtl8822be_phy_set_bb_reg,
 295        .get_rfreg = rtl8822be_phy_query_rf_reg,
 296        .set_rfreg = rtl8822be_phy_set_rf_reg,
 297        .fill_h2c_cmd = rtl8822be_fill_h2c_cmd,
 298        .set_default_port_id_cmd = rtl8822be_set_default_port_id_cmd,
 299        .get_btc_status = rtl8822be_get_btc_status,
 300        .rx_command_packet = rtl8822be_rx_command_packet,
 301        .c2h_content_parsing = rtl8822be_c2h_content_parsing,
 302        /* ops for halmac cb */
 303        .halmac_cb_init_mac_register = rtl8822be_halmac_cb_init_mac_register,
 304        .halmac_cb_init_bb_rf_register =
 305                rtl8822be_halmac_cb_init_bb_rf_register,
 306        .halmac_cb_write_data_rsvd_page =
 307                rtl8822b_halmac_cb_write_data_rsvd_page,
 308        .halmac_cb_write_data_h2c = rtl8822b_halmac_cb_write_data_h2c,
 309        /* ops for phydm cb */
 310        .get_txpower_index = rtl8822be_get_txpower_index,
 311        .set_tx_power_index_by_rs = rtl8822be_phy_set_tx_power_index_by_rs,
 312        .store_tx_power_by_rate = rtl8822be_store_tx_power_by_rate,
 313        .phy_set_txpower_limit = rtl8822be_phy_set_txpower_limit,
 314};
 315
 316static struct rtl_mod_params rtl8822be_mod_params = {
 317        .sw_crypto = false,
 318        .inactiveps = true,
 319        .swctrl_lps = false,
 320        .fwctrl_lps = true,
 321        .msi_support = true,
 322        .dma64 = false,
 323        .aspm_support = 1,
 324        .disable_watchdog = false,
 325        .debug_level = 0,
 326        .debug_mask = 0,
 327};
 328
 329static struct rtl_hal_cfg rtl8822be_hal_cfg = {
 330        .bar_id = 2,
 331        .write_readback = false,
 332        .name = "rtl8822be_pci",
 333        .ops = &rtl8822be_hal_ops,
 334        .mod_params = &rtl8822be_mod_params,
 335        .spec_ver = RTL_SPEC_NEW_RATEID | RTL_SPEC_SUPPORT_VHT |
 336                    RTL_SPEC_NEW_FW_C2H,
 337        .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL_8822B,
 338        .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN_8822B,
 339        .maps[SYS_CLK] = REG_SYS_CLK_CTRL_8822B,
 340        .maps[MAC_RCR_AM] = AM,
 341        .maps[MAC_RCR_AB] = AB,
 342        .maps[MAC_RCR_ACRC32] = ACRC32,
 343        .maps[MAC_RCR_ACF] = ACF,
 344        .maps[MAC_RCR_AAP] = AAP,
 345        .maps[MAC_HIMR] = REG_HIMR0_8822B,
 346        .maps[MAC_HIMRE] = REG_HIMR1_8822B,
 347
 348        .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS_8822B,
 349
 350        .maps[EFUSE_TEST] = REG_LDO_EFUSE_CTRL_8822B,
 351        .maps[EFUSE_CTRL] = REG_EFUSE_CTRL_8822B,
 352        .maps[EFUSE_CLK] = 0,
 353        .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL_8822B,
 354        .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 355        .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 356        .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 357        .maps[EFUSE_ANA8M] = ANA8M,
 358        .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 359        .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 360        .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 361        .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 362
 363        .maps[RWCAM] = REG_CAMCMD_8822B,
 364        .maps[WCAMI] = REG_CAMWRITE_8822B,
 365        .maps[RCAMO] = REG_CAMREAD_8822B,
 366        .maps[CAMDBG] = REG_CAMDBG_8822B,
 367        .maps[SECR] = REG_SECCFG_8822B,
 368        .maps[SEC_CAM_NONE] = CAM_NONE,
 369        .maps[SEC_CAM_WEP40] = CAM_WEP40,
 370        .maps[SEC_CAM_TKIP] = CAM_TKIP,
 371        .maps[SEC_CAM_AES] = CAM_AES,
 372        .maps[SEC_CAM_WEP104] = CAM_WEP104,
 373
 374        .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 375        .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 376        .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 377        .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 378        .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 379        .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 380        /*      .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */ /*need check*/
 381        .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 382        .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 383        .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 384        .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 385        .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 386        .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 387        .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 388        /*      .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
 389        /*      .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
 390
 391        .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 392        .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 393        .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
 394        .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 395        .maps[RTL_IMR_RDU] = IMR_RDU,
 396        .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 397        .maps[RTL_IMR_H2CDOK] = IMR_H2CDOK,
 398        .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
 399        .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 400        .maps[RTL_IMR_TBDER] = IMR_TBDER,
 401        .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 402        .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 403        .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 404        .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 405        .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 406        .maps[RTL_IMR_VODOK] = IMR_VODOK,
 407        .maps[RTL_IMR_ROK] = IMR_ROK,
 408        .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
 409
 410        .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
 411        .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
 412        .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
 413        .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
 414        .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
 415        .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
 416        .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
 417        .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
 418        .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
 419        .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
 420        .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
 421        .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
 422
 423        .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
 424        .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
 425
 426        /*VHT hightest rate*/
 427        .maps[RTL_RC_VHT_RATE_1SS_MCS7] = DESC_RATEVHT1SS_MCS7,
 428        .maps[RTL_RC_VHT_RATE_1SS_MCS8] = DESC_RATEVHT1SS_MCS8,
 429        .maps[RTL_RC_VHT_RATE_1SS_MCS9] = DESC_RATEVHT1SS_MCS9,
 430        .maps[RTL_RC_VHT_RATE_2SS_MCS7] = DESC_RATEVHT2SS_MCS7,
 431        .maps[RTL_RC_VHT_RATE_2SS_MCS8] = DESC_RATEVHT2SS_MCS8,
 432        .maps[RTL_RC_VHT_RATE_2SS_MCS9] = DESC_RATEVHT2SS_MCS9,
 433};
 434
 435static const struct pci_device_id rtl8822be_pci_ids[] = {
 436        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xB822, rtl8822be_hal_cfg)},
 437        {},
 438};
 439
 440MODULE_DEVICE_TABLE(pci, rtl8822be_pci_ids);
 441
 442MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 443MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 444MODULE_LICENSE("GPL");
 445MODULE_DESCRIPTION("Realtek 8822BE 802.11n PCI wireless");
 446MODULE_FIRMWARE("rtlwifi/rtl8822befw.bin");
 447
 448module_param_named(swenc, rtl8822be_mod_params.sw_crypto, bool, 0444);
 449module_param_named(debug_level, rtl8822be_mod_params.debug_level, int, 0644);
 450module_param_named(debug_mask, rtl8822be_mod_params.debug_mask, ullong, 0644);
 451module_param_named(ips, rtl8822be_mod_params.inactiveps, bool, 0444);
 452module_param_named(swlps, rtl8822be_mod_params.swctrl_lps, bool, 0444);
 453module_param_named(fwlps, rtl8822be_mod_params.fwctrl_lps, bool, 0444);
 454module_param_named(msi, rtl8822be_mod_params.msi_support, bool, 0444);
 455module_param_named(dma64, rtl8822be_mod_params.dma64, bool, 0444);
 456module_param_named(aspm, rtl8822be_mod_params.aspm_support, int, 0444);
 457module_param_named(disable_watchdog, rtl8822be_mod_params.disable_watchdog,
 458                   bool, 0444);
 459MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 460MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 461MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 462MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 463MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
 464MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
 465MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
 466MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 467MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
 468MODULE_PARM_DESC(disable_watchdog,
 469                 "Set to 1 to disable the watchdog (default 0)\n");
 470
 471static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 472
 473static struct pci_driver rtl8822be_driver = {
 474        .name = KBUILD_MODNAME,
 475        .id_table = rtl8822be_pci_ids,
 476        .probe = rtl_pci_probe,
 477        .remove = rtl_pci_disconnect,
 478        .driver.pm = &rtlwifi_pm_ops,
 479};
 480
 481module_pci_driver(rtl8822be_driver);
 482