1
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7
8
9#undef DEBUG
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/slab.h>
15#include <linux/delay.h>
16#include <linux/tty.h>
17#include <linux/serial_reg.h>
18#include <linux/serial_core.h>
19#include <linux/8250_pci.h>
20#include <linux/bitops.h>
21
22#include <asm/byteorder.h>
23#include <asm/io.h>
24
25#include "8250.h"
26
27
28
29
30
31
32
33struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44};
45
46#define PCI_NUM_BAR_RESOURCES 6
47
48struct serial_private {
49 struct pci_dev *dev;
50 unsigned int nr;
51 struct pci_serial_quirk *quirk;
52 const struct pciserial_board *board;
53 int line[0];
54};
55
56static int pci_default_setup(struct serial_private*,
57 const struct pciserial_board*, struct uart_8250_port *, int);
58
59static void moan_device(const char *str, struct pci_dev *dev)
60{
61 dev_err(&dev->dev,
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to <linux-serial@vger.kernel.org>.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69}
70
71static int
72setup_port(struct serial_private *priv, struct uart_8250_port *port,
73 int bar, int offset, int regshift)
74{
75 struct pci_dev *dev = priv->dev;
76
77 if (bar >= PCI_NUM_BAR_RESOURCES)
78 return -EINVAL;
79
80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
82 return -ENOMEM;
83
84 port->port.iotype = UPIO_MEM;
85 port->port.iobase = 0;
86 port->port.mapbase = pci_resource_start(dev, bar) + offset;
87 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
88 port->port.regshift = regshift;
89 } else {
90 port->port.iotype = UPIO_PORT;
91 port->port.iobase = pci_resource_start(dev, bar) + offset;
92 port->port.mapbase = 0;
93 port->port.membase = NULL;
94 port->port.regshift = 0;
95 }
96 return 0;
97}
98
99
100
101
102static int addidata_apci7800_setup(struct serial_private *priv,
103 const struct pciserial_board *board,
104 struct uart_8250_port *port, int idx)
105{
106 unsigned int bar = 0, offset = board->first_offset;
107 bar = FL_GET_BASE(board->flags);
108
109 if (idx < 2) {
110 offset += idx * board->uart_offset;
111 } else if ((idx >= 2) && (idx < 4)) {
112 bar += 1;
113 offset += ((idx - 2) * board->uart_offset);
114 } else if ((idx >= 4) && (idx < 6)) {
115 bar += 2;
116 offset += ((idx - 4) * board->uart_offset);
117 } else if (idx >= 6) {
118 bar += 3;
119 offset += ((idx - 6) * board->uart_offset);
120 }
121
122 return setup_port(priv, port, bar, offset, board->reg_shift);
123}
124
125
126
127
128
129static int
130afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
131 struct uart_8250_port *port, int idx)
132{
133 unsigned int bar, offset = board->first_offset;
134
135 bar = FL_GET_BASE(board->flags);
136 if (idx < 4)
137 bar += idx;
138 else {
139 bar = 4;
140 offset += (idx - 4) * board->uart_offset;
141 }
142
143 return setup_port(priv, port, bar, offset, board->reg_shift);
144}
145
146
147
148
149
150
151
152
153static int pci_hp_diva_init(struct pci_dev *dev)
154{
155 int rc = 0;
156
157 switch (dev->subsystem_device) {
158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
161 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
162 rc = 3;
163 break;
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
165 rc = 2;
166 break;
167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
168 rc = 4;
169 break;
170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
172 rc = 1;
173 break;
174 }
175
176 return rc;
177}
178
179
180
181
182
183static int
184pci_hp_diva_setup(struct serial_private *priv,
185 const struct pciserial_board *board,
186 struct uart_8250_port *port, int idx)
187{
188 unsigned int offset = board->first_offset;
189 unsigned int bar = FL_GET_BASE(board->flags);
190
191 switch (priv->dev->subsystem_device) {
192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
193 if (idx == 3)
194 idx++;
195 break;
196 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
197 if (idx > 0)
198 idx++;
199 if (idx > 2)
200 idx++;
201 break;
202 }
203 if (idx > 2)
204 offset = 0x18;
205
206 offset += idx * board->uart_offset;
207
208 return setup_port(priv, port, bar, offset, board->reg_shift);
209}
210
211
212
213
214static int pci_inteli960ni_init(struct pci_dev *dev)
215{
216 u32 oldval;
217
218 if (!(dev->subsystem_device & 0x1000))
219 return -ENODEV;
220
221
222 pci_read_config_dword(dev, 0x44, &oldval);
223 if (oldval == 0x00001000L) {
224 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
225 return -ENODEV;
226 }
227 return 0;
228}
229
230
231
232
233
234
235
236static int pci_plx9050_init(struct pci_dev *dev)
237{
238 u8 irq_config;
239 void __iomem *p;
240
241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
242 moan_device("no memory in bar 0", dev);
243 return 0;
244 }
245
246 irq_config = 0x41;
247 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
249 irq_config = 0x43;
250
251 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
253
254
255
256
257
258
259
260
261 irq_config = 0x5b;
262
263
264
265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
266 if (p == NULL)
267 return -ENOMEM;
268 writel(irq_config, p + 0x4c);
269
270
271
272
273 readl(p + 0x4c);
274 iounmap(p);
275
276 return 0;
277}
278
279static void pci_plx9050_exit(struct pci_dev *dev)
280{
281 u8 __iomem *p;
282
283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
284 return;
285
286
287
288
289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
290 if (p != NULL) {
291 writel(0, p + 0x4c);
292
293
294
295
296 readl(p + 0x4c);
297 iounmap(p);
298 }
299}
300
301#define NI8420_INT_ENABLE_REG 0x38
302#define NI8420_INT_ENABLE_BIT 0x2000
303
304static void pci_ni8420_exit(struct pci_dev *dev)
305{
306 void __iomem *p;
307 unsigned int bar = 0;
308
309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
310 moan_device("no memory in bar", dev);
311 return;
312 }
313
314 p = pci_ioremap_bar(dev, bar);
315 if (p == NULL)
316 return;
317
318
319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
320 p + NI8420_INT_ENABLE_REG);
321 iounmap(p);
322}
323
324
325
326#define MITE_IOWBSR1 0xc4
327#define MITE_IOWCR1 0xf4
328#define MITE_LCIMR1 0x08
329#define MITE_LCIMR2 0x10
330
331#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
332
333static void pci_ni8430_exit(struct pci_dev *dev)
334{
335 void __iomem *p;
336 unsigned int bar = 0;
337
338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
339 moan_device("no memory in bar", dev);
340 return;
341 }
342
343 p = pci_ioremap_bar(dev, bar);
344 if (p == NULL)
345 return;
346
347
348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
349 iounmap(p);
350}
351
352
353static int
354sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
355 struct uart_8250_port *port, int idx)
356{
357 unsigned int bar, offset = board->first_offset;
358
359 bar = 0;
360
361 if (idx < 4) {
362
363 offset += idx * board->uart_offset;
364 } else if (idx < 8) {
365
366 offset += idx * board->uart_offset + 0xC00;
367 } else
368 return 1;
369
370 return setup_port(priv, port, bar, offset, board->reg_shift);
371}
372
373
374
375
376
377
378
379
380
381#define OCT_REG_CR_OFF 0x500
382
383static int sbs_init(struct pci_dev *dev)
384{
385 u8 __iomem *p;
386
387 p = pci_ioremap_bar(dev, 0);
388
389 if (p == NULL)
390 return -ENOMEM;
391
392 writeb(0x10, p + OCT_REG_CR_OFF);
393 udelay(50);
394 writeb(0x0, p + OCT_REG_CR_OFF);
395
396
397 writeb(0x4, p + OCT_REG_CR_OFF);
398 iounmap(p);
399
400 return 0;
401}
402
403
404
405
406
407static void sbs_exit(struct pci_dev *dev)
408{
409 u8 __iomem *p;
410
411 p = pci_ioremap_bar(dev, 0);
412
413 if (p != NULL)
414 writeb(0, p + OCT_REG_CR_OFF);
415 iounmap(p);
416}
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
446#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
447
448static int pci_siig10x_init(struct pci_dev *dev)
449{
450 u16 data;
451 void __iomem *p;
452
453 switch (dev->device & 0xfff8) {
454 case PCI_DEVICE_ID_SIIG_1S_10x:
455 data = 0xffdf;
456 break;
457 case PCI_DEVICE_ID_SIIG_2S_10x:
458 data = 0xf7ff;
459 break;
460 default:
461 data = 0xfffb;
462 break;
463 }
464
465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
466 if (p == NULL)
467 return -ENOMEM;
468
469 writew(readw(p + 0x28) & data, p + 0x28);
470 readw(p + 0x28);
471 iounmap(p);
472 return 0;
473}
474
475#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
476#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
477
478static int pci_siig20x_init(struct pci_dev *dev)
479{
480 u8 data;
481
482
483 pci_read_config_byte(dev, 0x6f, &data);
484 pci_write_config_byte(dev, 0x6f, data & 0xef);
485
486
487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
489 pci_read_config_byte(dev, 0x73, &data);
490 pci_write_config_byte(dev, 0x73, data & 0xef);
491 }
492 return 0;
493}
494
495static int pci_siig_init(struct pci_dev *dev)
496{
497 unsigned int type = dev->device & 0xff00;
498
499 if (type == 0x1000)
500 return pci_siig10x_init(dev);
501 else if (type == 0x2000)
502 return pci_siig20x_init(dev);
503
504 moan_device("Unknown SIIG card", dev);
505 return -ENODEV;
506}
507
508static int pci_siig_setup(struct serial_private *priv,
509 const struct pciserial_board *board,
510 struct uart_8250_port *port, int idx)
511{
512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
513
514 if (idx > 3) {
515 bar = 4;
516 offset = (idx - 4) * 8;
517 }
518
519 return setup_port(priv, port, bar, offset, 0);
520}
521
522
523
524
525
526
527static const unsigned short timedia_single_port[] = {
528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
529};
530
531static const unsigned short timedia_dual_port[] = {
532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
536 0xD079, 0
537};
538
539static const unsigned short timedia_quad_port[] = {
540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
543 0xB157, 0
544};
545
546static const unsigned short timedia_eight_port[] = {
547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
549};
550
551static const struct timedia_struct {
552 int num;
553 const unsigned short *ids;
554} timedia_data[] = {
555 { 1, timedia_single_port },
556 { 2, timedia_dual_port },
557 { 4, timedia_quad_port },
558 { 8, timedia_eight_port }
559};
560
561
562
563
564
565
566
567static int pci_timedia_probe(struct pci_dev *dev)
568{
569
570
571
572
573 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
574 dev_info(&dev->dev,
575 "ignoring Timedia subdevice %04x for parport_serial\n",
576 dev->subsystem_device);
577 return -ENODEV;
578 }
579
580 return 0;
581}
582
583static int pci_timedia_init(struct pci_dev *dev)
584{
585 const unsigned short *ids;
586 int i, j;
587
588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
589 ids = timedia_data[i].ids;
590 for (j = 0; ids[j]; j++)
591 if (dev->subsystem_device == ids[j])
592 return timedia_data[i].num;
593 }
594 return 0;
595}
596
597
598
599
600
601static int
602pci_timedia_setup(struct serial_private *priv,
603 const struct pciserial_board *board,
604 struct uart_8250_port *port, int idx)
605{
606 unsigned int bar = 0, offset = board->first_offset;
607
608 switch (idx) {
609 case 0:
610 bar = 0;
611 break;
612 case 1:
613 offset = board->uart_offset;
614 bar = 0;
615 break;
616 case 2:
617 bar = 1;
618 break;
619 case 3:
620 offset = board->uart_offset;
621
622 case 4:
623 case 5:
624 case 6:
625 case 7:
626 bar = idx - 2;
627 }
628
629 return setup_port(priv, port, bar, offset, board->reg_shift);
630}
631
632
633
634
635static int
636titan_400l_800l_setup(struct serial_private *priv,
637 const struct pciserial_board *board,
638 struct uart_8250_port *port, int idx)
639{
640 unsigned int bar, offset = board->first_offset;
641
642 switch (idx) {
643 case 0:
644 bar = 1;
645 break;
646 case 1:
647 bar = 2;
648 break;
649 default:
650 bar = 4;
651 offset = (idx - 2) * board->uart_offset;
652 }
653
654 return setup_port(priv, port, bar, offset, board->reg_shift);
655}
656
657static int pci_xircom_init(struct pci_dev *dev)
658{
659 msleep(100);
660 return 0;
661}
662
663static int pci_ni8420_init(struct pci_dev *dev)
664{
665 void __iomem *p;
666 unsigned int bar = 0;
667
668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
669 moan_device("no memory in bar", dev);
670 return 0;
671 }
672
673 p = pci_ioremap_bar(dev, bar);
674 if (p == NULL)
675 return -ENOMEM;
676
677
678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
679 p + NI8420_INT_ENABLE_REG);
680
681 iounmap(p);
682 return 0;
683}
684
685#define MITE_IOWBSR1_WSIZE 0xa
686#define MITE_IOWBSR1_WIN_OFFSET 0x800
687#define MITE_IOWBSR1_WENAB (1 << 7)
688#define MITE_LCIMR1_IO_IE_0 (1 << 24)
689#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
690#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
691
692static int pci_ni8430_init(struct pci_dev *dev)
693{
694 void __iomem *p;
695 struct pci_bus_region region;
696 u32 device_window;
697 unsigned int bar = 0;
698
699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
700 moan_device("no memory in bar", dev);
701 return 0;
702 }
703
704 p = pci_ioremap_bar(dev, bar);
705 if (p == NULL)
706 return -ENOMEM;
707
708
709
710
711
712
713 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
716 writel(device_window, p + MITE_IOWBSR1);
717
718
719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
720 p + MITE_IOWCR1);
721
722
723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
724
725
726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
727
728 iounmap(p);
729 return 0;
730}
731
732
733#define NI8430_PORTCON 0x0f
734#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
735
736static int
737pci_ni8430_setup(struct serial_private *priv,
738 const struct pciserial_board *board,
739 struct uart_8250_port *port, int idx)
740{
741 struct pci_dev *dev = priv->dev;
742 void __iomem *p;
743 unsigned int bar, offset = board->first_offset;
744
745 if (idx >= board->num_ports)
746 return 1;
747
748 bar = FL_GET_BASE(board->flags);
749 offset += idx * board->uart_offset;
750
751 p = pci_ioremap_bar(dev, bar);
752 if (!p)
753 return -ENOMEM;
754
755
756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
757 p + offset + NI8430_PORTCON);
758
759 iounmap(p);
760
761 return setup_port(priv, port, bar, offset, board->reg_shift);
762}
763
764static int pci_netmos_9900_setup(struct serial_private *priv,
765 const struct pciserial_board *board,
766 struct uart_8250_port *port, int idx)
767{
768 unsigned int bar;
769
770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
771 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
772
773
774
775 bar = 3 * idx;
776
777 return setup_port(priv, port, bar, 0, board->reg_shift);
778 } else {
779 return pci_default_setup(priv, board, port, idx);
780 }
781}
782
783
784
785
786
787
788
789
790
791static int pci_netmos_9900_numports(struct pci_dev *dev)
792{
793 unsigned int c = dev->class;
794 unsigned int pi;
795 unsigned short sub_serports;
796
797 pi = c & 0xff;
798
799 if (pi == 2)
800 return 1;
801
802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
803
804
805
806
807
808
809 sub_serports = dev->subsystem_device & 0xf;
810 if (sub_serports > 0)
811 return sub_serports;
812
813 dev_err(&dev->dev,
814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
815 return 0;
816 }
817
818 moan_device("unknown NetMos/Mostech program interface", dev);
819 return 0;
820}
821
822static int pci_netmos_init(struct pci_dev *dev)
823{
824
825 unsigned int num_serial = dev->subsystem_device & 0xf;
826
827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
828 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
829 return 0;
830
831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
832 dev->subsystem_device == 0x0299)
833 return 0;
834
835 switch (dev->device) {
836 case PCI_DEVICE_ID_NETMOS_9904:
837 case PCI_DEVICE_ID_NETMOS_9912:
838 case PCI_DEVICE_ID_NETMOS_9922:
839 case PCI_DEVICE_ID_NETMOS_9900:
840 num_serial = pci_netmos_9900_numports(dev);
841 break;
842
843 default:
844 break;
845 }
846
847 if (num_serial == 0) {
848 moan_device("unknown NetMos/Mostech device", dev);
849 return -ENODEV;
850 }
851
852 return num_serial;
853}
854
855
856
857
858
859
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862
863
864
865
866#define ITE_887x_MISCR 0x9c
867#define ITE_887x_INTCBAR 0x78
868#define ITE_887x_UARTBAR 0x7c
869#define ITE_887x_PS0BAR 0x10
870#define ITE_887x_POSIO0 0x60
871
872
873#define ITE_887x_IOSIZE 32
874
875#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
876
877#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
878
879#define ITE_887x_POSIO_SPEED (3 << 29)
880
881#define ITE_887x_POSIO_ENABLE (1 << 31)
882
883static int pci_ite887x_init(struct pci_dev *dev)
884{
885
886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
887 0x200, 0x280, 0 };
888 int ret, i, type;
889 struct resource *iobase = NULL;
890 u32 miscr, uartbar, ioport;
891
892
893 i = 0;
894 while (inta_addr[i] && iobase == NULL) {
895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
896 "ite887x");
897 if (iobase != NULL) {
898
899 pci_write_config_dword(dev, ITE_887x_POSIO0,
900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
902
903 pci_write_config_dword(dev, ITE_887x_INTCBAR,
904 inta_addr[i]);
905 ret = inb(inta_addr[i]);
906 if (ret != 0xff) {
907
908 break;
909 }
910 release_region(iobase->start, ITE_887x_IOSIZE);
911 iobase = NULL;
912 }
913 i++;
914 }
915
916 if (!inta_addr[i]) {
917 dev_err(&dev->dev, "ite887x: could not find iobase\n");
918 return -ENODEV;
919 }
920
921
922 type = inb(iobase->start + 0x18) & 0x0f;
923
924 switch (type) {
925 case 0x2:
926 case 0xa:
927 ret = 0;
928 break;
929 case 0xe:
930 ret = 2;
931 break;
932 case 0x6:
933 ret = 1;
934 break;
935 case 0x8:
936 ret = 2;
937 break;
938 default:
939 moan_device("Unknown ITE887x", dev);
940 ret = -ENODEV;
941 }
942
943
944 for (i = 0; i < ret; i++) {
945
946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
947 &ioport);
948 ioport &= 0x0000FF00;
949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
951 ITE_887x_POSIO_IOSIZE_8 | ioport);
952
953
954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
955 uartbar &= ~(0xffff << (16 * i));
956 uartbar |= (ioport << (16 * i));
957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
958
959
960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
961
962 miscr &= ~(0xf << (12 - 4 * i));
963
964 miscr |= 1 << (23 - i);
965
966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
967 }
968
969 if (ret <= 0) {
970
971 release_region(iobase->start, ITE_887x_IOSIZE);
972 }
973
974 return ret;
975}
976
977static void pci_ite887x_exit(struct pci_dev *dev)
978{
979 u32 ioport;
980
981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
982 ioport &= 0xffff;
983 release_region(ioport, ITE_887x_IOSIZE);
984}
985
986
987
988
989
990#define PCI_VENDOR_ID_ENDRUN 0x7401
991#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
992
993static int pci_endrun_init(struct pci_dev *dev)
994{
995 u8 __iomem *p;
996 unsigned long deviceID;
997 unsigned int number_uarts = 0;
998
999
1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1001 (dev->device & 0xf000) != 0xe000)
1002 return 0;
1003
1004 p = pci_iomap(dev, 0, 5);
1005 if (p == NULL)
1006 return -ENOMEM;
1007
1008 deviceID = ioread32(p);
1009
1010 if (deviceID == 0x07000200) {
1011 number_uarts = ioread8(p + 4);
1012 dev_dbg(&dev->dev,
1013 "%d ports detected on EndRun PCI Express device\n",
1014 number_uarts);
1015 }
1016 pci_iounmap(dev, p);
1017 return number_uarts;
1018}
1019
1020
1021
1022
1023
1024
1025static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1026{
1027 u8 __iomem *p;
1028 unsigned long deviceID;
1029 unsigned int number_uarts = 0;
1030
1031
1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1033 (dev->device & 0xF000) != 0xC000)
1034 return 0;
1035
1036 p = pci_iomap(dev, 0, 5);
1037 if (p == NULL)
1038 return -ENOMEM;
1039
1040 deviceID = ioread32(p);
1041
1042 if (deviceID == 0x07000200) {
1043 number_uarts = ioread8(p + 4);
1044 dev_dbg(&dev->dev,
1045 "%d ports detected on Oxford PCI Express device\n",
1046 number_uarts);
1047 }
1048 pci_iounmap(dev, p);
1049 return number_uarts;
1050}
1051
1052static int pci_asix_setup(struct serial_private *priv,
1053 const struct pciserial_board *board,
1054 struct uart_8250_port *port, int idx)
1055{
1056 port->bugs |= UART_BUG_PARITY;
1057 return pci_default_setup(priv, board, port, idx);
1058}
1059
1060
1061
1062struct quatech_feature {
1063 u16 devid;
1064 bool amcc;
1065};
1066
1067#define QPCR_TEST_FOR1 0x3F
1068#define QPCR_TEST_GET1 0x00
1069#define QPCR_TEST_FOR2 0x40
1070#define QPCR_TEST_GET2 0x40
1071#define QPCR_TEST_FOR3 0x80
1072#define QPCR_TEST_GET3 0x40
1073#define QPCR_TEST_FOR4 0xC0
1074#define QPCR_TEST_GET4 0x80
1075
1076#define QOPR_CLOCK_X1 0x0000
1077#define QOPR_CLOCK_X2 0x0001
1078#define QOPR_CLOCK_X4 0x0002
1079#define QOPR_CLOCK_X8 0x0003
1080#define QOPR_CLOCK_RATE_MASK 0x0003
1081
1082
1083static struct quatech_feature quatech_cards[] = {
1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1103 { 0, }
1104};
1105
1106static int pci_quatech_amcc(u16 devid)
1107{
1108 struct quatech_feature *qf = &quatech_cards[0];
1109 while (qf->devid) {
1110 if (qf->devid == devid)
1111 return qf->amcc;
1112 qf++;
1113 }
1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1115 return 0;
1116};
1117
1118static int pci_quatech_rqopr(struct uart_8250_port *port)
1119{
1120 unsigned long base = port->port.iobase;
1121 u8 LCR, val;
1122
1123 LCR = inb(base + UART_LCR);
1124 outb(0xBF, base + UART_LCR);
1125 val = inb(base + UART_SCR);
1126 outb(LCR, base + UART_LCR);
1127 return val;
1128}
1129
1130static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1131{
1132 unsigned long base = port->port.iobase;
1133 u8 LCR;
1134
1135 LCR = inb(base + UART_LCR);
1136 outb(0xBF, base + UART_LCR);
1137 inb(base + UART_SCR);
1138 outb(qopr, base + UART_SCR);
1139 outb(LCR, base + UART_LCR);
1140}
1141
1142static int pci_quatech_rqmcr(struct uart_8250_port *port)
1143{
1144 unsigned long base = port->port.iobase;
1145 u8 LCR, val, qmcr;
1146
1147 LCR = inb(base + UART_LCR);
1148 outb(0xBF, base + UART_LCR);
1149 val = inb(base + UART_SCR);
1150 outb(val | 0x10, base + UART_SCR);
1151 qmcr = inb(base + UART_MCR);
1152 outb(val, base + UART_SCR);
1153 outb(LCR, base + UART_LCR);
1154
1155 return qmcr;
1156}
1157
1158static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1159{
1160 unsigned long base = port->port.iobase;
1161 u8 LCR, val;
1162
1163 LCR = inb(base + UART_LCR);
1164 outb(0xBF, base + UART_LCR);
1165 val = inb(base + UART_SCR);
1166 outb(val | 0x10, base + UART_SCR);
1167 outb(qmcr, base + UART_MCR);
1168 outb(val, base + UART_SCR);
1169 outb(LCR, base + UART_LCR);
1170}
1171
1172static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1173{
1174 unsigned long base = port->port.iobase;
1175 u8 LCR, val;
1176
1177 LCR = inb(base + UART_LCR);
1178 outb(0xBF, base + UART_LCR);
1179 val = inb(base + UART_SCR);
1180 if (val & 0x20) {
1181 outb(0x80, UART_LCR);
1182 if (!(inb(UART_SCR) & 0x20)) {
1183 outb(LCR, base + UART_LCR);
1184 return 1;
1185 }
1186 }
1187 return 0;
1188}
1189
1190static int pci_quatech_test(struct uart_8250_port *port)
1191{
1192 u8 reg, qopr;
1193
1194 qopr = pci_quatech_rqopr(port);
1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1196 reg = pci_quatech_rqopr(port) & 0xC0;
1197 if (reg != QPCR_TEST_GET1)
1198 return -EINVAL;
1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1200 reg = pci_quatech_rqopr(port) & 0xC0;
1201 if (reg != QPCR_TEST_GET2)
1202 return -EINVAL;
1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET3)
1206 return -EINVAL;
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET4)
1210 return -EINVAL;
1211
1212 pci_quatech_wqopr(port, qopr);
1213 return 0;
1214}
1215
1216static int pci_quatech_clock(struct uart_8250_port *port)
1217{
1218 u8 qopr, reg, set;
1219 unsigned long clock;
1220
1221 if (pci_quatech_test(port) < 0)
1222 return 1843200;
1223
1224 qopr = pci_quatech_rqopr(port);
1225
1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1227 reg = pci_quatech_rqopr(port);
1228 if (reg & QOPR_CLOCK_X8) {
1229 clock = 1843200;
1230 goto out;
1231 }
1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1233 reg = pci_quatech_rqopr(port);
1234 if (!(reg & QOPR_CLOCK_X8)) {
1235 clock = 1843200;
1236 goto out;
1237 }
1238 reg &= QOPR_CLOCK_X8;
1239 if (reg == QOPR_CLOCK_X2) {
1240 clock = 3685400;
1241 set = QOPR_CLOCK_X2;
1242 } else if (reg == QOPR_CLOCK_X4) {
1243 clock = 7372800;
1244 set = QOPR_CLOCK_X4;
1245 } else if (reg == QOPR_CLOCK_X8) {
1246 clock = 14745600;
1247 set = QOPR_CLOCK_X8;
1248 } else {
1249 clock = 1843200;
1250 set = QOPR_CLOCK_X1;
1251 }
1252 qopr &= ~QOPR_CLOCK_RATE_MASK;
1253 qopr |= set;
1254
1255out:
1256 pci_quatech_wqopr(port, qopr);
1257 return clock;
1258}
1259
1260static int pci_quatech_rs422(struct uart_8250_port *port)
1261{
1262 u8 qmcr;
1263 int rs422 = 0;
1264
1265 if (!pci_quatech_has_qmcr(port))
1266 return 0;
1267 qmcr = pci_quatech_rqmcr(port);
1268 pci_quatech_wqmcr(port, 0xFF);
1269 if (pci_quatech_rqmcr(port))
1270 rs422 = 1;
1271 pci_quatech_wqmcr(port, qmcr);
1272 return rs422;
1273}
1274
1275static int pci_quatech_init(struct pci_dev *dev)
1276{
1277 if (pci_quatech_amcc(dev->device)) {
1278 unsigned long base = pci_resource_start(dev, 0);
1279 if (base) {
1280 u32 tmp;
1281
1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1283 tmp = inl(base + 0x3c);
1284 outl(tmp | 0x01000000, base + 0x3c);
1285 outl(tmp &= ~0x01000000, base + 0x3c);
1286 }
1287 }
1288 return 0;
1289}
1290
1291static int pci_quatech_setup(struct serial_private *priv,
1292 const struct pciserial_board *board,
1293 struct uart_8250_port *port, int idx)
1294{
1295
1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1297
1298 port->port.uartclk = pci_quatech_clock(port);
1299
1300 if (pci_quatech_rs422(port))
1301 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1302 return pci_default_setup(priv, board, port, idx);
1303}
1304
1305static void pci_quatech_exit(struct pci_dev *dev)
1306{
1307}
1308
1309static int pci_default_setup(struct serial_private *priv,
1310 const struct pciserial_board *board,
1311 struct uart_8250_port *port, int idx)
1312{
1313 unsigned int bar, offset = board->first_offset, maxnr;
1314
1315 bar = FL_GET_BASE(board->flags);
1316 if (board->flags & FL_BASE_BARS)
1317 bar += idx;
1318 else
1319 offset += idx * board->uart_offset;
1320
1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1322 (board->reg_shift + 3);
1323
1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1325 return 1;
1326
1327 return setup_port(priv, port, bar, offset, board->reg_shift);
1328}
1329
1330static int pci_pericom_setup(struct serial_private *priv,
1331 const struct pciserial_board *board,
1332 struct uart_8250_port *port, int idx)
1333{
1334 unsigned int bar, offset = board->first_offset, maxnr;
1335
1336 bar = FL_GET_BASE(board->flags);
1337 if (board->flags & FL_BASE_BARS)
1338 bar += idx;
1339 else
1340 offset += idx * board->uart_offset;
1341
1342 if (idx==3)
1343 offset = 0x38;
1344
1345 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1346 (board->reg_shift + 3);
1347
1348 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1349 return 1;
1350
1351 return setup_port(priv, port, bar, offset, board->reg_shift);
1352}
1353
1354static int
1355ce4100_serial_setup(struct serial_private *priv,
1356 const struct pciserial_board *board,
1357 struct uart_8250_port *port, int idx)
1358{
1359 int ret;
1360
1361 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1362 port->port.iotype = UPIO_MEM32;
1363 port->port.type = PORT_XSCALE;
1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1365 port->port.regshift = 2;
1366
1367 return ret;
1368}
1369
1370static int
1371pci_omegapci_setup(struct serial_private *priv,
1372 const struct pciserial_board *board,
1373 struct uart_8250_port *port, int idx)
1374{
1375 return setup_port(priv, port, 2, idx * 8, 0);
1376}
1377
1378static int
1379pci_brcm_trumanage_setup(struct serial_private *priv,
1380 const struct pciserial_board *board,
1381 struct uart_8250_port *port, int idx)
1382{
1383 int ret = pci_default_setup(priv, board, port, idx);
1384
1385 port->port.type = PORT_BRCM_TRUMANAGE;
1386 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1387 return ret;
1388}
1389
1390
1391#define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1392
1393#define FINTEK_RTS_INVERT BIT(5)
1394
1395
1396static int pci_fintek_rs485_config(struct uart_port *port,
1397 struct serial_rs485 *rs485)
1398{
1399 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1400 u8 setting;
1401 u8 *index = (u8 *) port->private_data;
1402
1403 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1404
1405 if (!rs485)
1406 rs485 = &port->rs485;
1407 else if (rs485->flags & SER_RS485_ENABLED)
1408 memset(rs485->padding, 0, sizeof(rs485->padding));
1409 else
1410 memset(rs485, 0, sizeof(*rs485));
1411
1412
1413 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1414
1415 if (rs485->flags & SER_RS485_ENABLED) {
1416
1417 setting |= FINTEK_RTS_CONTROL_BY_HW;
1418
1419 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1420
1421 setting &= ~FINTEK_RTS_INVERT;
1422 } else {
1423
1424 setting |= FINTEK_RTS_INVERT;
1425 }
1426
1427 rs485->delay_rts_after_send = 0;
1428 rs485->delay_rts_before_send = 0;
1429 } else {
1430
1431 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1432 }
1433
1434 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1435
1436 if (rs485 != &port->rs485)
1437 port->rs485 = *rs485;
1438
1439 return 0;
1440}
1441
1442static int pci_fintek_setup(struct serial_private *priv,
1443 const struct pciserial_board *board,
1444 struct uart_8250_port *port, int idx)
1445{
1446 struct pci_dev *pdev = priv->dev;
1447 u8 *data;
1448 u8 config_base;
1449 u16 iobase;
1450
1451 config_base = 0x40 + 0x08 * idx;
1452
1453
1454 pci_read_config_word(pdev, config_base + 4, &iobase);
1455
1456 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1457
1458 port->port.iotype = UPIO_PORT;
1459 port->port.iobase = iobase;
1460 port->port.rs485_config = pci_fintek_rs485_config;
1461
1462 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1463 if (!data)
1464 return -ENOMEM;
1465
1466
1467 *data = idx;
1468 port->port.private_data = data;
1469
1470 return 0;
1471}
1472
1473static int pci_fintek_init(struct pci_dev *dev)
1474{
1475 unsigned long iobase;
1476 u32 max_port, i;
1477 resource_size_t bar_data[3];
1478 u8 config_base;
1479 struct serial_private *priv = pci_get_drvdata(dev);
1480 struct uart_8250_port *port;
1481
1482 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1483 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1484 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1485 return -ENODEV;
1486
1487 switch (dev->device) {
1488 case 0x1104:
1489 case 0x1108:
1490 max_port = dev->device & 0xff;
1491 break;
1492 case 0x1112:
1493 max_port = 12;
1494 break;
1495 default:
1496 return -EINVAL;
1497 }
1498
1499
1500 bar_data[0] = pci_resource_start(dev, 5);
1501 bar_data[1] = pci_resource_start(dev, 4);
1502 bar_data[2] = pci_resource_start(dev, 3);
1503
1504 for (i = 0; i < max_port; ++i) {
1505
1506 config_base = 0x40 + 0x08 * i;
1507
1508
1509 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1510
1511
1512 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1513
1514
1515 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1516
1517
1518 pci_write_config_byte(dev, config_base + 0x04,
1519 (u8)(iobase & 0xff));
1520
1521
1522 pci_write_config_byte(dev, config_base + 0x05,
1523 (u8)((iobase & 0xff00) >> 8));
1524
1525 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1526
1527 if (priv) {
1528
1529
1530
1531 port = serial8250_get_port(priv->line[i]);
1532 pci_fintek_rs485_config(&port->port, NULL);
1533 } else {
1534
1535
1536
1537 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1538 }
1539 }
1540
1541 return max_port;
1542}
1543
1544static int skip_tx_en_setup(struct serial_private *priv,
1545 const struct pciserial_board *board,
1546 struct uart_8250_port *port, int idx)
1547{
1548 port->port.quirks |= UPQ_NO_TXEN_TEST;
1549 dev_dbg(&priv->dev->dev,
1550 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1551 priv->dev->vendor, priv->dev->device,
1552 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1553
1554 return pci_default_setup(priv, board, port, idx);
1555}
1556
1557static void kt_handle_break(struct uart_port *p)
1558{
1559 struct uart_8250_port *up = up_to_u8250p(p);
1560
1561
1562
1563
1564
1565 serial8250_clear_and_reinit_fifos(up);
1566}
1567
1568static unsigned int kt_serial_in(struct uart_port *p, int offset)
1569{
1570 struct uart_8250_port *up = up_to_u8250p(p);
1571 unsigned int val;
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583 val = inb(p->iobase + offset);
1584 if (offset == UART_IER) {
1585 if (val == 0)
1586 val = up->ier;
1587 }
1588 return val;
1589}
1590
1591static int kt_serial_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1594{
1595 port->port.flags |= UPF_BUG_THRE;
1596 port->port.serial_in = kt_serial_in;
1597 port->port.handle_break = kt_handle_break;
1598 return skip_tx_en_setup(priv, board, port, idx);
1599}
1600
1601static int pci_eg20t_init(struct pci_dev *dev)
1602{
1603#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1604 return -ENODEV;
1605#else
1606 return 0;
1607#endif
1608}
1609
1610static int
1611pci_wch_ch353_setup(struct serial_private *priv,
1612 const struct pciserial_board *board,
1613 struct uart_8250_port *port, int idx)
1614{
1615 port->port.flags |= UPF_FIXED_TYPE;
1616 port->port.type = PORT_16550A;
1617 return pci_default_setup(priv, board, port, idx);
1618}
1619
1620static int
1621pci_wch_ch355_setup(struct serial_private *priv,
1622 const struct pciserial_board *board,
1623 struct uart_8250_port *port, int idx)
1624{
1625 port->port.flags |= UPF_FIXED_TYPE;
1626 port->port.type = PORT_16550A;
1627 return pci_default_setup(priv, board, port, idx);
1628}
1629
1630static int
1631pci_wch_ch38x_setup(struct serial_private *priv,
1632 const struct pciserial_board *board,
1633 struct uart_8250_port *port, int idx)
1634{
1635 port->port.flags |= UPF_FIXED_TYPE;
1636 port->port.type = PORT_16850;
1637 return pci_default_setup(priv, board, port, idx);
1638}
1639
1640#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1641#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1642#define PCI_DEVICE_ID_OCTPRO 0x0001
1643#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1644#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1645#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1646#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1647#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1648#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1649#define PCI_VENDOR_ID_ADVANTECH 0x13fe
1650#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1651#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1652#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1653#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1654#define PCI_DEVICE_ID_TITAN_200I 0x8028
1655#define PCI_DEVICE_ID_TITAN_400I 0x8048
1656#define PCI_DEVICE_ID_TITAN_800I 0x8088
1657#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1658#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1659#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1660#define PCI_DEVICE_ID_TITAN_100E 0xA010
1661#define PCI_DEVICE_ID_TITAN_200E 0xA012
1662#define PCI_DEVICE_ID_TITAN_400E 0xA013
1663#define PCI_DEVICE_ID_TITAN_800E 0xA014
1664#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1665#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1666#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1667#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1668#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1669#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1670#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1671#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1672#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1673#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1674#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1675#define PCI_VENDOR_ID_WCH 0x4348
1676#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1677#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1678#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1679#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1680#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1681#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1682#define PCI_VENDOR_ID_AGESTAR 0x5372
1683#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1684#define PCI_VENDOR_ID_ASIX 0x9710
1685#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1686#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1687
1688#define PCIE_VENDOR_ID_WCH 0x1c00
1689#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1690#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1691#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1692
1693#define PCI_VENDOR_ID_PERICOM 0x12D8
1694#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1695#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1696#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1697#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1698
1699#define PCI_VENDOR_ID_ACCESIO 0x494f
1700#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1701#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1702#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1703#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1704#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1705#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1706#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1707#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1708#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1709#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1710#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1711#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1712#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1713#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1714#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1715#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1716#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1717#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1718#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1719#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1720#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1721#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1722#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1723#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1724#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1725#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1726#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1727#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1728#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1729#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1730#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1731#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1732#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1733
1734
1735
1736
1737#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1738#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1749
1750
1751
1752 {
1753 .vendor = PCI_VENDOR_ID_AMCC,
1754 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1755 .subvendor = PCI_ANY_ID,
1756 .subdevice = PCI_ANY_ID,
1757 .setup = addidata_apci7800_setup,
1758 },
1759
1760
1761
1762
1763 {
1764 .vendor = PCI_VENDOR_ID_AFAVLAB,
1765 .device = PCI_ANY_ID,
1766 .subvendor = PCI_ANY_ID,
1767 .subdevice = PCI_ANY_ID,
1768 .setup = afavlab_setup,
1769 },
1770
1771
1772
1773 {
1774 .vendor = PCI_VENDOR_ID_HP,
1775 .device = PCI_DEVICE_ID_HP_DIVA,
1776 .subvendor = PCI_ANY_ID,
1777 .subdevice = PCI_ANY_ID,
1778 .init = pci_hp_diva_init,
1779 .setup = pci_hp_diva_setup,
1780 },
1781
1782
1783
1784 {
1785 .vendor = PCI_VENDOR_ID_INTEL,
1786 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1787 .subvendor = 0xe4bf,
1788 .subdevice = PCI_ANY_ID,
1789 .init = pci_inteli960ni_init,
1790 .setup = pci_default_setup,
1791 },
1792 {
1793 .vendor = PCI_VENDOR_ID_INTEL,
1794 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1795 .subvendor = PCI_ANY_ID,
1796 .subdevice = PCI_ANY_ID,
1797 .setup = skip_tx_en_setup,
1798 },
1799 {
1800 .vendor = PCI_VENDOR_ID_INTEL,
1801 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1802 .subvendor = PCI_ANY_ID,
1803 .subdevice = PCI_ANY_ID,
1804 .setup = skip_tx_en_setup,
1805 },
1806 {
1807 .vendor = PCI_VENDOR_ID_INTEL,
1808 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1809 .subvendor = PCI_ANY_ID,
1810 .subdevice = PCI_ANY_ID,
1811 .setup = skip_tx_en_setup,
1812 },
1813 {
1814 .vendor = PCI_VENDOR_ID_INTEL,
1815 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1816 .subvendor = PCI_ANY_ID,
1817 .subdevice = PCI_ANY_ID,
1818 .setup = ce4100_serial_setup,
1819 },
1820 {
1821 .vendor = PCI_VENDOR_ID_INTEL,
1822 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1823 .subvendor = PCI_ANY_ID,
1824 .subdevice = PCI_ANY_ID,
1825 .setup = kt_serial_setup,
1826 },
1827
1828
1829
1830 {
1831 .vendor = PCI_VENDOR_ID_ITE,
1832 .device = PCI_DEVICE_ID_ITE_8872,
1833 .subvendor = PCI_ANY_ID,
1834 .subdevice = PCI_ANY_ID,
1835 .init = pci_ite887x_init,
1836 .setup = pci_default_setup,
1837 .exit = pci_ite887x_exit,
1838 },
1839
1840
1841
1842 {
1843 .vendor = PCI_VENDOR_ID_NI,
1844 .device = PCI_DEVICE_ID_NI_PCI23216,
1845 .subvendor = PCI_ANY_ID,
1846 .subdevice = PCI_ANY_ID,
1847 .init = pci_ni8420_init,
1848 .setup = pci_default_setup,
1849 .exit = pci_ni8420_exit,
1850 },
1851 {
1852 .vendor = PCI_VENDOR_ID_NI,
1853 .device = PCI_DEVICE_ID_NI_PCI2328,
1854 .subvendor = PCI_ANY_ID,
1855 .subdevice = PCI_ANY_ID,
1856 .init = pci_ni8420_init,
1857 .setup = pci_default_setup,
1858 .exit = pci_ni8420_exit,
1859 },
1860 {
1861 .vendor = PCI_VENDOR_ID_NI,
1862 .device = PCI_DEVICE_ID_NI_PCI2324,
1863 .subvendor = PCI_ANY_ID,
1864 .subdevice = PCI_ANY_ID,
1865 .init = pci_ni8420_init,
1866 .setup = pci_default_setup,
1867 .exit = pci_ni8420_exit,
1868 },
1869 {
1870 .vendor = PCI_VENDOR_ID_NI,
1871 .device = PCI_DEVICE_ID_NI_PCI2322,
1872 .subvendor = PCI_ANY_ID,
1873 .subdevice = PCI_ANY_ID,
1874 .init = pci_ni8420_init,
1875 .setup = pci_default_setup,
1876 .exit = pci_ni8420_exit,
1877 },
1878 {
1879 .vendor = PCI_VENDOR_ID_NI,
1880 .device = PCI_DEVICE_ID_NI_PCI2324I,
1881 .subvendor = PCI_ANY_ID,
1882 .subdevice = PCI_ANY_ID,
1883 .init = pci_ni8420_init,
1884 .setup = pci_default_setup,
1885 .exit = pci_ni8420_exit,
1886 },
1887 {
1888 .vendor = PCI_VENDOR_ID_NI,
1889 .device = PCI_DEVICE_ID_NI_PCI2322I,
1890 .subvendor = PCI_ANY_ID,
1891 .subdevice = PCI_ANY_ID,
1892 .init = pci_ni8420_init,
1893 .setup = pci_default_setup,
1894 .exit = pci_ni8420_exit,
1895 },
1896 {
1897 .vendor = PCI_VENDOR_ID_NI,
1898 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1899 .subvendor = PCI_ANY_ID,
1900 .subdevice = PCI_ANY_ID,
1901 .init = pci_ni8420_init,
1902 .setup = pci_default_setup,
1903 .exit = pci_ni8420_exit,
1904 },
1905 {
1906 .vendor = PCI_VENDOR_ID_NI,
1907 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1908 .subvendor = PCI_ANY_ID,
1909 .subdevice = PCI_ANY_ID,
1910 .init = pci_ni8420_init,
1911 .setup = pci_default_setup,
1912 .exit = pci_ni8420_exit,
1913 },
1914 {
1915 .vendor = PCI_VENDOR_ID_NI,
1916 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1917 .subvendor = PCI_ANY_ID,
1918 .subdevice = PCI_ANY_ID,
1919 .init = pci_ni8420_init,
1920 .setup = pci_default_setup,
1921 .exit = pci_ni8420_exit,
1922 },
1923 {
1924 .vendor = PCI_VENDOR_ID_NI,
1925 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1926 .subvendor = PCI_ANY_ID,
1927 .subdevice = PCI_ANY_ID,
1928 .init = pci_ni8420_init,
1929 .setup = pci_default_setup,
1930 .exit = pci_ni8420_exit,
1931 },
1932 {
1933 .vendor = PCI_VENDOR_ID_NI,
1934 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 .init = pci_ni8420_init,
1938 .setup = pci_default_setup,
1939 .exit = pci_ni8420_exit,
1940 },
1941 {
1942 .vendor = PCI_VENDOR_ID_NI,
1943 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1944 .subvendor = PCI_ANY_ID,
1945 .subdevice = PCI_ANY_ID,
1946 .init = pci_ni8420_init,
1947 .setup = pci_default_setup,
1948 .exit = pci_ni8420_exit,
1949 },
1950 {
1951 .vendor = PCI_VENDOR_ID_NI,
1952 .device = PCI_ANY_ID,
1953 .subvendor = PCI_ANY_ID,
1954 .subdevice = PCI_ANY_ID,
1955 .init = pci_ni8430_init,
1956 .setup = pci_ni8430_setup,
1957 .exit = pci_ni8430_exit,
1958 },
1959
1960 {
1961 .vendor = PCI_VENDOR_ID_QUATECH,
1962 .device = PCI_ANY_ID,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .init = pci_quatech_init,
1966 .setup = pci_quatech_setup,
1967 .exit = pci_quatech_exit,
1968 },
1969
1970
1971
1972 {
1973 .vendor = PCI_VENDOR_ID_PANACOM,
1974 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1975 .subvendor = PCI_ANY_ID,
1976 .subdevice = PCI_ANY_ID,
1977 .init = pci_plx9050_init,
1978 .setup = pci_default_setup,
1979 .exit = pci_plx9050_exit,
1980 },
1981 {
1982 .vendor = PCI_VENDOR_ID_PANACOM,
1983 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1984 .subvendor = PCI_ANY_ID,
1985 .subdevice = PCI_ANY_ID,
1986 .init = pci_plx9050_init,
1987 .setup = pci_default_setup,
1988 .exit = pci_plx9050_exit,
1989 },
1990
1991
1992
1993 {
1994 .vendor = PCI_VENDOR_ID_PERICOM,
1995 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .setup = pci_pericom_setup,
1999 },
2000
2001
2002
2003 {
2004 .vendor = PCI_VENDOR_ID_PLX,
2005 .device = PCI_DEVICE_ID_PLX_9050,
2006 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2007 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2008 .init = pci_plx9050_init,
2009 .setup = pci_default_setup,
2010 .exit = pci_plx9050_exit,
2011 },
2012 {
2013 .vendor = PCI_VENDOR_ID_PLX,
2014 .device = PCI_DEVICE_ID_PLX_9050,
2015 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2016 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2017 .init = pci_plx9050_init,
2018 .setup = pci_default_setup,
2019 .exit = pci_plx9050_exit,
2020 },
2021 {
2022 .vendor = PCI_VENDOR_ID_PLX,
2023 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2024 .subvendor = PCI_VENDOR_ID_PLX,
2025 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2026 .init = pci_plx9050_init,
2027 .setup = pci_default_setup,
2028 .exit = pci_plx9050_exit,
2029 },
2030
2031
2032
2033 {
2034 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2035 .device = PCI_DEVICE_ID_OCTPRO,
2036 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2037 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2038 .init = sbs_init,
2039 .setup = sbs_setup,
2040 .exit = sbs_exit,
2041 },
2042
2043
2044
2045 {
2046 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2047 .device = PCI_DEVICE_ID_OCTPRO,
2048 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2049 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2050 .init = sbs_init,
2051 .setup = sbs_setup,
2052 .exit = sbs_exit,
2053 },
2054
2055
2056
2057 {
2058 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2059 .device = PCI_DEVICE_ID_OCTPRO,
2060 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2061 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2062 .init = sbs_init,
2063 .setup = sbs_setup,
2064 .exit = sbs_exit,
2065 },
2066
2067
2068
2069 {
2070 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2071 .device = PCI_DEVICE_ID_OCTPRO,
2072 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2073 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2074 .init = sbs_init,
2075 .setup = sbs_setup,
2076 .exit = sbs_exit,
2077 },
2078
2079
2080
2081 {
2082 .vendor = PCI_VENDOR_ID_SIIG,
2083 .device = PCI_ANY_ID,
2084 .subvendor = PCI_ANY_ID,
2085 .subdevice = PCI_ANY_ID,
2086 .init = pci_siig_init,
2087 .setup = pci_siig_setup,
2088 },
2089
2090
2091
2092 {
2093 .vendor = PCI_VENDOR_ID_TITAN,
2094 .device = PCI_DEVICE_ID_TITAN_400L,
2095 .subvendor = PCI_ANY_ID,
2096 .subdevice = PCI_ANY_ID,
2097 .setup = titan_400l_800l_setup,
2098 },
2099 {
2100 .vendor = PCI_VENDOR_ID_TITAN,
2101 .device = PCI_DEVICE_ID_TITAN_800L,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .setup = titan_400l_800l_setup,
2105 },
2106
2107
2108
2109 {
2110 .vendor = PCI_VENDOR_ID_TIMEDIA,
2111 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2112 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2113 .subdevice = PCI_ANY_ID,
2114 .probe = pci_timedia_probe,
2115 .init = pci_timedia_init,
2116 .setup = pci_timedia_setup,
2117 },
2118 {
2119 .vendor = PCI_VENDOR_ID_TIMEDIA,
2120 .device = PCI_ANY_ID,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = pci_timedia_setup,
2124 },
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134 {
2135 .vendor = PCI_VENDOR_ID_SUNIX,
2136 .device = PCI_DEVICE_ID_SUNIX_1999,
2137 .subvendor = PCI_VENDOR_ID_SUNIX,
2138 .subdevice = PCI_ANY_ID,
2139 .init = pci_timedia_init,
2140 .setup = pci_timedia_setup,
2141 },
2142
2143
2144
2145 {
2146 .vendor = PCI_VENDOR_ID_XIRCOM,
2147 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2148 .subvendor = PCI_ANY_ID,
2149 .subdevice = PCI_ANY_ID,
2150 .init = pci_xircom_init,
2151 .setup = pci_default_setup,
2152 },
2153
2154
2155
2156 {
2157 .vendor = PCI_VENDOR_ID_NETMOS,
2158 .device = PCI_ANY_ID,
2159 .subvendor = PCI_ANY_ID,
2160 .subdevice = PCI_ANY_ID,
2161 .init = pci_netmos_init,
2162 .setup = pci_netmos_9900_setup,
2163 },
2164
2165
2166
2167 {
2168 .vendor = PCI_VENDOR_ID_ENDRUN,
2169 .device = PCI_ANY_ID,
2170 .subvendor = PCI_ANY_ID,
2171 .subdevice = PCI_ANY_ID,
2172 .init = pci_endrun_init,
2173 .setup = pci_default_setup,
2174 },
2175
2176
2177
2178 {
2179 .vendor = PCI_VENDOR_ID_OXSEMI,
2180 .device = PCI_ANY_ID,
2181 .subvendor = PCI_ANY_ID,
2182 .subdevice = PCI_ANY_ID,
2183 .init = pci_oxsemi_tornado_init,
2184 .setup = pci_default_setup,
2185 },
2186 {
2187 .vendor = PCI_VENDOR_ID_MAINPINE,
2188 .device = PCI_ANY_ID,
2189 .subvendor = PCI_ANY_ID,
2190 .subdevice = PCI_ANY_ID,
2191 .init = pci_oxsemi_tornado_init,
2192 .setup = pci_default_setup,
2193 },
2194 {
2195 .vendor = PCI_VENDOR_ID_DIGI,
2196 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2197 .subvendor = PCI_SUBVENDOR_ID_IBM,
2198 .subdevice = PCI_ANY_ID,
2199 .init = pci_oxsemi_tornado_init,
2200 .setup = pci_default_setup,
2201 },
2202 {
2203 .vendor = PCI_VENDOR_ID_INTEL,
2204 .device = 0x8811,
2205 .subvendor = PCI_ANY_ID,
2206 .subdevice = PCI_ANY_ID,
2207 .init = pci_eg20t_init,
2208 .setup = pci_default_setup,
2209 },
2210 {
2211 .vendor = PCI_VENDOR_ID_INTEL,
2212 .device = 0x8812,
2213 .subvendor = PCI_ANY_ID,
2214 .subdevice = PCI_ANY_ID,
2215 .init = pci_eg20t_init,
2216 .setup = pci_default_setup,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_INTEL,
2220 .device = 0x8813,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .init = pci_eg20t_init,
2224 .setup = pci_default_setup,
2225 },
2226 {
2227 .vendor = PCI_VENDOR_ID_INTEL,
2228 .device = 0x8814,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .init = pci_eg20t_init,
2232 .setup = pci_default_setup,
2233 },
2234 {
2235 .vendor = 0x10DB,
2236 .device = 0x8027,
2237 .subvendor = PCI_ANY_ID,
2238 .subdevice = PCI_ANY_ID,
2239 .init = pci_eg20t_init,
2240 .setup = pci_default_setup,
2241 },
2242 {
2243 .vendor = 0x10DB,
2244 .device = 0x8028,
2245 .subvendor = PCI_ANY_ID,
2246 .subdevice = PCI_ANY_ID,
2247 .init = pci_eg20t_init,
2248 .setup = pci_default_setup,
2249 },
2250 {
2251 .vendor = 0x10DB,
2252 .device = 0x8029,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .init = pci_eg20t_init,
2256 .setup = pci_default_setup,
2257 },
2258 {
2259 .vendor = 0x10DB,
2260 .device = 0x800C,
2261 .subvendor = PCI_ANY_ID,
2262 .subdevice = PCI_ANY_ID,
2263 .init = pci_eg20t_init,
2264 .setup = pci_default_setup,
2265 },
2266 {
2267 .vendor = 0x10DB,
2268 .device = 0x800D,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .init = pci_eg20t_init,
2272 .setup = pci_default_setup,
2273 },
2274
2275
2276
2277 {
2278 .vendor = PCI_VENDOR_ID_PLX,
2279 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .setup = pci_omegapci_setup,
2283 },
2284
2285 {
2286 .vendor = PCI_VENDOR_ID_WCH,
2287 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2288 .subvendor = PCI_ANY_ID,
2289 .subdevice = PCI_ANY_ID,
2290 .setup = pci_wch_ch353_setup,
2291 },
2292
2293 {
2294 .vendor = PCI_VENDOR_ID_WCH,
2295 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .setup = pci_wch_ch353_setup,
2299 },
2300
2301 {
2302 .vendor = PCI_VENDOR_ID_WCH,
2303 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .setup = pci_wch_ch353_setup,
2307 },
2308
2309 {
2310 .vendor = PCI_VENDOR_ID_WCH,
2311 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
2314 .setup = pci_wch_ch353_setup,
2315 },
2316
2317 {
2318 .vendor = PCI_VENDOR_ID_WCH,
2319 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .setup = pci_wch_ch353_setup,
2323 },
2324
2325 {
2326 .vendor = PCI_VENDOR_ID_WCH,
2327 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .setup = pci_wch_ch355_setup,
2331 },
2332
2333 {
2334 .vendor = PCIE_VENDOR_ID_WCH,
2335 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .setup = pci_wch_ch38x_setup,
2339 },
2340
2341 {
2342 .vendor = PCIE_VENDOR_ID_WCH,
2343 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2344 .subvendor = PCI_ANY_ID,
2345 .subdevice = PCI_ANY_ID,
2346 .setup = pci_wch_ch38x_setup,
2347 },
2348
2349 {
2350 .vendor = PCIE_VENDOR_ID_WCH,
2351 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .setup = pci_wch_ch38x_setup,
2355 },
2356
2357
2358
2359 {
2360 .vendor = PCI_VENDOR_ID_ASIX,
2361 .device = PCI_ANY_ID,
2362 .subvendor = PCI_ANY_ID,
2363 .subdevice = PCI_ANY_ID,
2364 .setup = pci_asix_setup,
2365 },
2366
2367
2368
2369 {
2370 .vendor = PCI_VENDOR_ID_BROADCOM,
2371 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2372 .subvendor = PCI_ANY_ID,
2373 .subdevice = PCI_ANY_ID,
2374 .setup = pci_brcm_trumanage_setup,
2375 },
2376 {
2377 .vendor = 0x1c29,
2378 .device = 0x1104,
2379 .subvendor = PCI_ANY_ID,
2380 .subdevice = PCI_ANY_ID,
2381 .setup = pci_fintek_setup,
2382 .init = pci_fintek_init,
2383 },
2384 {
2385 .vendor = 0x1c29,
2386 .device = 0x1108,
2387 .subvendor = PCI_ANY_ID,
2388 .subdevice = PCI_ANY_ID,
2389 .setup = pci_fintek_setup,
2390 .init = pci_fintek_init,
2391 },
2392 {
2393 .vendor = 0x1c29,
2394 .device = 0x1112,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .setup = pci_fintek_setup,
2398 .init = pci_fintek_init,
2399 },
2400
2401
2402
2403
2404 {
2405 .vendor = PCI_ANY_ID,
2406 .device = PCI_ANY_ID,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .setup = pci_default_setup,
2410 }
2411};
2412
2413static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2414{
2415 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2416}
2417
2418static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2419{
2420 struct pci_serial_quirk *quirk;
2421
2422 for (quirk = pci_serial_quirks; ; quirk++)
2423 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2424 quirk_id_matches(quirk->device, dev->device) &&
2425 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2426 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2427 break;
2428 return quirk;
2429}
2430
2431static inline int get_pci_irq(struct pci_dev *dev,
2432 const struct pciserial_board *board)
2433{
2434 if (board->flags & FL_NOIRQ)
2435 return 0;
2436 else
2437 return dev->irq;
2438}
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460enum pci_board_num_t {
2461 pbn_default = 0,
2462
2463 pbn_b0_1_115200,
2464 pbn_b0_2_115200,
2465 pbn_b0_4_115200,
2466 pbn_b0_5_115200,
2467 pbn_b0_8_115200,
2468
2469 pbn_b0_1_921600,
2470 pbn_b0_2_921600,
2471 pbn_b0_4_921600,
2472
2473 pbn_b0_2_1130000,
2474
2475 pbn_b0_4_1152000,
2476
2477 pbn_b0_4_1250000,
2478
2479 pbn_b0_2_1843200,
2480 pbn_b0_4_1843200,
2481
2482 pbn_b0_1_4000000,
2483
2484 pbn_b0_bt_1_115200,
2485 pbn_b0_bt_2_115200,
2486 pbn_b0_bt_4_115200,
2487 pbn_b0_bt_8_115200,
2488
2489 pbn_b0_bt_1_460800,
2490 pbn_b0_bt_2_460800,
2491 pbn_b0_bt_4_460800,
2492
2493 pbn_b0_bt_1_921600,
2494 pbn_b0_bt_2_921600,
2495 pbn_b0_bt_4_921600,
2496 pbn_b0_bt_8_921600,
2497
2498 pbn_b1_1_115200,
2499 pbn_b1_2_115200,
2500 pbn_b1_4_115200,
2501 pbn_b1_8_115200,
2502 pbn_b1_16_115200,
2503
2504 pbn_b1_1_921600,
2505 pbn_b1_2_921600,
2506 pbn_b1_4_921600,
2507 pbn_b1_8_921600,
2508
2509 pbn_b1_2_1250000,
2510
2511 pbn_b1_bt_1_115200,
2512 pbn_b1_bt_2_115200,
2513 pbn_b1_bt_4_115200,
2514
2515 pbn_b1_bt_2_921600,
2516
2517 pbn_b1_1_1382400,
2518 pbn_b1_2_1382400,
2519 pbn_b1_4_1382400,
2520 pbn_b1_8_1382400,
2521
2522 pbn_b2_1_115200,
2523 pbn_b2_2_115200,
2524 pbn_b2_4_115200,
2525 pbn_b2_8_115200,
2526
2527 pbn_b2_1_460800,
2528 pbn_b2_4_460800,
2529 pbn_b2_8_460800,
2530 pbn_b2_16_460800,
2531
2532 pbn_b2_1_921600,
2533 pbn_b2_4_921600,
2534 pbn_b2_8_921600,
2535
2536 pbn_b2_8_1152000,
2537
2538 pbn_b2_bt_1_115200,
2539 pbn_b2_bt_2_115200,
2540 pbn_b2_bt_4_115200,
2541
2542 pbn_b2_bt_2_921600,
2543 pbn_b2_bt_4_921600,
2544
2545 pbn_b3_2_115200,
2546 pbn_b3_4_115200,
2547 pbn_b3_8_115200,
2548
2549 pbn_b4_bt_2_921600,
2550 pbn_b4_bt_4_921600,
2551 pbn_b4_bt_8_921600,
2552
2553
2554
2555
2556 pbn_panacom,
2557 pbn_panacom2,
2558 pbn_panacom4,
2559 pbn_plx_romulus,
2560 pbn_endrun_2_4000000,
2561 pbn_oxsemi,
2562 pbn_oxsemi_1_4000000,
2563 pbn_oxsemi_2_4000000,
2564 pbn_oxsemi_4_4000000,
2565 pbn_oxsemi_8_4000000,
2566 pbn_intel_i960,
2567 pbn_sgi_ioc3,
2568 pbn_computone_4,
2569 pbn_computone_6,
2570 pbn_computone_8,
2571 pbn_sbsxrsio,
2572 pbn_pasemi_1682M,
2573 pbn_ni8430_2,
2574 pbn_ni8430_4,
2575 pbn_ni8430_8,
2576 pbn_ni8430_16,
2577 pbn_ADDIDATA_PCIe_1_3906250,
2578 pbn_ADDIDATA_PCIe_2_3906250,
2579 pbn_ADDIDATA_PCIe_4_3906250,
2580 pbn_ADDIDATA_PCIe_8_3906250,
2581 pbn_ce4100_1_115200,
2582 pbn_omegapci,
2583 pbn_NETMOS9900_2s_115200,
2584 pbn_brcm_trumanage,
2585 pbn_fintek_4,
2586 pbn_fintek_8,
2587 pbn_fintek_12,
2588 pbn_wch382_2,
2589 pbn_wch384_4,
2590 pbn_pericom_PI7C9X7951,
2591 pbn_pericom_PI7C9X7952,
2592 pbn_pericom_PI7C9X7954,
2593 pbn_pericom_PI7C9X7958,
2594};
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606static struct pciserial_board pci_boards[] = {
2607 [pbn_default] = {
2608 .flags = FL_BASE0,
2609 .num_ports = 1,
2610 .base_baud = 115200,
2611 .uart_offset = 8,
2612 },
2613 [pbn_b0_1_115200] = {
2614 .flags = FL_BASE0,
2615 .num_ports = 1,
2616 .base_baud = 115200,
2617 .uart_offset = 8,
2618 },
2619 [pbn_b0_2_115200] = {
2620 .flags = FL_BASE0,
2621 .num_ports = 2,
2622 .base_baud = 115200,
2623 .uart_offset = 8,
2624 },
2625 [pbn_b0_4_115200] = {
2626 .flags = FL_BASE0,
2627 .num_ports = 4,
2628 .base_baud = 115200,
2629 .uart_offset = 8,
2630 },
2631 [pbn_b0_5_115200] = {
2632 .flags = FL_BASE0,
2633 .num_ports = 5,
2634 .base_baud = 115200,
2635 .uart_offset = 8,
2636 },
2637 [pbn_b0_8_115200] = {
2638 .flags = FL_BASE0,
2639 .num_ports = 8,
2640 .base_baud = 115200,
2641 .uart_offset = 8,
2642 },
2643 [pbn_b0_1_921600] = {
2644 .flags = FL_BASE0,
2645 .num_ports = 1,
2646 .base_baud = 921600,
2647 .uart_offset = 8,
2648 },
2649 [pbn_b0_2_921600] = {
2650 .flags = FL_BASE0,
2651 .num_ports = 2,
2652 .base_baud = 921600,
2653 .uart_offset = 8,
2654 },
2655 [pbn_b0_4_921600] = {
2656 .flags = FL_BASE0,
2657 .num_ports = 4,
2658 .base_baud = 921600,
2659 .uart_offset = 8,
2660 },
2661
2662 [pbn_b0_2_1130000] = {
2663 .flags = FL_BASE0,
2664 .num_ports = 2,
2665 .base_baud = 1130000,
2666 .uart_offset = 8,
2667 },
2668
2669 [pbn_b0_4_1152000] = {
2670 .flags = FL_BASE0,
2671 .num_ports = 4,
2672 .base_baud = 1152000,
2673 .uart_offset = 8,
2674 },
2675
2676 [pbn_b0_4_1250000] = {
2677 .flags = FL_BASE0,
2678 .num_ports = 4,
2679 .base_baud = 1250000,
2680 .uart_offset = 8,
2681 },
2682
2683 [pbn_b0_2_1843200] = {
2684 .flags = FL_BASE0,
2685 .num_ports = 2,
2686 .base_baud = 1843200,
2687 .uart_offset = 8,
2688 },
2689 [pbn_b0_4_1843200] = {
2690 .flags = FL_BASE0,
2691 .num_ports = 4,
2692 .base_baud = 1843200,
2693 .uart_offset = 8,
2694 },
2695
2696 [pbn_b0_1_4000000] = {
2697 .flags = FL_BASE0,
2698 .num_ports = 1,
2699 .base_baud = 4000000,
2700 .uart_offset = 8,
2701 },
2702
2703 [pbn_b0_bt_1_115200] = {
2704 .flags = FL_BASE0|FL_BASE_BARS,
2705 .num_ports = 1,
2706 .base_baud = 115200,
2707 .uart_offset = 8,
2708 },
2709 [pbn_b0_bt_2_115200] = {
2710 .flags = FL_BASE0|FL_BASE_BARS,
2711 .num_ports = 2,
2712 .base_baud = 115200,
2713 .uart_offset = 8,
2714 },
2715 [pbn_b0_bt_4_115200] = {
2716 .flags = FL_BASE0|FL_BASE_BARS,
2717 .num_ports = 4,
2718 .base_baud = 115200,
2719 .uart_offset = 8,
2720 },
2721 [pbn_b0_bt_8_115200] = {
2722 .flags = FL_BASE0|FL_BASE_BARS,
2723 .num_ports = 8,
2724 .base_baud = 115200,
2725 .uart_offset = 8,
2726 },
2727
2728 [pbn_b0_bt_1_460800] = {
2729 .flags = FL_BASE0|FL_BASE_BARS,
2730 .num_ports = 1,
2731 .base_baud = 460800,
2732 .uart_offset = 8,
2733 },
2734 [pbn_b0_bt_2_460800] = {
2735 .flags = FL_BASE0|FL_BASE_BARS,
2736 .num_ports = 2,
2737 .base_baud = 460800,
2738 .uart_offset = 8,
2739 },
2740 [pbn_b0_bt_4_460800] = {
2741 .flags = FL_BASE0|FL_BASE_BARS,
2742 .num_ports = 4,
2743 .base_baud = 460800,
2744 .uart_offset = 8,
2745 },
2746
2747 [pbn_b0_bt_1_921600] = {
2748 .flags = FL_BASE0|FL_BASE_BARS,
2749 .num_ports = 1,
2750 .base_baud = 921600,
2751 .uart_offset = 8,
2752 },
2753 [pbn_b0_bt_2_921600] = {
2754 .flags = FL_BASE0|FL_BASE_BARS,
2755 .num_ports = 2,
2756 .base_baud = 921600,
2757 .uart_offset = 8,
2758 },
2759 [pbn_b0_bt_4_921600] = {
2760 .flags = FL_BASE0|FL_BASE_BARS,
2761 .num_ports = 4,
2762 .base_baud = 921600,
2763 .uart_offset = 8,
2764 },
2765 [pbn_b0_bt_8_921600] = {
2766 .flags = FL_BASE0|FL_BASE_BARS,
2767 .num_ports = 8,
2768 .base_baud = 921600,
2769 .uart_offset = 8,
2770 },
2771
2772 [pbn_b1_1_115200] = {
2773 .flags = FL_BASE1,
2774 .num_ports = 1,
2775 .base_baud = 115200,
2776 .uart_offset = 8,
2777 },
2778 [pbn_b1_2_115200] = {
2779 .flags = FL_BASE1,
2780 .num_ports = 2,
2781 .base_baud = 115200,
2782 .uart_offset = 8,
2783 },
2784 [pbn_b1_4_115200] = {
2785 .flags = FL_BASE1,
2786 .num_ports = 4,
2787 .base_baud = 115200,
2788 .uart_offset = 8,
2789 },
2790 [pbn_b1_8_115200] = {
2791 .flags = FL_BASE1,
2792 .num_ports = 8,
2793 .base_baud = 115200,
2794 .uart_offset = 8,
2795 },
2796 [pbn_b1_16_115200] = {
2797 .flags = FL_BASE1,
2798 .num_ports = 16,
2799 .base_baud = 115200,
2800 .uart_offset = 8,
2801 },
2802
2803 [pbn_b1_1_921600] = {
2804 .flags = FL_BASE1,
2805 .num_ports = 1,
2806 .base_baud = 921600,
2807 .uart_offset = 8,
2808 },
2809 [pbn_b1_2_921600] = {
2810 .flags = FL_BASE1,
2811 .num_ports = 2,
2812 .base_baud = 921600,
2813 .uart_offset = 8,
2814 },
2815 [pbn_b1_4_921600] = {
2816 .flags = FL_BASE1,
2817 .num_ports = 4,
2818 .base_baud = 921600,
2819 .uart_offset = 8,
2820 },
2821 [pbn_b1_8_921600] = {
2822 .flags = FL_BASE1,
2823 .num_ports = 8,
2824 .base_baud = 921600,
2825 .uart_offset = 8,
2826 },
2827 [pbn_b1_2_1250000] = {
2828 .flags = FL_BASE1,
2829 .num_ports = 2,
2830 .base_baud = 1250000,
2831 .uart_offset = 8,
2832 },
2833
2834 [pbn_b1_bt_1_115200] = {
2835 .flags = FL_BASE1|FL_BASE_BARS,
2836 .num_ports = 1,
2837 .base_baud = 115200,
2838 .uart_offset = 8,
2839 },
2840 [pbn_b1_bt_2_115200] = {
2841 .flags = FL_BASE1|FL_BASE_BARS,
2842 .num_ports = 2,
2843 .base_baud = 115200,
2844 .uart_offset = 8,
2845 },
2846 [pbn_b1_bt_4_115200] = {
2847 .flags = FL_BASE1|FL_BASE_BARS,
2848 .num_ports = 4,
2849 .base_baud = 115200,
2850 .uart_offset = 8,
2851 },
2852
2853 [pbn_b1_bt_2_921600] = {
2854 .flags = FL_BASE1|FL_BASE_BARS,
2855 .num_ports = 2,
2856 .base_baud = 921600,
2857 .uart_offset = 8,
2858 },
2859
2860 [pbn_b1_1_1382400] = {
2861 .flags = FL_BASE1,
2862 .num_ports = 1,
2863 .base_baud = 1382400,
2864 .uart_offset = 8,
2865 },
2866 [pbn_b1_2_1382400] = {
2867 .flags = FL_BASE1,
2868 .num_ports = 2,
2869 .base_baud = 1382400,
2870 .uart_offset = 8,
2871 },
2872 [pbn_b1_4_1382400] = {
2873 .flags = FL_BASE1,
2874 .num_ports = 4,
2875 .base_baud = 1382400,
2876 .uart_offset = 8,
2877 },
2878 [pbn_b1_8_1382400] = {
2879 .flags = FL_BASE1,
2880 .num_ports = 8,
2881 .base_baud = 1382400,
2882 .uart_offset = 8,
2883 },
2884
2885 [pbn_b2_1_115200] = {
2886 .flags = FL_BASE2,
2887 .num_ports = 1,
2888 .base_baud = 115200,
2889 .uart_offset = 8,
2890 },
2891 [pbn_b2_2_115200] = {
2892 .flags = FL_BASE2,
2893 .num_ports = 2,
2894 .base_baud = 115200,
2895 .uart_offset = 8,
2896 },
2897 [pbn_b2_4_115200] = {
2898 .flags = FL_BASE2,
2899 .num_ports = 4,
2900 .base_baud = 115200,
2901 .uart_offset = 8,
2902 },
2903 [pbn_b2_8_115200] = {
2904 .flags = FL_BASE2,
2905 .num_ports = 8,
2906 .base_baud = 115200,
2907 .uart_offset = 8,
2908 },
2909
2910 [pbn_b2_1_460800] = {
2911 .flags = FL_BASE2,
2912 .num_ports = 1,
2913 .base_baud = 460800,
2914 .uart_offset = 8,
2915 },
2916 [pbn_b2_4_460800] = {
2917 .flags = FL_BASE2,
2918 .num_ports = 4,
2919 .base_baud = 460800,
2920 .uart_offset = 8,
2921 },
2922 [pbn_b2_8_460800] = {
2923 .flags = FL_BASE2,
2924 .num_ports = 8,
2925 .base_baud = 460800,
2926 .uart_offset = 8,
2927 },
2928 [pbn_b2_16_460800] = {
2929 .flags = FL_BASE2,
2930 .num_ports = 16,
2931 .base_baud = 460800,
2932 .uart_offset = 8,
2933 },
2934
2935 [pbn_b2_1_921600] = {
2936 .flags = FL_BASE2,
2937 .num_ports = 1,
2938 .base_baud = 921600,
2939 .uart_offset = 8,
2940 },
2941 [pbn_b2_4_921600] = {
2942 .flags = FL_BASE2,
2943 .num_ports = 4,
2944 .base_baud = 921600,
2945 .uart_offset = 8,
2946 },
2947 [pbn_b2_8_921600] = {
2948 .flags = FL_BASE2,
2949 .num_ports = 8,
2950 .base_baud = 921600,
2951 .uart_offset = 8,
2952 },
2953
2954 [pbn_b2_8_1152000] = {
2955 .flags = FL_BASE2,
2956 .num_ports = 8,
2957 .base_baud = 1152000,
2958 .uart_offset = 8,
2959 },
2960
2961 [pbn_b2_bt_1_115200] = {
2962 .flags = FL_BASE2|FL_BASE_BARS,
2963 .num_ports = 1,
2964 .base_baud = 115200,
2965 .uart_offset = 8,
2966 },
2967 [pbn_b2_bt_2_115200] = {
2968 .flags = FL_BASE2|FL_BASE_BARS,
2969 .num_ports = 2,
2970 .base_baud = 115200,
2971 .uart_offset = 8,
2972 },
2973 [pbn_b2_bt_4_115200] = {
2974 .flags = FL_BASE2|FL_BASE_BARS,
2975 .num_ports = 4,
2976 .base_baud = 115200,
2977 .uart_offset = 8,
2978 },
2979
2980 [pbn_b2_bt_2_921600] = {
2981 .flags = FL_BASE2|FL_BASE_BARS,
2982 .num_ports = 2,
2983 .base_baud = 921600,
2984 .uart_offset = 8,
2985 },
2986 [pbn_b2_bt_4_921600] = {
2987 .flags = FL_BASE2|FL_BASE_BARS,
2988 .num_ports = 4,
2989 .base_baud = 921600,
2990 .uart_offset = 8,
2991 },
2992
2993 [pbn_b3_2_115200] = {
2994 .flags = FL_BASE3,
2995 .num_ports = 2,
2996 .base_baud = 115200,
2997 .uart_offset = 8,
2998 },
2999 [pbn_b3_4_115200] = {
3000 .flags = FL_BASE3,
3001 .num_ports = 4,
3002 .base_baud = 115200,
3003 .uart_offset = 8,
3004 },
3005 [pbn_b3_8_115200] = {
3006 .flags = FL_BASE3,
3007 .num_ports = 8,
3008 .base_baud = 115200,
3009 .uart_offset = 8,
3010 },
3011
3012 [pbn_b4_bt_2_921600] = {
3013 .flags = FL_BASE4,
3014 .num_ports = 2,
3015 .base_baud = 921600,
3016 .uart_offset = 8,
3017 },
3018 [pbn_b4_bt_4_921600] = {
3019 .flags = FL_BASE4,
3020 .num_ports = 4,
3021 .base_baud = 921600,
3022 .uart_offset = 8,
3023 },
3024 [pbn_b4_bt_8_921600] = {
3025 .flags = FL_BASE4,
3026 .num_ports = 8,
3027 .base_baud = 921600,
3028 .uart_offset = 8,
3029 },
3030
3031
3032
3033
3034
3035
3036
3037
3038 [pbn_panacom] = {
3039 .flags = FL_BASE2,
3040 .num_ports = 2,
3041 .base_baud = 921600,
3042 .uart_offset = 0x400,
3043 .reg_shift = 7,
3044 },
3045 [pbn_panacom2] = {
3046 .flags = FL_BASE2|FL_BASE_BARS,
3047 .num_ports = 2,
3048 .base_baud = 921600,
3049 .uart_offset = 0x400,
3050 .reg_shift = 7,
3051 },
3052 [pbn_panacom4] = {
3053 .flags = FL_BASE2|FL_BASE_BARS,
3054 .num_ports = 4,
3055 .base_baud = 921600,
3056 .uart_offset = 0x400,
3057 .reg_shift = 7,
3058 },
3059
3060
3061 [pbn_plx_romulus] = {
3062 .flags = FL_BASE2,
3063 .num_ports = 4,
3064 .base_baud = 921600,
3065 .uart_offset = 8 << 2,
3066 .reg_shift = 2,
3067 .first_offset = 0x03,
3068 },
3069
3070
3071
3072
3073
3074
3075
3076 [pbn_endrun_2_4000000] = {
3077 .flags = FL_BASE0,
3078 .num_ports = 2,
3079 .base_baud = 4000000,
3080 .uart_offset = 0x200,
3081 .first_offset = 0x1000,
3082 },
3083
3084
3085
3086
3087
3088 [pbn_oxsemi] = {
3089 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3090 .num_ports = 32,
3091 .base_baud = 115200,
3092 .uart_offset = 8,
3093 },
3094 [pbn_oxsemi_1_4000000] = {
3095 .flags = FL_BASE0,
3096 .num_ports = 1,
3097 .base_baud = 4000000,
3098 .uart_offset = 0x200,
3099 .first_offset = 0x1000,
3100 },
3101 [pbn_oxsemi_2_4000000] = {
3102 .flags = FL_BASE0,
3103 .num_ports = 2,
3104 .base_baud = 4000000,
3105 .uart_offset = 0x200,
3106 .first_offset = 0x1000,
3107 },
3108 [pbn_oxsemi_4_4000000] = {
3109 .flags = FL_BASE0,
3110 .num_ports = 4,
3111 .base_baud = 4000000,
3112 .uart_offset = 0x200,
3113 .first_offset = 0x1000,
3114 },
3115 [pbn_oxsemi_8_4000000] = {
3116 .flags = FL_BASE0,
3117 .num_ports = 8,
3118 .base_baud = 4000000,
3119 .uart_offset = 0x200,
3120 .first_offset = 0x1000,
3121 },
3122
3123
3124
3125
3126
3127
3128 [pbn_intel_i960] = {
3129 .flags = FL_BASE0,
3130 .num_ports = 32,
3131 .base_baud = 921600,
3132 .uart_offset = 8 << 2,
3133 .reg_shift = 2,
3134 .first_offset = 0x10000,
3135 },
3136 [pbn_sgi_ioc3] = {
3137 .flags = FL_BASE0|FL_NOIRQ,
3138 .num_ports = 1,
3139 .base_baud = 458333,
3140 .uart_offset = 8,
3141 .reg_shift = 0,
3142 .first_offset = 0x20178,
3143 },
3144
3145
3146
3147
3148 [pbn_computone_4] = {
3149 .flags = FL_BASE0,
3150 .num_ports = 4,
3151 .base_baud = 921600,
3152 .uart_offset = 0x40,
3153 .reg_shift = 2,
3154 .first_offset = 0x200,
3155 },
3156 [pbn_computone_6] = {
3157 .flags = FL_BASE0,
3158 .num_ports = 6,
3159 .base_baud = 921600,
3160 .uart_offset = 0x40,
3161 .reg_shift = 2,
3162 .first_offset = 0x200,
3163 },
3164 [pbn_computone_8] = {
3165 .flags = FL_BASE0,
3166 .num_ports = 8,
3167 .base_baud = 921600,
3168 .uart_offset = 0x40,
3169 .reg_shift = 2,
3170 .first_offset = 0x200,
3171 },
3172 [pbn_sbsxrsio] = {
3173 .flags = FL_BASE0,
3174 .num_ports = 8,
3175 .base_baud = 460800,
3176 .uart_offset = 256,
3177 .reg_shift = 4,
3178 },
3179
3180
3181
3182 [pbn_pasemi_1682M] = {
3183 .flags = FL_BASE0,
3184 .num_ports = 1,
3185 .base_baud = 8333333,
3186 },
3187
3188
3189
3190 [pbn_ni8430_16] = {
3191 .flags = FL_BASE0,
3192 .num_ports = 16,
3193 .base_baud = 3686400,
3194 .uart_offset = 0x10,
3195 .first_offset = 0x800,
3196 },
3197 [pbn_ni8430_8] = {
3198 .flags = FL_BASE0,
3199 .num_ports = 8,
3200 .base_baud = 3686400,
3201 .uart_offset = 0x10,
3202 .first_offset = 0x800,
3203 },
3204 [pbn_ni8430_4] = {
3205 .flags = FL_BASE0,
3206 .num_ports = 4,
3207 .base_baud = 3686400,
3208 .uart_offset = 0x10,
3209 .first_offset = 0x800,
3210 },
3211 [pbn_ni8430_2] = {
3212 .flags = FL_BASE0,
3213 .num_ports = 2,
3214 .base_baud = 3686400,
3215 .uart_offset = 0x10,
3216 .first_offset = 0x800,
3217 },
3218
3219
3220
3221 [pbn_ADDIDATA_PCIe_1_3906250] = {
3222 .flags = FL_BASE0,
3223 .num_ports = 1,
3224 .base_baud = 3906250,
3225 .uart_offset = 0x200,
3226 .first_offset = 0x1000,
3227 },
3228 [pbn_ADDIDATA_PCIe_2_3906250] = {
3229 .flags = FL_BASE0,
3230 .num_ports = 2,
3231 .base_baud = 3906250,
3232 .uart_offset = 0x200,
3233 .first_offset = 0x1000,
3234 },
3235 [pbn_ADDIDATA_PCIe_4_3906250] = {
3236 .flags = FL_BASE0,
3237 .num_ports = 4,
3238 .base_baud = 3906250,
3239 .uart_offset = 0x200,
3240 .first_offset = 0x1000,
3241 },
3242 [pbn_ADDIDATA_PCIe_8_3906250] = {
3243 .flags = FL_BASE0,
3244 .num_ports = 8,
3245 .base_baud = 3906250,
3246 .uart_offset = 0x200,
3247 .first_offset = 0x1000,
3248 },
3249 [pbn_ce4100_1_115200] = {
3250 .flags = FL_BASE_BARS,
3251 .num_ports = 2,
3252 .base_baud = 921600,
3253 .reg_shift = 2,
3254 },
3255 [pbn_omegapci] = {
3256 .flags = FL_BASE0,
3257 .num_ports = 8,
3258 .base_baud = 115200,
3259 .uart_offset = 0x200,
3260 },
3261 [pbn_NETMOS9900_2s_115200] = {
3262 .flags = FL_BASE0,
3263 .num_ports = 2,
3264 .base_baud = 115200,
3265 },
3266 [pbn_brcm_trumanage] = {
3267 .flags = FL_BASE0,
3268 .num_ports = 1,
3269 .reg_shift = 2,
3270 .base_baud = 115200,
3271 },
3272 [pbn_fintek_4] = {
3273 .num_ports = 4,
3274 .uart_offset = 8,
3275 .base_baud = 115200,
3276 .first_offset = 0x40,
3277 },
3278 [pbn_fintek_8] = {
3279 .num_ports = 8,
3280 .uart_offset = 8,
3281 .base_baud = 115200,
3282 .first_offset = 0x40,
3283 },
3284 [pbn_fintek_12] = {
3285 .num_ports = 12,
3286 .uart_offset = 8,
3287 .base_baud = 115200,
3288 .first_offset = 0x40,
3289 },
3290 [pbn_wch382_2] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 2,
3293 .base_baud = 115200,
3294 .uart_offset = 8,
3295 .first_offset = 0xC0,
3296 },
3297 [pbn_wch384_4] = {
3298 .flags = FL_BASE0,
3299 .num_ports = 4,
3300 .base_baud = 115200,
3301 .uart_offset = 8,
3302 .first_offset = 0xC0,
3303 },
3304
3305
3306
3307 [pbn_pericom_PI7C9X7951] = {
3308 .flags = FL_BASE0,
3309 .num_ports = 1,
3310 .base_baud = 921600,
3311 .uart_offset = 0x8,
3312 },
3313 [pbn_pericom_PI7C9X7952] = {
3314 .flags = FL_BASE0,
3315 .num_ports = 2,
3316 .base_baud = 921600,
3317 .uart_offset = 0x8,
3318 },
3319 [pbn_pericom_PI7C9X7954] = {
3320 .flags = FL_BASE0,
3321 .num_ports = 4,
3322 .base_baud = 921600,
3323 .uart_offset = 0x8,
3324 },
3325 [pbn_pericom_PI7C9X7958] = {
3326 .flags = FL_BASE0,
3327 .num_ports = 8,
3328 .base_baud = 921600,
3329 .uart_offset = 0x8,
3330 },
3331};
3332
3333static const struct pci_device_id blacklist[] = {
3334
3335 { PCI_VDEVICE(AL, 0x5457), },
3336 { PCI_VDEVICE(MOTOROLA, 0x3052), },
3337 { PCI_DEVICE(0x1543, 0x3052), },
3338
3339
3340 { PCI_DEVICE(0x4348, 0x7053), },
3341 { PCI_DEVICE(0x4348, 0x5053), },
3342 { PCI_DEVICE(0x4348, 0x7173), },
3343 { PCI_DEVICE(0x1c00, 0x3250), },
3344 { PCI_DEVICE(0x1c00, 0x3470), },
3345
3346
3347 { PCI_VDEVICE(MOXA, 0x1024), },
3348 { PCI_VDEVICE(MOXA, 0x1025), },
3349 { PCI_VDEVICE(MOXA, 0x1045), },
3350 { PCI_VDEVICE(MOXA, 0x1144), },
3351 { PCI_VDEVICE(MOXA, 0x1160), },
3352 { PCI_VDEVICE(MOXA, 0x1161), },
3353 { PCI_VDEVICE(MOXA, 0x1182), },
3354 { PCI_VDEVICE(MOXA, 0x1183), },
3355 { PCI_VDEVICE(MOXA, 0x1322), },
3356 { PCI_VDEVICE(MOXA, 0x1342), },
3357 { PCI_VDEVICE(MOXA, 0x1381), },
3358 { PCI_VDEVICE(MOXA, 0x1683), },
3359
3360
3361 { PCI_VDEVICE(INTEL, 0x081b), },
3362 { PCI_VDEVICE(INTEL, 0x081c), },
3363 { PCI_VDEVICE(INTEL, 0x081d), },
3364 { PCI_VDEVICE(INTEL, 0x1191), },
3365 { PCI_VDEVICE(INTEL, 0x18d8), },
3366 { PCI_VDEVICE(INTEL, 0x19d8), },
3367
3368
3369 { PCI_VDEVICE(INTEL, 0x0936), },
3370 { PCI_VDEVICE(INTEL, 0x0f0a), },
3371 { PCI_VDEVICE(INTEL, 0x0f0c), },
3372 { PCI_VDEVICE(INTEL, 0x228a), },
3373 { PCI_VDEVICE(INTEL, 0x228c), },
3374 { PCI_VDEVICE(INTEL, 0x9ce3), },
3375 { PCI_VDEVICE(INTEL, 0x9ce4), },
3376
3377
3378 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3379 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3380};
3381
3382static int serial_pci_is_class_communication(struct pci_dev *dev)
3383{
3384
3385
3386
3387
3388 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3389 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3390 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3391 (dev->class & 0xff) > 6)
3392 return -ENODEV;
3393
3394 return 0;
3395}
3396
3397static int serial_pci_is_blacklisted(struct pci_dev *dev)
3398{
3399 const struct pci_device_id *bldev;
3400
3401
3402
3403
3404
3405 for (bldev = blacklist;
3406 bldev < blacklist + ARRAY_SIZE(blacklist);
3407 bldev++) {
3408 if (dev->vendor == bldev->vendor &&
3409 dev->device == bldev->device)
3410 return -ENODEV;
3411 }
3412
3413 return 0;
3414}
3415
3416
3417
3418
3419
3420
3421static int
3422serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3423{
3424 int num_iomem, num_port, first_port = -1, i;
3425
3426
3427
3428
3429 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3430 return -ENODEV;
3431
3432 num_iomem = num_port = 0;
3433 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3434 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3435 num_port++;
3436 if (first_port == -1)
3437 first_port = i;
3438 }
3439 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3440 num_iomem++;
3441 }
3442
3443
3444
3445
3446
3447
3448 if (num_iomem <= 1 && num_port == 1) {
3449 board->flags = first_port;
3450 board->num_ports = pci_resource_len(dev, first_port) / 8;
3451 return 0;
3452 }
3453
3454
3455
3456
3457
3458
3459 first_port = -1;
3460 num_port = 0;
3461 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3462 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3463 pci_resource_len(dev, i) == 8 &&
3464 (first_port == -1 || (first_port + num_port) == i)) {
3465 num_port++;
3466 if (first_port == -1)
3467 first_port = i;
3468 }
3469 }
3470
3471 if (num_port > 1) {
3472 board->flags = first_port | FL_BASE_BARS;
3473 board->num_ports = num_port;
3474 return 0;
3475 }
3476
3477 return -ENODEV;
3478}
3479
3480static inline int
3481serial_pci_matches(const struct pciserial_board *board,
3482 const struct pciserial_board *guessed)
3483{
3484 return
3485 board->num_ports == guessed->num_ports &&
3486 board->base_baud == guessed->base_baud &&
3487 board->uart_offset == guessed->uart_offset &&
3488 board->reg_shift == guessed->reg_shift &&
3489 board->first_offset == guessed->first_offset;
3490}
3491
3492struct serial_private *
3493pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3494{
3495 struct uart_8250_port uart;
3496 struct serial_private *priv;
3497 struct pci_serial_quirk *quirk;
3498 int rc, nr_ports, i;
3499
3500 nr_ports = board->num_ports;
3501
3502
3503
3504
3505 quirk = find_quirk(dev);
3506
3507
3508
3509
3510
3511
3512
3513
3514 if (quirk->init) {
3515 rc = quirk->init(dev);
3516 if (rc < 0) {
3517 priv = ERR_PTR(rc);
3518 goto err_out;
3519 }
3520 if (rc)
3521 nr_ports = rc;
3522 }
3523
3524 priv = kzalloc(sizeof(struct serial_private) +
3525 sizeof(unsigned int) * nr_ports,
3526 GFP_KERNEL);
3527 if (!priv) {
3528 priv = ERR_PTR(-ENOMEM);
3529 goto err_deinit;
3530 }
3531
3532 priv->dev = dev;
3533 priv->quirk = quirk;
3534
3535 memset(&uart, 0, sizeof(uart));
3536 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3537 uart.port.uartclk = board->base_baud * 16;
3538 uart.port.irq = get_pci_irq(dev, board);
3539 uart.port.dev = &dev->dev;
3540
3541 for (i = 0; i < nr_ports; i++) {
3542 if (quirk->setup(priv, board, &uart, i))
3543 break;
3544
3545 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3546 uart.port.iobase, uart.port.irq, uart.port.iotype);
3547
3548 priv->line[i] = serial8250_register_8250_port(&uart);
3549 if (priv->line[i] < 0) {
3550 dev_err(&dev->dev,
3551 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3552 uart.port.iobase, uart.port.irq,
3553 uart.port.iotype, priv->line[i]);
3554 break;
3555 }
3556 }
3557 priv->nr = i;
3558 priv->board = board;
3559 return priv;
3560
3561err_deinit:
3562 if (quirk->exit)
3563 quirk->exit(dev);
3564err_out:
3565 return priv;
3566}
3567EXPORT_SYMBOL_GPL(pciserial_init_ports);
3568
3569static void pciserial_detach_ports(struct serial_private *priv)
3570{
3571 struct pci_serial_quirk *quirk;
3572 int i;
3573
3574 for (i = 0; i < priv->nr; i++)
3575 serial8250_unregister_port(priv->line[i]);
3576
3577
3578
3579
3580 quirk = find_quirk(priv->dev);
3581 if (quirk->exit)
3582 quirk->exit(priv->dev);
3583}
3584
3585void pciserial_remove_ports(struct serial_private *priv)
3586{
3587 pciserial_detach_ports(priv);
3588 kfree(priv);
3589}
3590EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3591
3592void pciserial_suspend_ports(struct serial_private *priv)
3593{
3594 int i;
3595
3596 for (i = 0; i < priv->nr; i++)
3597 if (priv->line[i] >= 0)
3598 serial8250_suspend_port(priv->line[i]);
3599
3600
3601
3602
3603 if (priv->quirk->exit)
3604 priv->quirk->exit(priv->dev);
3605}
3606EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3607
3608void pciserial_resume_ports(struct serial_private *priv)
3609{
3610 int i;
3611
3612
3613
3614
3615 if (priv->quirk->init)
3616 priv->quirk->init(priv->dev);
3617
3618 for (i = 0; i < priv->nr; i++)
3619 if (priv->line[i] >= 0)
3620 serial8250_resume_port(priv->line[i]);
3621}
3622EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3623
3624
3625
3626
3627
3628static int
3629pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3630{
3631 struct pci_serial_quirk *quirk;
3632 struct serial_private *priv;
3633 const struct pciserial_board *board;
3634 struct pciserial_board tmp;
3635 int rc;
3636
3637 quirk = find_quirk(dev);
3638 if (quirk->probe) {
3639 rc = quirk->probe(dev);
3640 if (rc)
3641 return rc;
3642 }
3643
3644 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3645 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3646 ent->driver_data);
3647 return -EINVAL;
3648 }
3649
3650 board = &pci_boards[ent->driver_data];
3651
3652 rc = serial_pci_is_class_communication(dev);
3653 if (rc)
3654 return rc;
3655
3656 rc = serial_pci_is_blacklisted(dev);
3657 if (rc)
3658 return rc;
3659
3660 rc = pcim_enable_device(dev);
3661 pci_save_state(dev);
3662 if (rc)
3663 return rc;
3664
3665 if (ent->driver_data == pbn_default) {
3666
3667
3668
3669
3670 memcpy(&tmp, board, sizeof(struct pciserial_board));
3671 board = &tmp;
3672
3673
3674
3675
3676
3677 rc = serial_pci_guess_board(dev, &tmp);
3678 if (rc)
3679 return rc;
3680 } else {
3681
3682
3683
3684
3685
3686 memcpy(&tmp, &pci_boards[pbn_default],
3687 sizeof(struct pciserial_board));
3688 rc = serial_pci_guess_board(dev, &tmp);
3689 if (rc == 0 && serial_pci_matches(board, &tmp))
3690 moan_device("Redundant entry in serial pci_table.",
3691 dev);
3692 }
3693
3694 priv = pciserial_init_ports(dev, board);
3695 if (IS_ERR(priv))
3696 return PTR_ERR(priv);
3697
3698 pci_set_drvdata(dev, priv);
3699 return 0;
3700}
3701
3702static void pciserial_remove_one(struct pci_dev *dev)
3703{
3704 struct serial_private *priv = pci_get_drvdata(dev);
3705
3706 pciserial_remove_ports(priv);
3707}
3708
3709#ifdef CONFIG_PM_SLEEP
3710static int pciserial_suspend_one(struct device *dev)
3711{
3712 struct pci_dev *pdev = to_pci_dev(dev);
3713 struct serial_private *priv = pci_get_drvdata(pdev);
3714
3715 if (priv)
3716 pciserial_suspend_ports(priv);
3717
3718 return 0;
3719}
3720
3721static int pciserial_resume_one(struct device *dev)
3722{
3723 struct pci_dev *pdev = to_pci_dev(dev);
3724 struct serial_private *priv = pci_get_drvdata(pdev);
3725 int err;
3726
3727 if (priv) {
3728
3729
3730
3731 err = pci_enable_device(pdev);
3732
3733 if (err)
3734 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3735 pciserial_resume_ports(priv);
3736 }
3737 return 0;
3738}
3739#endif
3740
3741static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3742 pciserial_resume_one);
3743
3744static const struct pci_device_id serial_pci_tbl[] = {
3745
3746 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3747 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3748 pbn_b2_8_921600 },
3749
3750 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3751 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3752 pbn_b0_4_921600 },
3753 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3754 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3755 pbn_b0_4_921600 },
3756 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3757 PCI_SUBVENDOR_ID_CONNECT_TECH,
3758 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3759 pbn_b1_8_1382400 },
3760 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3761 PCI_SUBVENDOR_ID_CONNECT_TECH,
3762 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3763 pbn_b1_4_1382400 },
3764 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3765 PCI_SUBVENDOR_ID_CONNECT_TECH,
3766 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3767 pbn_b1_2_1382400 },
3768 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3769 PCI_SUBVENDOR_ID_CONNECT_TECH,
3770 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3771 pbn_b1_8_1382400 },
3772 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3773 PCI_SUBVENDOR_ID_CONNECT_TECH,
3774 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3775 pbn_b1_4_1382400 },
3776 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3777 PCI_SUBVENDOR_ID_CONNECT_TECH,
3778 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3779 pbn_b1_2_1382400 },
3780 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3781 PCI_SUBVENDOR_ID_CONNECT_TECH,
3782 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3783 pbn_b1_8_921600 },
3784 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3785 PCI_SUBVENDOR_ID_CONNECT_TECH,
3786 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3787 pbn_b1_8_921600 },
3788 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3789 PCI_SUBVENDOR_ID_CONNECT_TECH,
3790 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3791 pbn_b1_4_921600 },
3792 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3793 PCI_SUBVENDOR_ID_CONNECT_TECH,
3794 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3795 pbn_b1_4_921600 },
3796 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3797 PCI_SUBVENDOR_ID_CONNECT_TECH,
3798 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3799 pbn_b1_2_921600 },
3800 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3801 PCI_SUBVENDOR_ID_CONNECT_TECH,
3802 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3803 pbn_b1_8_921600 },
3804 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3805 PCI_SUBVENDOR_ID_CONNECT_TECH,
3806 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3807 pbn_b1_8_921600 },
3808 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3809 PCI_SUBVENDOR_ID_CONNECT_TECH,
3810 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3811 pbn_b1_4_921600 },
3812 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3813 PCI_SUBVENDOR_ID_CONNECT_TECH,
3814 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3815 pbn_b1_2_1250000 },
3816 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3817 PCI_SUBVENDOR_ID_CONNECT_TECH,
3818 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3819 pbn_b0_2_1843200 },
3820 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3821 PCI_SUBVENDOR_ID_CONNECT_TECH,
3822 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3823 pbn_b0_4_1843200 },
3824 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3825 PCI_VENDOR_ID_AFAVLAB,
3826 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3827 pbn_b0_4_1152000 },
3828 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830 pbn_b2_bt_1_115200 },
3831 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3833 pbn_b2_bt_2_115200 },
3834 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3836 pbn_b2_bt_4_115200 },
3837 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839 pbn_b2_bt_2_115200 },
3840 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3842 pbn_b2_bt_4_115200 },
3843 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845 pbn_b2_8_115200 },
3846 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3848 pbn_b2_8_460800 },
3849 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3851 pbn_b2_8_115200 },
3852
3853 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3855 pbn_b2_bt_2_115200 },
3856 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3858 pbn_b2_bt_2_921600 },
3859
3860
3861
3862 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3864 pbn_b2_8_921600 },
3865 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3867 pbn_b2_4_921600 },
3868
3869 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3870 PCI_VENDOR_ID_PLX,
3871 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3872 pbn_b2_4_115200 },
3873
3874 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3875 PCI_VENDOR_ID_PLX,
3876 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3877 pbn_b2_8_115200 },
3878 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3879 PCI_SUBVENDOR_ID_KEYSPAN,
3880 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3881 pbn_panacom },
3882 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3884 pbn_panacom4 },
3885 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3887 pbn_panacom2 },
3888 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3889 PCI_VENDOR_ID_ESDGMBH,
3890 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3891 pbn_b2_4_115200 },
3892 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3893 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3894 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3895 pbn_b2_4_460800 },
3896 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3897 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3898 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3899 pbn_b2_8_460800 },
3900 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3901 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3902 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3903 pbn_b2_16_460800 },
3904 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3905 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3906 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3907 pbn_b2_16_460800 },
3908 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3909 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3910 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3911 pbn_b2_4_460800 },
3912 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3913 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3914 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3915 pbn_b2_8_460800 },
3916 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3917 PCI_SUBVENDOR_ID_EXSYS,
3918 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3919 pbn_b2_4_115200 },
3920
3921
3922
3923
3924 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3925 0x10b5, 0x106a, 0, 0,
3926 pbn_plx_romulus },
3927
3928
3929
3930
3931 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
3932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3933 pbn_endrun_2_4000000 },
3934
3935
3936
3937
3938
3939
3940 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942 pbn_b1_4_115200 },
3943 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945 pbn_b1_2_115200 },
3946 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948 pbn_b2_2_115200 },
3949 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951 pbn_b1_2_115200 },
3952 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3954 pbn_b2_2_115200 },
3955 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3957 pbn_b1_4_115200 },
3958 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3960 pbn_b1_8_115200 },
3961 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3963 pbn_b1_8_115200 },
3964 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3966 pbn_b1_4_115200 },
3967 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3969 pbn_b1_2_115200 },
3970 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3972 pbn_b1_4_115200 },
3973 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3975 pbn_b1_2_115200 },
3976 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3978 pbn_b2_4_115200 },
3979 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3981 pbn_b2_2_115200 },
3982 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3984 pbn_b2_1_115200 },
3985 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3987 pbn_b2_4_115200 },
3988 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3990 pbn_b2_2_115200 },
3991 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3993 pbn_b2_1_115200 },
3994 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3996 pbn_b0_8_115200 },
3997
3998 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3999 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4000 0, 0,
4001 pbn_b0_4_921600 },
4002 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4003 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4004 0, 0,
4005 pbn_b0_4_1152000 },
4006 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4008 pbn_b0_bt_2_921600 },
4009
4010
4011
4012
4013
4014
4015
4016 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4017 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4018 0, 0, pbn_b0_2_115200 },
4019 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4020 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4021 0, 0, pbn_b0_2_115200 },
4022 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4024 pbn_b0_2_1130000 },
4025 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4026 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4027 pbn_b0_1_921600 },
4028 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4030 pbn_b0_4_115200 },
4031 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4033 pbn_b0_bt_2_921600 },
4034 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4036 pbn_b2_8_1152000 },
4037
4038
4039
4040
4041 { PCI_VENDOR_ID_OXSEMI, 0xc101,
4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4043 pbn_b0_1_4000000 },
4044 { PCI_VENDOR_ID_OXSEMI, 0xc105,
4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4046 pbn_b0_1_4000000 },
4047 { PCI_VENDOR_ID_OXSEMI, 0xc11b,
4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4049 pbn_oxsemi_1_4000000 },
4050 { PCI_VENDOR_ID_OXSEMI, 0xc11f,
4051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4052 pbn_oxsemi_1_4000000 },
4053 { PCI_VENDOR_ID_OXSEMI, 0xc120,
4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4055 pbn_b0_1_4000000 },
4056 { PCI_VENDOR_ID_OXSEMI, 0xc124,
4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4058 pbn_b0_1_4000000 },
4059 { PCI_VENDOR_ID_OXSEMI, 0xc138,
4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4061 pbn_oxsemi_1_4000000 },
4062 { PCI_VENDOR_ID_OXSEMI, 0xc13d,
4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4064 pbn_oxsemi_1_4000000 },
4065 { PCI_VENDOR_ID_OXSEMI, 0xc140,
4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4067 pbn_b0_1_4000000 },
4068 { PCI_VENDOR_ID_OXSEMI, 0xc141,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 pbn_b0_1_4000000 },
4071 { PCI_VENDOR_ID_OXSEMI, 0xc144,
4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4073 pbn_b0_1_4000000 },
4074 { PCI_VENDOR_ID_OXSEMI, 0xc145,
4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076 pbn_b0_1_4000000 },
4077 { PCI_VENDOR_ID_OXSEMI, 0xc158,
4078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4079 pbn_oxsemi_2_4000000 },
4080 { PCI_VENDOR_ID_OXSEMI, 0xc15d,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082 pbn_oxsemi_2_4000000 },
4083 { PCI_VENDOR_ID_OXSEMI, 0xc208,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 pbn_oxsemi_4_4000000 },
4086 { PCI_VENDOR_ID_OXSEMI, 0xc20d,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 pbn_oxsemi_4_4000000 },
4089 { PCI_VENDOR_ID_OXSEMI, 0xc308,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 pbn_oxsemi_8_4000000 },
4092 { PCI_VENDOR_ID_OXSEMI, 0xc30d,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_oxsemi_8_4000000 },
4095 { PCI_VENDOR_ID_OXSEMI, 0xc40b,
4096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097 pbn_oxsemi_1_4000000 },
4098 { PCI_VENDOR_ID_OXSEMI, 0xc40f,
4099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100 pbn_oxsemi_1_4000000 },
4101 { PCI_VENDOR_ID_OXSEMI, 0xc41b,
4102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 pbn_oxsemi_1_4000000 },
4104 { PCI_VENDOR_ID_OXSEMI, 0xc41f,
4105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106 pbn_oxsemi_1_4000000 },
4107 { PCI_VENDOR_ID_OXSEMI, 0xc42b,
4108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 pbn_oxsemi_1_4000000 },
4110 { PCI_VENDOR_ID_OXSEMI, 0xc42f,
4111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112 pbn_oxsemi_1_4000000 },
4113 { PCI_VENDOR_ID_OXSEMI, 0xc43b,
4114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4115 pbn_oxsemi_1_4000000 },
4116 { PCI_VENDOR_ID_OXSEMI, 0xc43f,
4117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118 pbn_oxsemi_1_4000000 },
4119 { PCI_VENDOR_ID_OXSEMI, 0xc44b,
4120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4121 pbn_oxsemi_1_4000000 },
4122 { PCI_VENDOR_ID_OXSEMI, 0xc44f,
4123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4124 pbn_oxsemi_1_4000000 },
4125 { PCI_VENDOR_ID_OXSEMI, 0xc45b,
4126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4127 pbn_oxsemi_1_4000000 },
4128 { PCI_VENDOR_ID_OXSEMI, 0xc45f,
4129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130 pbn_oxsemi_1_4000000 },
4131 { PCI_VENDOR_ID_OXSEMI, 0xc46b,
4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4133 pbn_oxsemi_1_4000000 },
4134 { PCI_VENDOR_ID_OXSEMI, 0xc46f,
4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4136 pbn_oxsemi_1_4000000 },
4137 { PCI_VENDOR_ID_OXSEMI, 0xc47b,
4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139 pbn_oxsemi_1_4000000 },
4140 { PCI_VENDOR_ID_OXSEMI, 0xc47f,
4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142 pbn_oxsemi_1_4000000 },
4143 { PCI_VENDOR_ID_OXSEMI, 0xc48b,
4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4145 pbn_oxsemi_1_4000000 },
4146 { PCI_VENDOR_ID_OXSEMI, 0xc48f,
4147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4148 pbn_oxsemi_1_4000000 },
4149 { PCI_VENDOR_ID_OXSEMI, 0xc49b,
4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151 pbn_oxsemi_1_4000000 },
4152 { PCI_VENDOR_ID_OXSEMI, 0xc49f,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 pbn_oxsemi_1_4000000 },
4155 { PCI_VENDOR_ID_OXSEMI, 0xc4ab,
4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4157 pbn_oxsemi_1_4000000 },
4158 { PCI_VENDOR_ID_OXSEMI, 0xc4af,
4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4160 pbn_oxsemi_1_4000000 },
4161 { PCI_VENDOR_ID_OXSEMI, 0xc4bb,
4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163 pbn_oxsemi_1_4000000 },
4164 { PCI_VENDOR_ID_OXSEMI, 0xc4bf,
4165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4166 pbn_oxsemi_1_4000000 },
4167 { PCI_VENDOR_ID_OXSEMI, 0xc4cb,
4168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4169 pbn_oxsemi_1_4000000 },
4170 { PCI_VENDOR_ID_OXSEMI, 0xc4cf,
4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172 pbn_oxsemi_1_4000000 },
4173
4174
4175
4176 { PCI_VENDOR_ID_MAINPINE, 0x4000,
4177 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4178 pbn_oxsemi_1_4000000 },
4179 { PCI_VENDOR_ID_MAINPINE, 0x4000,
4180 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4181 pbn_oxsemi_2_4000000 },
4182 { PCI_VENDOR_ID_MAINPINE, 0x4000,
4183 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4184 pbn_oxsemi_4_4000000 },
4185 { PCI_VENDOR_ID_MAINPINE, 0x4000,
4186 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4187 pbn_oxsemi_8_4000000 },
4188
4189
4190
4191
4192 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4193 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4194 pbn_oxsemi_2_4000000 },
4195
4196
4197
4198
4199
4200 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4201 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4202 pbn_sbsxrsio },
4203 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4204 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4205 pbn_sbsxrsio },
4206 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4207 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4208 pbn_sbsxrsio },
4209 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4210 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4211 pbn_sbsxrsio },
4212
4213
4214
4215
4216 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218 pbn_b1_1_115200 },
4219
4220
4221
4222
4223
4224 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226 pbn_b0_1_921600 },
4227 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229 pbn_b0_2_921600 },
4230 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232 pbn_b0_4_921600 },
4233 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235 pbn_b0_4_921600 },
4236 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238 pbn_b1_1_921600 },
4239 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4241 pbn_b1_bt_2_921600 },
4242 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4244 pbn_b0_bt_4_921600 },
4245 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4247 pbn_b0_bt_8_921600 },
4248 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4250 pbn_b4_bt_2_921600 },
4251 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4253 pbn_b4_bt_4_921600 },
4254 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4256 pbn_b4_bt_8_921600 },
4257 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4259 pbn_b0_4_921600 },
4260 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262 pbn_b0_4_921600 },
4263 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4265 pbn_b0_4_921600 },
4266 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268 pbn_oxsemi_1_4000000 },
4269 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4271 pbn_oxsemi_2_4000000 },
4272 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4274 pbn_oxsemi_4_4000000 },
4275 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4277 pbn_oxsemi_8_4000000 },
4278 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280 pbn_oxsemi_2_4000000 },
4281 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283 pbn_oxsemi_2_4000000 },
4284 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286 pbn_b0_bt_2_921600 },
4287 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 pbn_b0_4_921600 },
4290 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292 pbn_b0_4_921600 },
4293 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295 pbn_b0_4_921600 },
4296 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_b0_4_921600 },
4299
4300 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4302 pbn_b2_1_460800 },
4303 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4305 pbn_b2_1_460800 },
4306 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308 pbn_b2_1_460800 },
4309 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 pbn_b2_bt_2_921600 },
4312 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 pbn_b2_bt_2_921600 },
4315 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4317 pbn_b2_bt_2_921600 },
4318 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 pbn_b2_bt_4_921600 },
4321 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 pbn_b2_bt_4_921600 },
4324 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4326 pbn_b2_bt_4_921600 },
4327 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4329 pbn_b0_1_921600 },
4330 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 pbn_b0_1_921600 },
4333 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335 pbn_b0_1_921600 },
4336 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 pbn_b0_bt_2_921600 },
4339 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341 pbn_b0_bt_2_921600 },
4342 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344 pbn_b0_bt_2_921600 },
4345 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347 pbn_b0_bt_4_921600 },
4348 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4350 pbn_b0_bt_4_921600 },
4351 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353 pbn_b0_bt_4_921600 },
4354 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356 pbn_b0_bt_8_921600 },
4357 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359 pbn_b0_bt_8_921600 },
4360 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362 pbn_b0_bt_8_921600 },
4363
4364
4365
4366
4367 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4368 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4369 0, 0, pbn_computone_4 },
4370 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4371 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4372 0, 0, pbn_computone_8 },
4373 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4374 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4375 0, 0, pbn_computone_6 },
4376
4377 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379 pbn_oxsemi },
4380 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4381 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4382 pbn_b0_bt_1_921600 },
4383
4384
4385
4386
4387 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4388 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4389 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4390 pbn_b0_bt_1_921600 },
4391
4392 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4393 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4394 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4395 pbn_b0_bt_1_921600 },
4396
4397
4398
4399
4400 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402 pbn_b0_bt_8_115200 },
4403 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405 pbn_b0_bt_8_115200 },
4406
4407 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b0_bt_2_115200 },
4410 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_b0_bt_2_115200 },
4413 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b0_bt_2_115200 },
4416 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b0_bt_2_115200 },
4419 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b0_bt_2_115200 },
4422 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_b0_bt_4_460800 },
4425 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_b0_bt_4_460800 },
4428 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_b0_bt_2_460800 },
4431 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_b0_bt_2_460800 },
4434 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_b0_bt_2_460800 },
4437 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_b0_bt_1_115200 },
4440 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_b0_bt_1_460800 },
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4453 0x1204, 0x0004, 0, 0,
4454 pbn_b0_4_921600 },
4455 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4456 0x1208, 0x0004, 0, 0,
4457 pbn_b0_4_921600 },
4458
4459
4460
4461
4462
4463
4464 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4465 0x1208, 0x0004, 0, 0,
4466 pbn_b0_4_921600 },
4467
4468 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4469 0x1204, 0x0004, 0, 0,
4470 pbn_b0_4_921600 },
4471 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4472 0x1208, 0x0004, 0, 0,
4473 pbn_b0_4_921600 },
4474 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4475 0x1208, 0x0004, 0, 0,
4476 pbn_b0_4_921600 },
4477
4478
4479
4480 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_b1_1_1382400 },
4483
4484
4485
4486
4487 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b1_1_1382400 },
4490
4491
4492
4493
4494 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_b2_bt_2_115200 },
4497
4498
4499
4500
4501 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4502 0xE4BF, PCI_ANY_ID, 0, 0,
4503 pbn_intel_i960 },
4504
4505
4506
4507
4508 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b0_1_115200 },
4511
4512
4513
4514 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b0_1_115200 },
4517
4518
4519
4520
4521
4522
4523
4524
4525 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4526 0x1048, 0x1500, 0, 0,
4527 pbn_b1_1_115200 },
4528
4529 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4530 0xFF00, 0, 0, 0,
4531 pbn_sgi_ioc3 },
4532
4533
4534
4535
4536 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4537 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4538 pbn_b1_1_115200 },
4539 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_b0_5_115200 },
4542 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_b2_1_115200 },
4545
4546 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b3_2_115200 },
4549 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b3_4_115200 },
4552 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_b3_8_115200 },
4555
4556
4557
4558 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4559 PCI_ANY_ID, PCI_ANY_ID,
4560 0,
4561 0, pbn_pericom_PI7C9X7951 },
4562 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4563 PCI_ANY_ID, PCI_ANY_ID,
4564 0,
4565 0, pbn_pericom_PI7C9X7952 },
4566 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4567 PCI_ANY_ID, PCI_ANY_ID,
4568 0,
4569 0, pbn_pericom_PI7C9X7954 },
4570 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4571 PCI_ANY_ID, PCI_ANY_ID,
4572 0,
4573 0, pbn_pericom_PI7C9X7958 },
4574
4575
4576
4577 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579 pbn_pericom_PI7C9X7954 },
4580 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582 pbn_pericom_PI7C9X7954 },
4583 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585 pbn_pericom_PI7C9X7954 },
4586 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588 pbn_pericom_PI7C9X7954 },
4589 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4591 pbn_pericom_PI7C9X7954 },
4592 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594 pbn_pericom_PI7C9X7954 },
4595 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_pericom_PI7C9X7954 },
4598 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_pericom_PI7C9X7954 },
4601 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_pericom_PI7C9X7954 },
4604 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_pericom_PI7C9X7954 },
4607 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_pericom_PI7C9X7954 },
4610 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_pericom_PI7C9X7954 },
4613 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_pericom_PI7C9X7954 },
4616 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_pericom_PI7C9X7954 },
4619 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_pericom_PI7C9X7954 },
4622 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_pericom_PI7C9X7954 },
4625 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_pericom_PI7C9X7954 },
4628 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_pericom_PI7C9X7954 },
4631 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_pericom_PI7C9X7954 },
4634 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_pericom_PI7C9X7954 },
4637 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_pericom_PI7C9X7954 },
4640 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_pericom_PI7C9X7954 },
4643 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_pericom_PI7C9X7954 },
4646 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_pericom_PI7C9X7954 },
4649 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_pericom_PI7C9X7958 },
4652 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_pericom_PI7C9X7958 },
4655 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_pericom_PI7C9X7958 },
4658 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_pericom_PI7C9X7958 },
4661 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_pericom_PI7C9X7958 },
4664 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_pericom_PI7C9X7958 },
4667 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_pericom_PI7C9X7958 },
4670 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_pericom_PI7C9X7958 },
4673 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_pericom_PI7C9X7958 },
4676
4677
4678
4679 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_b0_1_115200 },
4682
4683
4684
4685 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4686 PCI_ANY_ID, PCI_ANY_ID,
4687 0, 0,
4688 pbn_b1_bt_1_115200 },
4689
4690
4691
4692
4693 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_b2_2_115200 },
4696
4697
4698
4699 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_b2_4_115200 },
4702
4703
4704
4705 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4706 PCI_ANY_ID, PCI_ANY_ID,
4707 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4708 pbn_b2_4_115200 },
4709 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4710 PCI_ANY_ID, PCI_ANY_ID,
4711 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4712 pbn_b2_4_115200 },
4713
4714
4715
4716 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4717 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4718 0, 0, pbn_b2_4_921600 },
4719 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4720 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4721 0, 0, pbn_b2_8_921600 },
4722
4723
4724
4725
4726
4727
4728
4729 {
4730 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4731 PCI_VENDOR_ID_MAINPINE, 0x0200,
4732 0, 0, pbn_b0_2_115200 },
4733 {
4734 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4735 PCI_VENDOR_ID_MAINPINE, 0x0300,
4736 0, 0, pbn_b0_4_115200 },
4737 {
4738 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4739 PCI_VENDOR_ID_MAINPINE, 0x0400,
4740 0, 0, pbn_b0_2_115200 },
4741 {
4742 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4743 PCI_VENDOR_ID_MAINPINE, 0x0500,
4744 0, 0, pbn_b0_4_115200 },
4745 {
4746 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4747 PCI_VENDOR_ID_MAINPINE, 0x0600,
4748 0, 0, pbn_b0_2_115200 },
4749 {
4750 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4751 PCI_VENDOR_ID_MAINPINE, 0x0700,
4752 0, 0, pbn_b0_4_115200 },
4753 {
4754 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4755 PCI_VENDOR_ID_MAINPINE, 0x0800,
4756 0, 0, pbn_b0_8_115200 },
4757 {
4758 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4759 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4760 0, 0, pbn_b0_2_115200 },
4761 {
4762 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4763 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4764 0, 0, pbn_b0_4_115200 },
4765 {
4766 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4767 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4768 0, 0, pbn_b0_8_115200 },
4769 {
4770 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4771 PCI_VENDOR_ID_MAINPINE, 0x2000,
4772 0, 0, pbn_b0_1_115200 },
4773 {
4774 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4775 PCI_VENDOR_ID_MAINPINE, 0x2100,
4776 0, 0, pbn_b0_1_115200 },
4777 {
4778 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4779 PCI_VENDOR_ID_MAINPINE, 0x2200,
4780 0, 0, pbn_b0_2_115200 },
4781 {
4782 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4783 PCI_VENDOR_ID_MAINPINE, 0x2300,
4784 0, 0, pbn_b0_2_115200 },
4785 {
4786 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4787 PCI_VENDOR_ID_MAINPINE, 0x2400,
4788 0, 0, pbn_b0_4_115200 },
4789 {
4790 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4791 PCI_VENDOR_ID_MAINPINE, 0x2500,
4792 0, 0, pbn_b0_4_115200 },
4793 {
4794 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4795 PCI_VENDOR_ID_MAINPINE, 0x2600,
4796 0, 0, pbn_b0_8_115200 },
4797 {
4798 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4799 PCI_VENDOR_ID_MAINPINE, 0x2700,
4800 0, 0, pbn_b0_8_115200 },
4801 {
4802 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4803 PCI_VENDOR_ID_MAINPINE, 0x3000,
4804 0, 0, pbn_b0_1_115200 },
4805 {
4806 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4807 PCI_VENDOR_ID_MAINPINE, 0x3100,
4808 0, 0, pbn_b0_1_115200 },
4809 {
4810 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4811 PCI_VENDOR_ID_MAINPINE, 0x3200,
4812 0, 0, pbn_b0_2_115200 },
4813 {
4814 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4815 PCI_VENDOR_ID_MAINPINE, 0x3300,
4816 0, 0, pbn_b0_2_115200 },
4817 {
4818 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4819 PCI_VENDOR_ID_MAINPINE, 0x3400,
4820 0, 0, pbn_b0_4_115200 },
4821 {
4822 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4823 PCI_VENDOR_ID_MAINPINE, 0x3500,
4824 0, 0, pbn_b0_4_115200 },
4825 {
4826 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4827 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4828 0, 0, pbn_b0_8_115200 },
4829 {
4830 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4831 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4832 0, 0, pbn_b0_8_115200 },
4833
4834
4835
4836
4837
4838 { PCI_VENDOR_ID_PASEMI, 0xa004,
4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 pbn_pasemi_1682M },
4841
4842
4843
4844
4845 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_b1_16_115200 },
4848 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850 pbn_b1_8_115200 },
4851 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_b1_bt_4_115200 },
4854 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856 pbn_b1_bt_2_115200 },
4857 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 pbn_b1_bt_4_115200 },
4860 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_b1_bt_2_115200 },
4863 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865 pbn_b1_16_115200 },
4866 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 pbn_b1_8_115200 },
4869 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4871 pbn_b1_bt_4_115200 },
4872 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874 pbn_b1_bt_2_115200 },
4875 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877 pbn_b1_bt_4_115200 },
4878 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 pbn_b1_bt_2_115200 },
4881 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883 pbn_ni8430_2 },
4884 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_ni8430_2 },
4887 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 pbn_ni8430_4 },
4890 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 pbn_ni8430_4 },
4893 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_ni8430_8 },
4896 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_ni8430_8 },
4899 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_ni8430_16 },
4902 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_ni8430_16 },
4905 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_ni8430_2 },
4908 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_ni8430_2 },
4911 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 pbn_ni8430_4 },
4914 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 pbn_ni8430_4 },
4917
4918
4919
4920
4921 { PCI_VENDOR_ID_ADDIDATA,
4922 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4923 PCI_ANY_ID,
4924 PCI_ANY_ID,
4925 0,
4926 0,
4927 pbn_b0_4_115200 },
4928
4929 { PCI_VENDOR_ID_ADDIDATA,
4930 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4931 PCI_ANY_ID,
4932 PCI_ANY_ID,
4933 0,
4934 0,
4935 pbn_b0_2_115200 },
4936
4937 { PCI_VENDOR_ID_ADDIDATA,
4938 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4939 PCI_ANY_ID,
4940 PCI_ANY_ID,
4941 0,
4942 0,
4943 pbn_b0_1_115200 },
4944
4945 { PCI_VENDOR_ID_AMCC,
4946 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
4947 PCI_ANY_ID,
4948 PCI_ANY_ID,
4949 0,
4950 0,
4951 pbn_b1_8_115200 },
4952
4953 { PCI_VENDOR_ID_ADDIDATA,
4954 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4955 PCI_ANY_ID,
4956 PCI_ANY_ID,
4957 0,
4958 0,
4959 pbn_b0_4_115200 },
4960
4961 { PCI_VENDOR_ID_ADDIDATA,
4962 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4963 PCI_ANY_ID,
4964 PCI_ANY_ID,
4965 0,
4966 0,
4967 pbn_b0_2_115200 },
4968
4969 { PCI_VENDOR_ID_ADDIDATA,
4970 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4971 PCI_ANY_ID,
4972 PCI_ANY_ID,
4973 0,
4974 0,
4975 pbn_b0_1_115200 },
4976
4977 { PCI_VENDOR_ID_ADDIDATA,
4978 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4979 PCI_ANY_ID,
4980 PCI_ANY_ID,
4981 0,
4982 0,
4983 pbn_b0_4_115200 },
4984
4985 { PCI_VENDOR_ID_ADDIDATA,
4986 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4987 PCI_ANY_ID,
4988 PCI_ANY_ID,
4989 0,
4990 0,
4991 pbn_b0_2_115200 },
4992
4993 { PCI_VENDOR_ID_ADDIDATA,
4994 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4995 PCI_ANY_ID,
4996 PCI_ANY_ID,
4997 0,
4998 0,
4999 pbn_b0_1_115200 },
5000
5001 { PCI_VENDOR_ID_ADDIDATA,
5002 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5003 PCI_ANY_ID,
5004 PCI_ANY_ID,
5005 0,
5006 0,
5007 pbn_b0_8_115200 },
5008
5009 { PCI_VENDOR_ID_ADDIDATA,
5010 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5011 PCI_ANY_ID,
5012 PCI_ANY_ID,
5013 0,
5014 0,
5015 pbn_ADDIDATA_PCIe_4_3906250 },
5016
5017 { PCI_VENDOR_ID_ADDIDATA,
5018 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5019 PCI_ANY_ID,
5020 PCI_ANY_ID,
5021 0,
5022 0,
5023 pbn_ADDIDATA_PCIe_2_3906250 },
5024
5025 { PCI_VENDOR_ID_ADDIDATA,
5026 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5027 PCI_ANY_ID,
5028 PCI_ANY_ID,
5029 0,
5030 0,
5031 pbn_ADDIDATA_PCIe_1_3906250 },
5032
5033 { PCI_VENDOR_ID_ADDIDATA,
5034 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5035 PCI_ANY_ID,
5036 PCI_ANY_ID,
5037 0,
5038 0,
5039 pbn_ADDIDATA_PCIe_8_3906250 },
5040
5041 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5042 PCI_VENDOR_ID_IBM, 0x0299,
5043 0, 0, pbn_b0_bt_2_115200 },
5044
5045
5046
5047
5048
5049
5050
5051 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5052 0xA000, 0x1000,
5053 0, 0, pbn_b0_1_115200 },
5054
5055
5056 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5057 0xA000, 0x1000,
5058 0, 0, pbn_b0_1_115200 },
5059
5060 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5061 0xA000, 0x1000,
5062 0, 0, pbn_b0_1_115200 },
5063
5064 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5065 0xA000, 0x1000,
5066 0, 0, pbn_b0_1_115200 },
5067
5068 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5069 0xA000, 0x1000,
5070 0, 0, pbn_b0_1_115200 },
5071
5072 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5073 0xA000, 0x3002,
5074 0, 0, pbn_NETMOS9900_2s_115200 },
5075
5076
5077
5078
5079
5080 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5081 0xA000, 0x1000,
5082 0, 0, pbn_b0_1_115200 },
5083
5084 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5085 0xA000, 0x3002,
5086 0, 0, pbn_b0_bt_2_115200 },
5087
5088 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5089 0xA000, 0x3004,
5090 0, 0, pbn_b0_bt_4_115200 },
5091
5092 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 pbn_ce4100_1_115200 },
5095
5096
5097
5098
5099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5101 pbn_omegapci },
5102
5103
5104
5105
5106 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5108 pbn_brcm_trumanage },
5109
5110
5111
5112
5113 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5114 PCI_ANY_ID, PCI_ANY_ID,
5115 0, 0, pbn_b0_bt_2_115200 },
5116
5117
5118
5119
5120
5121 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5122 PCI_ANY_ID, PCI_ANY_ID,
5123 0, 0, pbn_b0_bt_4_115200 },
5124
5125 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5126 PCI_ANY_ID, PCI_ANY_ID,
5127 0, 0, pbn_b0_bt_2_115200 },
5128
5129 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5130 PCI_ANY_ID, PCI_ANY_ID,
5131 0, 0, pbn_b0_bt_4_115200 },
5132
5133 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5134 PCI_ANY_ID, PCI_ANY_ID,
5135 0, 0, pbn_wch382_2 },
5136
5137 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5138 PCI_ANY_ID, PCI_ANY_ID,
5139 0, 0, pbn_wch384_4 },
5140
5141
5142 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5143 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5144 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5145
5146
5147 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5148 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5149
5150
5151 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5152
5153
5154
5155
5156
5157 { PCI_ANY_ID, PCI_ANY_ID,
5158 PCI_ANY_ID, PCI_ANY_ID,
5159 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5160 0xffff00, pbn_default },
5161 { PCI_ANY_ID, PCI_ANY_ID,
5162 PCI_ANY_ID, PCI_ANY_ID,
5163 PCI_CLASS_COMMUNICATION_MODEM << 8,
5164 0xffff00, pbn_default },
5165 { PCI_ANY_ID, PCI_ANY_ID,
5166 PCI_ANY_ID, PCI_ANY_ID,
5167 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5168 0xffff00, pbn_default },
5169 { 0, }
5170};
5171
5172static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5173 pci_channel_state_t state)
5174{
5175 struct serial_private *priv = pci_get_drvdata(dev);
5176
5177 if (state == pci_channel_io_perm_failure)
5178 return PCI_ERS_RESULT_DISCONNECT;
5179
5180 if (priv)
5181 pciserial_detach_ports(priv);
5182
5183 pci_disable_device(dev);
5184
5185 return PCI_ERS_RESULT_NEED_RESET;
5186}
5187
5188static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5189{
5190 int rc;
5191
5192 rc = pci_enable_device(dev);
5193
5194 if (rc)
5195 return PCI_ERS_RESULT_DISCONNECT;
5196
5197 pci_restore_state(dev);
5198 pci_save_state(dev);
5199
5200 return PCI_ERS_RESULT_RECOVERED;
5201}
5202
5203static void serial8250_io_resume(struct pci_dev *dev)
5204{
5205 struct serial_private *priv = pci_get_drvdata(dev);
5206 struct serial_private *new;
5207
5208 if (!priv)
5209 return;
5210
5211 new = pciserial_init_ports(dev, priv->board);
5212 if (!IS_ERR(new)) {
5213 pci_set_drvdata(dev, new);
5214 kfree(priv);
5215 }
5216}
5217
5218static const struct pci_error_handlers serial8250_err_handler = {
5219 .error_detected = serial8250_io_error_detected,
5220 .slot_reset = serial8250_io_slot_reset,
5221 .resume = serial8250_io_resume,
5222};
5223
5224static struct pci_driver serial_pci_driver = {
5225 .name = "serial",
5226 .probe = pciserial_init_one,
5227 .remove = pciserial_remove_one,
5228 .driver = {
5229 .pm = &pciserial_pm_ops,
5230 },
5231 .id_table = serial_pci_tbl,
5232 .err_handler = &serial8250_err_handler,
5233};
5234
5235module_pci_driver(serial_pci_driver);
5236
5237MODULE_LICENSE("GPL");
5238MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5239MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5240