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28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/netdevice.h>
56#include <linux/vmalloc.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/ioctl.h>
60
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/dma.h>
64#include <linux/bitops.h>
65#include <asm/types.h>
66#include <linux/termios.h>
67#include <linux/workqueue.h>
68#include <linux/hdlc.h>
69#include <linux/synclink.h>
70
71#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72#define SYNCLINK_GENERIC_HDLC 1
73#else
74#define SYNCLINK_GENERIC_HDLC 0
75#endif
76
77#define GET_USER(error,value,addr) error = get_user(value,addr)
78#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79#define PUT_USER(error,value,addr) error = put_user(value,addr)
80#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82#include <linux/uaccess.h>
83
84static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC,
86 0,
87 HDLC_FLAG_UNDERRUN_ABORT15,
88 HDLC_ENCODING_NRZI_SPACE,
89 0,
90 0xff,
91 HDLC_CRC_16_CCITT,
92 HDLC_PREAMBLE_LENGTH_8BITS,
93 HDLC_PREAMBLE_PATTERN_NONE,
94 9600,
95 8,
96 1,
97 ASYNC_PARITY_NONE
98};
99
100
101#define SCABUFSIZE 1024
102#define SCA_MEM_SIZE 0x40000
103#define SCA_BASE_SIZE 512
104#define SCA_REG_SIZE 16
105#define SCA_MAX_PORTS 4
106#define SCAMAXDESC 128
107
108#define BUFFERLISTSIZE 4096
109
110
111typedef struct _SCADESC
112{
113 u16 next;
114 u16 buf_ptr;
115 u8 buf_base;
116 u8 pad1;
117 u16 length;
118 u8 status;
119 u8 pad2;
120} SCADESC, *PSCADESC;
121
122typedef struct _SCADESC_EX
123{
124
125 char *virt_addr;
126 u16 phys_entry;
127} SCADESC_EX, *PSCADESC_EX;
128
129
130
131#define BH_RECEIVE 1
132#define BH_TRANSMIT 2
133#define BH_STATUS 4
134
135#define IO_PIN_SHUTDOWN_LIMIT 100
136
137struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146};
147
148
149
150
151typedef struct _synclinkmp_info {
152 void *if_ptr;
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait;
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char;
163 u16 read_status_mask1;
164 u16 read_status_mask2;
165 unsigned char ignore_status_mask1;
166 unsigned char ignore_status_mask2;
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer;
175 struct _synclinkmp_info *next_device;
176 struct timer_list status_timer;
177
178 spinlock_t lock;
179 struct work_struct task;
180
181 u32 max_frame_size;
182
183 u32 pending_bh;
184
185 bool bh_running;
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount;
190 int cts_chkcount;
191 int dsr_chkcount;
192 int ri_chkcount;
193
194 char *buffer_list;
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count;
198 SCADESC *rx_buf_list;
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC];
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count;
203 SCADESC *tx_buf_list;
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC];
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25];
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type;
232
233 unsigned int irq_level;
234 unsigned long irq_flags;
235 bool irq_requested;
236
237 MGSL_PARAMS params;
238
239 unsigned char serial_signals;
240
241 bool irq_occurred;
242 unsigned int init_error;
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base;
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base;
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base;
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base;
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270
271 int netcount;
272 spinlock_t netlock;
273
274#if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276#endif
277
278} SLMP_INFO;
279
280#define MGSL_MAGIC 0x5401
281
282
283
284
285#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8)
286#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8)
287#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8)
288#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8)
289
290
291#define LPR 0x00
292#define PABR0 0x02
293#define PABR1 0x03
294#define WCRL 0x04
295#define WCRM 0x05
296#define WCRH 0x06
297#define DPCR 0x08
298#define DMER 0x09
299#define ISR0 0x10
300#define ISR1 0x11
301#define ISR2 0x12
302#define IER0 0x14
303#define IER1 0x15
304#define IER2 0x16
305#define ITCR 0x18
306#define INTVR 0x1a
307#define IMVR 0x1c
308
309
310#define TRB 0x20
311#define TRBL 0x20
312#define TRBH 0x21
313#define SR0 0x22
314#define SR1 0x23
315#define SR2 0x24
316#define SR3 0x25
317#define FST 0x26
318#define IE0 0x28
319#define IE1 0x29
320#define IE2 0x2a
321#define FIE 0x2b
322#define CMD 0x2c
323#define MD0 0x2e
324#define MD1 0x2f
325#define MD2 0x30
326#define CTL 0x31
327#define SA0 0x32
328#define SA1 0x33
329#define IDL 0x34
330#define TMC 0x35
331#define RXS 0x36
332#define TXS 0x37
333#define TRC0 0x38
334#define TRC1 0x39
335#define RRC 0x3a
336#define CST0 0x3c
337#define CST1 0x3d
338
339
340#define TCNT 0x60
341#define TCNTL 0x60
342#define TCNTH 0x61
343#define TCONR 0x62
344#define TCONRL 0x62
345#define TCONRH 0x63
346#define TMCS 0x64
347#define TEPR 0x65
348
349
350#define DARL 0x80
351#define DARH 0x81
352#define DARB 0x82
353#define BAR 0x80
354#define BARL 0x80
355#define BARH 0x81
356#define BARB 0x82
357#define SAR 0x84
358#define SARL 0x84
359#define SARH 0x85
360#define SARB 0x86
361#define CPB 0x86
362#define CDA 0x88
363#define CDAL 0x88
364#define CDAH 0x89
365#define EDA 0x8a
366#define EDAL 0x8a
367#define EDAH 0x8b
368#define BFL 0x8c
369#define BFLL 0x8c
370#define BFLH 0x8d
371#define BCR 0x8e
372#define BCRL 0x8e
373#define BCRH 0x8f
374#define DSR 0x90
375#define DMR 0x91
376#define FCT 0x93
377#define DIR 0x94
378#define DCMD 0x95
379
380
381#define TIMER0 0x00
382#define TIMER1 0x08
383#define TIMER2 0x10
384#define TIMER3 0x18
385#define RXDMA 0x00
386#define TXDMA 0x20
387
388
389#define NOOP 0x00
390#define TXRESET 0x01
391#define TXENABLE 0x02
392#define TXDISABLE 0x03
393#define TXCRCINIT 0x04
394#define TXCRCEXCL 0x05
395#define TXEOM 0x06
396#define TXABORT 0x07
397#define MPON 0x08
398#define TXBUFCLR 0x09
399#define RXRESET 0x11
400#define RXENABLE 0x12
401#define RXDISABLE 0x13
402#define RXCRCINIT 0x14
403#define RXREJECT 0x15
404#define SEARCHMP 0x16
405#define RXCRCEXCL 0x17
406#define RXCRCCALC 0x18
407#define CHRESET 0x21
408#define HUNT 0x31
409
410
411#define SWABORT 0x01
412#define FEICLEAR 0x02
413
414
415#define TXINTE BIT7
416#define RXINTE BIT6
417#define TXRDYE BIT1
418#define RXRDYE BIT0
419
420
421#define UDRN BIT7
422#define IDLE BIT6
423#define SYNCD BIT4
424#define FLGD BIT4
425#define CCTS BIT3
426#define CDCD BIT2
427#define BRKD BIT1
428#define ABTD BIT1
429#define GAPD BIT1
430#define BRKE BIT0
431#define IDLD BIT0
432
433
434#define EOM BIT7
435#define PMP BIT6
436#define SHRT BIT6
437#define PE BIT5
438#define ABT BIT5
439#define FRME BIT4
440#define RBIT BIT4
441#define OVRN BIT3
442#define CRCE BIT2
443
444
445
446
447
448static SLMP_INFO *synclinkmp_device_list = NULL;
449static int synclinkmp_adapter_count = -1;
450static int synclinkmp_device_count = 0;
451
452
453
454
455
456
457static bool break_on_load = 0;
458
459
460
461
462
463static int ttymajor = 0;
464
465
466
467
468static int debug_level = 0;
469static int maxframe[MAX_DEVICES] = {0,};
470
471module_param(break_on_load, bool, 0);
472module_param(ttymajor, int, 0);
473module_param(debug_level, int, 0);
474module_param_array(maxframe, int, NULL, 0);
475
476static char *driver_name = "SyncLink MultiPort driver";
477static char *driver_version = "$Revision: 4.38 $";
478
479static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480static void synclinkmp_remove_one(struct pci_dev *dev);
481
482static const struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, },
485};
486MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488MODULE_LICENSE("GPL");
489
490static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495};
496
497
498static struct tty_driver *serial_driver;
499
500
501#define WAKEUP_CHARS 256
502
503
504
505
506static int open(struct tty_struct *tty, struct file * filp);
507static void close(struct tty_struct *tty, struct file * filp);
508static void hangup(struct tty_struct *tty);
509static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512static int put_char(struct tty_struct *tty, unsigned char ch);
513static void send_xchar(struct tty_struct *tty, char ch);
514static void wait_until_sent(struct tty_struct *tty, int timeout);
515static int write_room(struct tty_struct *tty);
516static void flush_chars(struct tty_struct *tty);
517static void flush_buffer(struct tty_struct *tty);
518static void tx_hold(struct tty_struct *tty);
519static void tx_release(struct tty_struct *tty);
520
521static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522static int chars_in_buffer(struct tty_struct *tty);
523static void throttle(struct tty_struct * tty);
524static void unthrottle(struct tty_struct * tty);
525static int set_break(struct tty_struct *tty, int break_state);
526
527#if SYNCLINK_GENERIC_HDLC
528#define dev_to_port(D) (dev_to_hdlc(D)->priv)
529static void hdlcdev_tx_done(SLMP_INFO *info);
530static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531static int hdlcdev_init(SLMP_INFO *info);
532static void hdlcdev_exit(SLMP_INFO *info);
533#endif
534
535
536
537static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541static int set_txidle(SLMP_INFO *info, int idle_mode);
542static int tx_enable(SLMP_INFO *info, int enable);
543static int tx_abort(SLMP_INFO *info);
544static int rx_enable(SLMP_INFO *info, int enable);
545static int modem_input_wait(SLMP_INFO *info,int arg);
546static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547static int tiocmget(struct tty_struct *tty);
548static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550static int set_break(struct tty_struct *tty, int break_state);
551
552static int add_device(SLMP_INFO *info);
553static int device_init(int adapter_num, struct pci_dev *pdev);
554static int claim_resources(SLMP_INFO *info);
555static void release_resources(SLMP_INFO *info);
556
557static int startup(SLMP_INFO *info);
558static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559static int carrier_raised(struct tty_port *port);
560static void shutdown(SLMP_INFO *info);
561static void program_hw(SLMP_INFO *info);
562static void change_params(SLMP_INFO *info);
563
564static bool init_adapter(SLMP_INFO *info);
565static bool register_test(SLMP_INFO *info);
566static bool irq_test(SLMP_INFO *info);
567static bool loopback_test(SLMP_INFO *info);
568static int adapter_test(SLMP_INFO *info);
569static bool memory_test(SLMP_INFO *info);
570
571static void reset_adapter(SLMP_INFO *info);
572static void reset_port(SLMP_INFO *info);
573static void async_mode(SLMP_INFO *info);
574static void hdlc_mode(SLMP_INFO *info);
575
576static void rx_stop(SLMP_INFO *info);
577static void rx_start(SLMP_INFO *info);
578static void rx_reset_buffers(SLMP_INFO *info);
579static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580static bool rx_get_frame(SLMP_INFO *info);
581
582static void tx_start(SLMP_INFO *info);
583static void tx_stop(SLMP_INFO *info);
584static void tx_load_fifo(SLMP_INFO *info);
585static void tx_set_idle(SLMP_INFO *info);
586static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588static void get_signals(SLMP_INFO *info);
589static void set_signals(SLMP_INFO *info);
590static void enable_loopback(SLMP_INFO *info, int enable);
591static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593static int bh_action(SLMP_INFO *info);
594static void bh_handler(struct work_struct *work);
595static void bh_receive(SLMP_INFO *info);
596static void bh_transmit(SLMP_INFO *info);
597static void bh_status(SLMP_INFO *info);
598static void isr_timer(SLMP_INFO *info);
599static void isr_rxint(SLMP_INFO *info);
600static void isr_rxrdy(SLMP_INFO *info);
601static void isr_txint(SLMP_INFO *info);
602static void isr_txrdy(SLMP_INFO *info);
603static void isr_rxdmaok(SLMP_INFO *info);
604static void isr_rxdmaerror(SLMP_INFO *info);
605static void isr_txdmaok(SLMP_INFO *info);
606static void isr_txdmaerror(SLMP_INFO *info);
607static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609static int alloc_dma_bufs(SLMP_INFO *info);
610static void free_dma_bufs(SLMP_INFO *info);
611static int alloc_buf_list(SLMP_INFO *info);
612static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613static int alloc_tmp_rx_buf(SLMP_INFO *info);
614static void free_tmp_rx_buf(SLMP_INFO *info);
615
616static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618static void tx_timeout(struct timer_list *t);
619static void status_timeout(struct timer_list *t);
620
621static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625static unsigned char read_status_reg(SLMP_INFO * info);
626static void write_control_reg(SLMP_INFO * info);
627
628
629static unsigned char rx_active_fifo_level = 16;
630static unsigned char tx_active_fifo_level = 16;
631static unsigned char tx_negate_fifo_level = 32;
632
633static u32 misc_ctrl_value = 0x007e4040;
634static u32 lcr1_brdr_value = 0x00800028;
635
636static u32 read_ahead_count = 8;
637
638
639
640
641
642
643
644
645
646
647
648
649static unsigned char dma_priority = 0x04;
650
651
652
653static u32 sca_pci_load_interval = 64;
654
655
656
657
658
659
660
661static void* synclinkmp_get_text_ptr(void);
662static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666{
667#ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681#else
682 if (!info)
683 return 1;
684#endif
685 return 0;
686}
687
688
689
690
691
692
693
694
695
696
697static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699{
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709}
710
711
712
713static int install(struct tty_driver *driver, struct tty_struct *tty)
714{
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739}
740
741
742
743static int open(struct tty_struct *tty, struct file *filp)
744{
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
756
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
759 retval = -EBUSY;
760 spin_unlock_irqrestore(&info->netlock, flags);
761 goto cleanup;
762 }
763 info->port.count++;
764 spin_unlock_irqrestore(&info->netlock, flags);
765
766 if (info->port.count == 1) {
767
768 retval = startup(info);
769 if (retval < 0)
770 goto cleanup;
771 }
772
773 retval = block_til_ready(tty, filp, info);
774 if (retval) {
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
778 goto cleanup;
779 }
780
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
784 retval = 0;
785
786cleanup:
787 if (retval) {
788 if (tty->count == 1)
789 info->port.tty = NULL;
790 if(info->port.count)
791 info->port.count--;
792 }
793
794 return retval;
795}
796
797
798
799
800static void close(struct tty_struct *tty, struct file *filp)
801{
802 SLMP_INFO * info = tty->driver_data;
803
804 if (sanity_check(info, tty->name, "close"))
805 return;
806
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
809 __FILE__,__LINE__, info->device_name, info->port.count);
810
811 if (tty_port_close_start(&info->port, tty, filp) == 0)
812 goto cleanup;
813
814 mutex_lock(&info->port.mutex);
815 if (tty_port_initialized(&info->port))
816 wait_until_sent(tty, info->timeout);
817
818 flush_buffer(tty);
819 tty_ldisc_flush(tty);
820 shutdown(info);
821 mutex_unlock(&info->port.mutex);
822
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
825cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
829}
830
831
832
833
834static void hangup(struct tty_struct *tty)
835{
836 SLMP_INFO *info = tty->driver_data;
837 unsigned long flags;
838
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
842
843 if (sanity_check(info, tty->name, "hangup"))
844 return;
845
846 mutex_lock(&info->port.mutex);
847 flush_buffer(tty);
848 shutdown(info);
849
850 spin_lock_irqsave(&info->port.lock, flags);
851 info->port.count = 0;
852 info->port.tty = NULL;
853 spin_unlock_irqrestore(&info->port.lock, flags);
854 tty_port_set_active(&info->port, 1);
855 mutex_unlock(&info->port.mutex);
856
857 wake_up_interruptible(&info->port.open_wait);
858}
859
860
861
862static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
863{
864 SLMP_INFO *info = tty->driver_data;
865 unsigned long flags;
866
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
869 tty->driver->name );
870
871 change_params(info);
872
873
874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
876 spin_lock_irqsave(&info->lock,flags);
877 set_signals(info);
878 spin_unlock_irqrestore(&info->lock,flags);
879 }
880
881
882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
883 info->serial_signals |= SerialSignal_DTR;
884 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
885 info->serial_signals |= SerialSignal_RTS;
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891
892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896}
897
898
899
900
901
902
903
904
905
906
907
908static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910{
911 int c, ret = 0;
912 SLMP_INFO *info = tty->driver_data;
913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
922 if (!info->tx_buf)
923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933
934
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984}
985
986
987
988static int put_char(struct tty_struct *tty, unsigned char ch)
989{
990 SLMP_INFO *info = tty->driver_data;
991 unsigned long flags;
992 int ret = 0;
993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
1000 return 0;
1001
1002 if (!info->tx_buf)
1003 return 0;
1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
1015 ret = 1;
1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
1020 return ret;
1021}
1022
1023
1024
1025static void send_xchar(struct tty_struct *tty, char ch)
1026{
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045}
1046
1047
1048
1049static void wait_until_sent(struct tty_struct *tty, int timeout)
1050{
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
1064 if (!tty_port_initialized(&info->port))
1065 goto exit;
1066
1067 orig_jiffies = jiffies;
1068
1069
1070
1071
1072
1073
1074
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1077 if (!char_time)
1078 char_time++;
1079 } else
1080 char_time = 1;
1081
1082 if (timeout)
1083 char_time = min_t(unsigned long, char_time, timeout);
1084
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1089 break;
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091 break;
1092 }
1093 } else {
1094
1095
1096
1097
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107exit:
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1111}
1112
1113
1114
1115static int write_room(struct tty_struct *tty)
1116{
1117 SLMP_INFO *info = tty->driver_data;
1118 int ret;
1119
1120 if (sanity_check(info, tty->name, "write_room"))
1121 return 0;
1122
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125 } else {
1126 ret = info->max_frame_size - info->tx_count - 1;
1127 if (ret < 0)
1128 ret = 0;
1129 }
1130
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1134
1135 return ret;
1136}
1137
1138
1139
1140static void flush_chars(struct tty_struct *tty)
1141{
1142 SLMP_INFO *info = tty->driver_data;
1143 unsigned long flags;
1144
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149 if (sanity_check(info, tty->name, "flush_chars"))
1150 return;
1151
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153 !info->tx_buf)
1154 return;
1155
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1159
1160 spin_lock_irqsave(&info->lock,flags);
1161
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164 info->tx_count ) {
1165
1166
1167
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1170 }
1171 tx_start(info);
1172 }
1173
1174 spin_unlock_irqrestore(&info->lock,flags);
1175}
1176
1177
1178
1179static void flush_buffer(struct tty_struct *tty)
1180{
1181 SLMP_INFO *info = tty->driver_data;
1182 unsigned long flags;
1183
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1187
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1189 return;
1190
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1195
1196 tty_wakeup(tty);
1197}
1198
1199
1200
1201static void tx_hold(struct tty_struct *tty)
1202{
1203 SLMP_INFO *info = tty->driver_data;
1204 unsigned long flags;
1205
1206 if (sanity_check(info, tty->name, "tx_hold"))
1207 return;
1208
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1212
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1215 tx_stop(info);
1216 spin_unlock_irqrestore(&info->lock,flags);
1217}
1218
1219
1220
1221static void tx_release(struct tty_struct *tty)
1222{
1223 SLMP_INFO *info = tty->driver_data;
1224 unsigned long flags;
1225
1226 if (sanity_check(info, tty->name, "tx_release"))
1227 return;
1228
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1232
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1235 tx_start(info);
1236 spin_unlock_irqrestore(&info->lock,flags);
1237}
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249static int ioctl(struct tty_struct *tty,
1250 unsigned int cmd, unsigned long arg)
1251{
1252 SLMP_INFO *info = tty->driver_data;
1253 void __user *argp = (void __user *)arg;
1254
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1258
1259 if (sanity_check(info, tty->name, "ioctl"))
1260 return -ENODEV;
1261
1262 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1263 (cmd != TIOCMIWAIT)) {
1264 if (tty_io_error(tty))
1265 return -EIO;
1266 }
1267
1268 switch (cmd) {
1269 case MGSL_IOCGPARAMS:
1270 return get_params(info, argp);
1271 case MGSL_IOCSPARAMS:
1272 return set_params(info, argp);
1273 case MGSL_IOCGTXIDLE:
1274 return get_txidle(info, argp);
1275 case MGSL_IOCSTXIDLE:
1276 return set_txidle(info, (int)arg);
1277 case MGSL_IOCTXENABLE:
1278 return tx_enable(info, (int)arg);
1279 case MGSL_IOCRXENABLE:
1280 return rx_enable(info, (int)arg);
1281 case MGSL_IOCTXABORT:
1282 return tx_abort(info);
1283 case MGSL_IOCGSTATS:
1284 return get_stats(info, argp);
1285 case MGSL_IOCWAITEVENT:
1286 return wait_mgsl_event(info, argp);
1287 case MGSL_IOCLOOPTXDONE:
1288 return 0;
1289
1290
1291
1292 case TIOCMIWAIT:
1293 return modem_input_wait(info,(int)arg);
1294
1295
1296
1297
1298
1299
1300
1301 default:
1302 return -ENOIOCTLCMD;
1303 }
1304 return 0;
1305}
1306
1307static int get_icount(struct tty_struct *tty,
1308 struct serial_icounter_struct *icount)
1309{
1310 SLMP_INFO *info = tty->driver_data;
1311 struct mgsl_icount cnow;
1312 unsigned long flags;
1313
1314 spin_lock_irqsave(&info->lock,flags);
1315 cnow = info->icount;
1316 spin_unlock_irqrestore(&info->lock,flags);
1317
1318 icount->cts = cnow.cts;
1319 icount->dsr = cnow.dsr;
1320 icount->rng = cnow.rng;
1321 icount->dcd = cnow.dcd;
1322 icount->rx = cnow.rx;
1323 icount->tx = cnow.tx;
1324 icount->frame = cnow.frame;
1325 icount->overrun = cnow.overrun;
1326 icount->parity = cnow.parity;
1327 icount->brk = cnow.brk;
1328 icount->buf_overrun = cnow.buf_overrun;
1329
1330 return 0;
1331}
1332
1333
1334
1335
1336
1337static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1338{
1339 char stat_buf[30];
1340 unsigned long flags;
1341
1342 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1343 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->device_name,
1345 info->phys_sca_base,
1346 info->phys_memory_base,
1347 info->phys_statctrl_base,
1348 info->phys_lcr_base,
1349 info->irq_level,
1350 info->max_frame_size );
1351
1352
1353 spin_lock_irqsave(&info->lock,flags);
1354 get_signals(info);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356
1357 stat_buf[0] = 0;
1358 stat_buf[1] = 0;
1359 if (info->serial_signals & SerialSignal_RTS)
1360 strcat(stat_buf, "|RTS");
1361 if (info->serial_signals & SerialSignal_CTS)
1362 strcat(stat_buf, "|CTS");
1363 if (info->serial_signals & SerialSignal_DTR)
1364 strcat(stat_buf, "|DTR");
1365 if (info->serial_signals & SerialSignal_DSR)
1366 strcat(stat_buf, "|DSR");
1367 if (info->serial_signals & SerialSignal_DCD)
1368 strcat(stat_buf, "|CD");
1369 if (info->serial_signals & SerialSignal_RI)
1370 strcat(stat_buf, "|RI");
1371
1372 if (info->params.mode == MGSL_MODE_HDLC) {
1373 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1374 info->icount.txok, info->icount.rxok);
1375 if (info->icount.txunder)
1376 seq_printf(m, " txunder:%d", info->icount.txunder);
1377 if (info->icount.txabort)
1378 seq_printf(m, " txabort:%d", info->icount.txabort);
1379 if (info->icount.rxshort)
1380 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1381 if (info->icount.rxlong)
1382 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1383 if (info->icount.rxover)
1384 seq_printf(m, " rxover:%d", info->icount.rxover);
1385 if (info->icount.rxcrc)
1386 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1387 } else {
1388 seq_printf(m, "\tASYNC tx:%d rx:%d",
1389 info->icount.tx, info->icount.rx);
1390 if (info->icount.frame)
1391 seq_printf(m, " fe:%d", info->icount.frame);
1392 if (info->icount.parity)
1393 seq_printf(m, " pe:%d", info->icount.parity);
1394 if (info->icount.brk)
1395 seq_printf(m, " brk:%d", info->icount.brk);
1396 if (info->icount.overrun)
1397 seq_printf(m, " oe:%d", info->icount.overrun);
1398 }
1399
1400
1401 seq_printf(m, " %s\n", stat_buf+1);
1402
1403 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1404 info->tx_active,info->bh_requested,info->bh_running,
1405 info->pending_bh);
1406}
1407
1408
1409
1410static int synclinkmp_proc_show(struct seq_file *m, void *v)
1411{
1412 SLMP_INFO *info;
1413
1414 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1415
1416 info = synclinkmp_device_list;
1417 while( info ) {
1418 line_info(m, info);
1419 info = info->next_device;
1420 }
1421 return 0;
1422}
1423
1424static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1425{
1426 return single_open(file, synclinkmp_proc_show, NULL);
1427}
1428
1429static const struct file_operations synclinkmp_proc_fops = {
1430 .owner = THIS_MODULE,
1431 .open = synclinkmp_proc_open,
1432 .read = seq_read,
1433 .llseek = seq_lseek,
1434 .release = single_release,
1435};
1436
1437
1438
1439static int chars_in_buffer(struct tty_struct *tty)
1440{
1441 SLMP_INFO *info = tty->driver_data;
1442
1443 if (sanity_check(info, tty->name, "chars_in_buffer"))
1444 return 0;
1445
1446 if (debug_level >= DEBUG_LEVEL_INFO)
1447 printk("%s(%d):%s chars_in_buffer()=%d\n",
1448 __FILE__, __LINE__, info->device_name, info->tx_count);
1449
1450 return info->tx_count;
1451}
1452
1453
1454
1455static void throttle(struct tty_struct * tty)
1456{
1457 SLMP_INFO *info = tty->driver_data;
1458 unsigned long flags;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s throttle() entry\n",
1462 __FILE__,__LINE__, info->device_name );
1463
1464 if (sanity_check(info, tty->name, "throttle"))
1465 return;
1466
1467 if (I_IXOFF(tty))
1468 send_xchar(tty, STOP_CHAR(tty));
1469
1470 if (C_CRTSCTS(tty)) {
1471 spin_lock_irqsave(&info->lock,flags);
1472 info->serial_signals &= ~SerialSignal_RTS;
1473 set_signals(info);
1474 spin_unlock_irqrestore(&info->lock,flags);
1475 }
1476}
1477
1478
1479
1480static void unthrottle(struct tty_struct * tty)
1481{
1482 SLMP_INFO *info = tty->driver_data;
1483 unsigned long flags;
1484
1485 if (debug_level >= DEBUG_LEVEL_INFO)
1486 printk("%s(%d):%s unthrottle() entry\n",
1487 __FILE__,__LINE__, info->device_name );
1488
1489 if (sanity_check(info, tty->name, "unthrottle"))
1490 return;
1491
1492 if (I_IXOFF(tty)) {
1493 if (info->x_char)
1494 info->x_char = 0;
1495 else
1496 send_xchar(tty, START_CHAR(tty));
1497 }
1498
1499 if (C_CRTSCTS(tty)) {
1500 spin_lock_irqsave(&info->lock,flags);
1501 info->serial_signals |= SerialSignal_RTS;
1502 set_signals(info);
1503 spin_unlock_irqrestore(&info->lock,flags);
1504 }
1505}
1506
1507
1508
1509
1510static int set_break(struct tty_struct *tty, int break_state)
1511{
1512 unsigned char RegValue;
1513 SLMP_INFO * info = tty->driver_data;
1514 unsigned long flags;
1515
1516 if (debug_level >= DEBUG_LEVEL_INFO)
1517 printk("%s(%d):%s set_break(%d)\n",
1518 __FILE__,__LINE__, info->device_name, break_state);
1519
1520 if (sanity_check(info, tty->name, "set_break"))
1521 return -EINVAL;
1522
1523 spin_lock_irqsave(&info->lock,flags);
1524 RegValue = read_reg(info, CTL);
1525 if (break_state == -1)
1526 RegValue |= BIT3;
1527 else
1528 RegValue &= ~BIT3;
1529 write_reg(info, CTL, RegValue);
1530 spin_unlock_irqrestore(&info->lock,flags);
1531 return 0;
1532}
1533
1534#if SYNCLINK_GENERIC_HDLC
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1547 unsigned short parity)
1548{
1549 SLMP_INFO *info = dev_to_port(dev);
1550 unsigned char new_encoding;
1551 unsigned short new_crctype;
1552
1553
1554 if (info->port.count)
1555 return -EBUSY;
1556
1557 switch (encoding)
1558 {
1559 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1560 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1561 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1562 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1563 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1564 default: return -EINVAL;
1565 }
1566
1567 switch (parity)
1568 {
1569 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1570 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1571 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1572 default: return -EINVAL;
1573 }
1574
1575 info->params.encoding = new_encoding;
1576 info->params.crc_type = new_crctype;
1577
1578
1579 if (info->netcount)
1580 program_hw(info);
1581
1582 return 0;
1583}
1584
1585
1586
1587
1588
1589
1590
1591static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1592 struct net_device *dev)
1593{
1594 SLMP_INFO *info = dev_to_port(dev);
1595 unsigned long flags;
1596
1597 if (debug_level >= DEBUG_LEVEL_INFO)
1598 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1599
1600
1601 netif_stop_queue(dev);
1602
1603
1604 info->tx_count = skb->len;
1605 tx_load_dma_buffer(info, skb->data, skb->len);
1606
1607
1608 dev->stats.tx_packets++;
1609 dev->stats.tx_bytes += skb->len;
1610
1611
1612 dev_kfree_skb(skb);
1613
1614
1615 netif_trans_update(dev);
1616
1617
1618 spin_lock_irqsave(&info->lock,flags);
1619 if (!info->tx_active)
1620 tx_start(info);
1621 spin_unlock_irqrestore(&info->lock,flags);
1622
1623 return NETDEV_TX_OK;
1624}
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634static int hdlcdev_open(struct net_device *dev)
1635{
1636 SLMP_INFO *info = dev_to_port(dev);
1637 int rc;
1638 unsigned long flags;
1639
1640 if (debug_level >= DEBUG_LEVEL_INFO)
1641 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1642
1643
1644 rc = hdlc_open(dev);
1645 if (rc)
1646 return rc;
1647
1648
1649 spin_lock_irqsave(&info->netlock, flags);
1650 if (info->port.count != 0 || info->netcount != 0) {
1651 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1652 spin_unlock_irqrestore(&info->netlock, flags);
1653 return -EBUSY;
1654 }
1655 info->netcount=1;
1656 spin_unlock_irqrestore(&info->netlock, flags);
1657
1658
1659 if ((rc = startup(info)) != 0) {
1660 spin_lock_irqsave(&info->netlock, flags);
1661 info->netcount=0;
1662 spin_unlock_irqrestore(&info->netlock, flags);
1663 return rc;
1664 }
1665
1666
1667 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1668 program_hw(info);
1669
1670
1671 netif_trans_update(dev);
1672 netif_start_queue(dev);
1673
1674
1675 spin_lock_irqsave(&info->lock, flags);
1676 get_signals(info);
1677 spin_unlock_irqrestore(&info->lock, flags);
1678 if (info->serial_signals & SerialSignal_DCD)
1679 netif_carrier_on(dev);
1680 else
1681 netif_carrier_off(dev);
1682 return 0;
1683}
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693static int hdlcdev_close(struct net_device *dev)
1694{
1695 SLMP_INFO *info = dev_to_port(dev);
1696 unsigned long flags;
1697
1698 if (debug_level >= DEBUG_LEVEL_INFO)
1699 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1700
1701 netif_stop_queue(dev);
1702
1703
1704 shutdown(info);
1705
1706 hdlc_close(dev);
1707
1708 spin_lock_irqsave(&info->netlock, flags);
1709 info->netcount=0;
1710 spin_unlock_irqrestore(&info->netlock, flags);
1711
1712 return 0;
1713}
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1725{
1726 const size_t size = sizeof(sync_serial_settings);
1727 sync_serial_settings new_line;
1728 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1729 SLMP_INFO *info = dev_to_port(dev);
1730 unsigned int flags;
1731
1732 if (debug_level >= DEBUG_LEVEL_INFO)
1733 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1734
1735
1736 if (info->port.count)
1737 return -EBUSY;
1738
1739 if (cmd != SIOCWANDEV)
1740 return hdlc_ioctl(dev, ifr, cmd);
1741
1742 switch(ifr->ifr_settings.type) {
1743 case IF_GET_IFACE:
1744
1745 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1746 if (ifr->ifr_settings.size < size) {
1747 ifr->ifr_settings.size = size;
1748 return -ENOBUFS;
1749 }
1750
1751 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1752 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1753 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1754 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1755
1756 memset(&new_line, 0, sizeof(new_line));
1757 switch (flags){
1758 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1759 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1760 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1761 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1762 default: new_line.clock_type = CLOCK_DEFAULT;
1763 }
1764
1765 new_line.clock_rate = info->params.clock_speed;
1766 new_line.loopback = info->params.loopback ? 1:0;
1767
1768 if (copy_to_user(line, &new_line, size))
1769 return -EFAULT;
1770 return 0;
1771
1772 case IF_IFACE_SYNC_SERIAL:
1773
1774 if(!capable(CAP_NET_ADMIN))
1775 return -EPERM;
1776 if (copy_from_user(&new_line, line, size))
1777 return -EFAULT;
1778
1779 switch (new_line.clock_type)
1780 {
1781 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1782 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1783 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1784 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1785 case CLOCK_DEFAULT: flags = info->params.flags &
1786 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1787 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1788 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1789 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1790 default: return -EINVAL;
1791 }
1792
1793 if (new_line.loopback != 0 && new_line.loopback != 1)
1794 return -EINVAL;
1795
1796 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1797 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1798 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1799 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1800 info->params.flags |= flags;
1801
1802 info->params.loopback = new_line.loopback;
1803
1804 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1805 info->params.clock_speed = new_line.clock_rate;
1806 else
1807 info->params.clock_speed = 0;
1808
1809
1810 if (info->netcount)
1811 program_hw(info);
1812 return 0;
1813
1814 default:
1815 return hdlc_ioctl(dev, ifr, cmd);
1816 }
1817}
1818
1819
1820
1821
1822
1823
1824static void hdlcdev_tx_timeout(struct net_device *dev)
1825{
1826 SLMP_INFO *info = dev_to_port(dev);
1827 unsigned long flags;
1828
1829 if (debug_level >= DEBUG_LEVEL_INFO)
1830 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1831
1832 dev->stats.tx_errors++;
1833 dev->stats.tx_aborted_errors++;
1834
1835 spin_lock_irqsave(&info->lock,flags);
1836 tx_stop(info);
1837 spin_unlock_irqrestore(&info->lock,flags);
1838
1839 netif_wake_queue(dev);
1840}
1841
1842
1843
1844
1845
1846
1847
1848static void hdlcdev_tx_done(SLMP_INFO *info)
1849{
1850 if (netif_queue_stopped(info->netdev))
1851 netif_wake_queue(info->netdev);
1852}
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1863{
1864 struct sk_buff *skb = dev_alloc_skb(size);
1865 struct net_device *dev = info->netdev;
1866
1867 if (debug_level >= DEBUG_LEVEL_INFO)
1868 printk("hdlcdev_rx(%s)\n",dev->name);
1869
1870 if (skb == NULL) {
1871 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1872 dev->name);
1873 dev->stats.rx_dropped++;
1874 return;
1875 }
1876
1877 skb_put_data(skb, buf, size);
1878
1879 skb->protocol = hdlc_type_trans(skb, dev);
1880
1881 dev->stats.rx_packets++;
1882 dev->stats.rx_bytes += size;
1883
1884 netif_rx(skb);
1885}
1886
1887static const struct net_device_ops hdlcdev_ops = {
1888 .ndo_open = hdlcdev_open,
1889 .ndo_stop = hdlcdev_close,
1890 .ndo_start_xmit = hdlc_start_xmit,
1891 .ndo_do_ioctl = hdlcdev_ioctl,
1892 .ndo_tx_timeout = hdlcdev_tx_timeout,
1893};
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903static int hdlcdev_init(SLMP_INFO *info)
1904{
1905 int rc;
1906 struct net_device *dev;
1907 hdlc_device *hdlc;
1908
1909
1910
1911 dev = alloc_hdlcdev(info);
1912 if (!dev) {
1913 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1914 return -ENOMEM;
1915 }
1916
1917
1918 dev->mem_start = info->phys_sca_base;
1919 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1920 dev->irq = info->irq_level;
1921
1922
1923 dev->netdev_ops = &hdlcdev_ops;
1924 dev->watchdog_timeo = 10 * HZ;
1925 dev->tx_queue_len = 50;
1926
1927
1928 hdlc = dev_to_hdlc(dev);
1929 hdlc->attach = hdlcdev_attach;
1930 hdlc->xmit = hdlcdev_xmit;
1931
1932
1933 rc = register_hdlc_device(dev);
1934 if (rc) {
1935 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1936 free_netdev(dev);
1937 return rc;
1938 }
1939
1940 info->netdev = dev;
1941 return 0;
1942}
1943
1944
1945
1946
1947
1948
1949
1950static void hdlcdev_exit(SLMP_INFO *info)
1951{
1952 unregister_hdlc_device(info->netdev);
1953 free_netdev(info->netdev);
1954 info->netdev = NULL;
1955}
1956
1957#endif
1958
1959
1960
1961
1962
1963static int bh_action(SLMP_INFO *info)
1964{
1965 unsigned long flags;
1966 int rc = 0;
1967
1968 spin_lock_irqsave(&info->lock,flags);
1969
1970 if (info->pending_bh & BH_RECEIVE) {
1971 info->pending_bh &= ~BH_RECEIVE;
1972 rc = BH_RECEIVE;
1973 } else if (info->pending_bh & BH_TRANSMIT) {
1974 info->pending_bh &= ~BH_TRANSMIT;
1975 rc = BH_TRANSMIT;
1976 } else if (info->pending_bh & BH_STATUS) {
1977 info->pending_bh &= ~BH_STATUS;
1978 rc = BH_STATUS;
1979 }
1980
1981 if (!rc) {
1982
1983 info->bh_running = false;
1984 info->bh_requested = false;
1985 }
1986
1987 spin_unlock_irqrestore(&info->lock,flags);
1988
1989 return rc;
1990}
1991
1992
1993
1994static void bh_handler(struct work_struct *work)
1995{
1996 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1997 int action;
1998
1999 if ( debug_level >= DEBUG_LEVEL_BH )
2000 printk( "%s(%d):%s bh_handler() entry\n",
2001 __FILE__,__LINE__,info->device_name);
2002
2003 info->bh_running = true;
2004
2005 while((action = bh_action(info)) != 0) {
2006
2007
2008 if ( debug_level >= DEBUG_LEVEL_BH )
2009 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2010 __FILE__,__LINE__,info->device_name, action);
2011
2012 switch (action) {
2013
2014 case BH_RECEIVE:
2015 bh_receive(info);
2016 break;
2017 case BH_TRANSMIT:
2018 bh_transmit(info);
2019 break;
2020 case BH_STATUS:
2021 bh_status(info);
2022 break;
2023 default:
2024
2025 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2026 __FILE__,__LINE__,info->device_name,action);
2027 break;
2028 }
2029 }
2030
2031 if ( debug_level >= DEBUG_LEVEL_BH )
2032 printk( "%s(%d):%s bh_handler() exit\n",
2033 __FILE__,__LINE__,info->device_name);
2034}
2035
2036static void bh_receive(SLMP_INFO *info)
2037{
2038 if ( debug_level >= DEBUG_LEVEL_BH )
2039 printk( "%s(%d):%s bh_receive()\n",
2040 __FILE__,__LINE__,info->device_name);
2041
2042 while( rx_get_frame(info) );
2043}
2044
2045static void bh_transmit(SLMP_INFO *info)
2046{
2047 struct tty_struct *tty = info->port.tty;
2048
2049 if ( debug_level >= DEBUG_LEVEL_BH )
2050 printk( "%s(%d):%s bh_transmit() entry\n",
2051 __FILE__,__LINE__,info->device_name);
2052
2053 if (tty)
2054 tty_wakeup(tty);
2055}
2056
2057static void bh_status(SLMP_INFO *info)
2058{
2059 if ( debug_level >= DEBUG_LEVEL_BH )
2060 printk( "%s(%d):%s bh_status() entry\n",
2061 __FILE__,__LINE__,info->device_name);
2062
2063 info->ri_chkcount = 0;
2064 info->dsr_chkcount = 0;
2065 info->dcd_chkcount = 0;
2066 info->cts_chkcount = 0;
2067}
2068
2069static void isr_timer(SLMP_INFO * info)
2070{
2071 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2072
2073
2074 write_reg(info, IER2, 0);
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086 write_reg(info, (unsigned char)(timer + TMCS), 0);
2087
2088 info->irq_occurred = true;
2089
2090 if ( debug_level >= DEBUG_LEVEL_ISR )
2091 printk("%s(%d):%s isr_timer()\n",
2092 __FILE__,__LINE__,info->device_name);
2093}
2094
2095static void isr_rxint(SLMP_INFO * info)
2096{
2097 struct tty_struct *tty = info->port.tty;
2098 struct mgsl_icount *icount = &info->icount;
2099 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2100 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2101
2102
2103 if (status)
2104 write_reg(info, SR1, status);
2105
2106 if (status2)
2107 write_reg(info, SR2, status2);
2108
2109 if ( debug_level >= DEBUG_LEVEL_ISR )
2110 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2111 __FILE__,__LINE__,info->device_name,status,status2);
2112
2113 if (info->params.mode == MGSL_MODE_ASYNC) {
2114 if (status & BRKD) {
2115 icount->brk++;
2116
2117
2118
2119
2120 if (!(status & info->ignore_status_mask1)) {
2121 if (info->read_status_mask1 & BRKD) {
2122 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2123 if (tty && (info->port.flags & ASYNC_SAK))
2124 do_SAK(tty);
2125 }
2126 }
2127 }
2128 }
2129 else {
2130 if (status & (FLGD|IDLD)) {
2131 if (status & FLGD)
2132 info->icount.exithunt++;
2133 else if (status & IDLD)
2134 info->icount.rxidle++;
2135 wake_up_interruptible(&info->event_wait_q);
2136 }
2137 }
2138
2139 if (status & CDCD) {
2140
2141
2142
2143 get_signals( info );
2144 isr_io_pin(info,
2145 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2146 }
2147}
2148
2149
2150
2151
2152static void isr_rxrdy(SLMP_INFO * info)
2153{
2154 u16 status;
2155 unsigned char DataByte;
2156 struct mgsl_icount *icount = &info->icount;
2157
2158 if ( debug_level >= DEBUG_LEVEL_ISR )
2159 printk("%s(%d):%s isr_rxrdy\n",
2160 __FILE__,__LINE__,info->device_name);
2161
2162 while((status = read_reg(info,CST0)) & BIT0)
2163 {
2164 int flag = 0;
2165 bool over = false;
2166 DataByte = read_reg(info,TRB);
2167
2168 icount->rx++;
2169
2170 if ( status & (PE + FRME + OVRN) ) {
2171 printk("%s(%d):%s rxerr=%04X\n",
2172 __FILE__,__LINE__,info->device_name,status);
2173
2174
2175 if (status & PE)
2176 icount->parity++;
2177 else if (status & FRME)
2178 icount->frame++;
2179 else if (status & OVRN)
2180 icount->overrun++;
2181
2182
2183 if (status & info->ignore_status_mask2)
2184 continue;
2185
2186 status &= info->read_status_mask2;
2187
2188 if (status & PE)
2189 flag = TTY_PARITY;
2190 else if (status & FRME)
2191 flag = TTY_FRAME;
2192 if (status & OVRN) {
2193
2194
2195
2196
2197 over = true;
2198 }
2199 }
2200
2201 tty_insert_flip_char(&info->port, DataByte, flag);
2202 if (over)
2203 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2204 }
2205
2206 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2207 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2208 __FILE__,__LINE__,info->device_name,
2209 icount->rx,icount->brk,icount->parity,
2210 icount->frame,icount->overrun);
2211 }
2212
2213 tty_flip_buffer_push(&info->port);
2214}
2215
2216static void isr_txeom(SLMP_INFO * info, unsigned char status)
2217{
2218 if ( debug_level >= DEBUG_LEVEL_ISR )
2219 printk("%s(%d):%s isr_txeom status=%02x\n",
2220 __FILE__,__LINE__,info->device_name,status);
2221
2222 write_reg(info, TXDMA + DIR, 0x00);
2223 write_reg(info, TXDMA + DSR, 0xc0);
2224 write_reg(info, TXDMA + DCMD, SWABORT);
2225
2226 if (status & UDRN) {
2227 write_reg(info, CMD, TXRESET);
2228 write_reg(info, CMD, TXENABLE);
2229 } else
2230 write_reg(info, CMD, TXBUFCLR);
2231
2232
2233 info->ie0_value &= ~TXRDYE;
2234 info->ie1_value &= ~(IDLE + UDRN);
2235 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2236 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2237
2238 if ( info->tx_active ) {
2239 if (info->params.mode != MGSL_MODE_ASYNC) {
2240 if (status & UDRN)
2241 info->icount.txunder++;
2242 else if (status & IDLE)
2243 info->icount.txok++;
2244 }
2245
2246 info->tx_active = false;
2247 info->tx_count = info->tx_put = info->tx_get = 0;
2248
2249 del_timer(&info->tx_timer);
2250
2251 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2252 info->serial_signals &= ~SerialSignal_RTS;
2253 info->drop_rts_on_tx_done = false;
2254 set_signals(info);
2255 }
2256
2257#if SYNCLINK_GENERIC_HDLC
2258 if (info->netcount)
2259 hdlcdev_tx_done(info);
2260 else
2261#endif
2262 {
2263 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2264 tx_stop(info);
2265 return;
2266 }
2267 info->pending_bh |= BH_TRANSMIT;
2268 }
2269 }
2270}
2271
2272
2273
2274
2275
2276static void isr_txint(SLMP_INFO * info)
2277{
2278 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2279
2280
2281 write_reg(info, SR1, status);
2282
2283 if ( debug_level >= DEBUG_LEVEL_ISR )
2284 printk("%s(%d):%s isr_txint status=%02x\n",
2285 __FILE__,__LINE__,info->device_name,status);
2286
2287 if (status & (UDRN + IDLE))
2288 isr_txeom(info, status);
2289
2290 if (status & CCTS) {
2291
2292
2293
2294 get_signals( info );
2295 isr_io_pin(info,
2296 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2297
2298 }
2299}
2300
2301
2302
2303
2304static void isr_txrdy(SLMP_INFO * info)
2305{
2306 if ( debug_level >= DEBUG_LEVEL_ISR )
2307 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2308 __FILE__,__LINE__,info->device_name,info->tx_count);
2309
2310 if (info->params.mode != MGSL_MODE_ASYNC) {
2311
2312 info->ie0_value &= ~TXRDYE;
2313 info->ie1_value |= IDLE;
2314 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2315 return;
2316 }
2317
2318 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2319 tx_stop(info);
2320 return;
2321 }
2322
2323 if ( info->tx_count )
2324 tx_load_fifo( info );
2325 else {
2326 info->tx_active = false;
2327 info->ie0_value &= ~TXRDYE;
2328 write_reg(info, IE0, info->ie0_value);
2329 }
2330
2331 if (info->tx_count < WAKEUP_CHARS)
2332 info->pending_bh |= BH_TRANSMIT;
2333}
2334
2335static void isr_rxdmaok(SLMP_INFO * info)
2336{
2337
2338
2339
2340 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2341
2342
2343 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2344
2345 if ( debug_level >= DEBUG_LEVEL_ISR )
2346 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2347 __FILE__,__LINE__,info->device_name,status);
2348
2349 info->pending_bh |= BH_RECEIVE;
2350}
2351
2352static void isr_rxdmaerror(SLMP_INFO * info)
2353{
2354
2355
2356
2357 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2358
2359
2360 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2361
2362 if ( debug_level >= DEBUG_LEVEL_ISR )
2363 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2364 __FILE__,__LINE__,info->device_name,status);
2365
2366 info->rx_overflow = true;
2367 info->pending_bh |= BH_RECEIVE;
2368}
2369
2370static void isr_txdmaok(SLMP_INFO * info)
2371{
2372 unsigned char status_reg1 = read_reg(info, SR1);
2373
2374 write_reg(info, TXDMA + DIR, 0x00);
2375 write_reg(info, TXDMA + DSR, 0xc0);
2376 write_reg(info, TXDMA + DCMD, SWABORT);
2377
2378 if ( debug_level >= DEBUG_LEVEL_ISR )
2379 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2380 __FILE__,__LINE__,info->device_name,status_reg1);
2381
2382
2383 write_reg16(info, TRC0, 0);
2384 info->ie0_value |= TXRDYE;
2385 write_reg(info, IE0, info->ie0_value);
2386}
2387
2388static void isr_txdmaerror(SLMP_INFO * info)
2389{
2390
2391
2392
2393 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2394
2395
2396 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2397
2398 if ( debug_level >= DEBUG_LEVEL_ISR )
2399 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2400 __FILE__,__LINE__,info->device_name,status);
2401}
2402
2403
2404
2405static void isr_io_pin( SLMP_INFO *info, u16 status )
2406{
2407 struct mgsl_icount *icount;
2408
2409 if ( debug_level >= DEBUG_LEVEL_ISR )
2410 printk("%s(%d):isr_io_pin status=%04X\n",
2411 __FILE__,__LINE__,status);
2412
2413 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2414 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2415 icount = &info->icount;
2416
2417 if (status & MISCSTATUS_RI_LATCHED) {
2418 icount->rng++;
2419 if ( status & SerialSignal_RI )
2420 info->input_signal_events.ri_up++;
2421 else
2422 info->input_signal_events.ri_down++;
2423 }
2424 if (status & MISCSTATUS_DSR_LATCHED) {
2425 icount->dsr++;
2426 if ( status & SerialSignal_DSR )
2427 info->input_signal_events.dsr_up++;
2428 else
2429 info->input_signal_events.dsr_down++;
2430 }
2431 if (status & MISCSTATUS_DCD_LATCHED) {
2432 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2433 info->ie1_value &= ~CDCD;
2434 write_reg(info, IE1, info->ie1_value);
2435 }
2436 icount->dcd++;
2437 if (status & SerialSignal_DCD) {
2438 info->input_signal_events.dcd_up++;
2439 } else
2440 info->input_signal_events.dcd_down++;
2441#if SYNCLINK_GENERIC_HDLC
2442 if (info->netcount) {
2443 if (status & SerialSignal_DCD)
2444 netif_carrier_on(info->netdev);
2445 else
2446 netif_carrier_off(info->netdev);
2447 }
2448#endif
2449 }
2450 if (status & MISCSTATUS_CTS_LATCHED)
2451 {
2452 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2453 info->ie1_value &= ~CCTS;
2454 write_reg(info, IE1, info->ie1_value);
2455 }
2456 icount->cts++;
2457 if ( status & SerialSignal_CTS )
2458 info->input_signal_events.cts_up++;
2459 else
2460 info->input_signal_events.cts_down++;
2461 }
2462 wake_up_interruptible(&info->status_event_wait_q);
2463 wake_up_interruptible(&info->event_wait_q);
2464
2465 if (tty_port_check_carrier(&info->port) &&
2466 (status & MISCSTATUS_DCD_LATCHED) ) {
2467 if ( debug_level >= DEBUG_LEVEL_ISR )
2468 printk("%s CD now %s...", info->device_name,
2469 (status & SerialSignal_DCD) ? "on" : "off");
2470 if (status & SerialSignal_DCD)
2471 wake_up_interruptible(&info->port.open_wait);
2472 else {
2473 if ( debug_level >= DEBUG_LEVEL_ISR )
2474 printk("doing serial hangup...");
2475 if (info->port.tty)
2476 tty_hangup(info->port.tty);
2477 }
2478 }
2479
2480 if (tty_port_cts_enabled(&info->port) &&
2481 (status & MISCSTATUS_CTS_LATCHED) ) {
2482 if ( info->port.tty ) {
2483 if (info->port.tty->hw_stopped) {
2484 if (status & SerialSignal_CTS) {
2485 if ( debug_level >= DEBUG_LEVEL_ISR )
2486 printk("CTS tx start...");
2487 info->port.tty->hw_stopped = 0;
2488 tx_start(info);
2489 info->pending_bh |= BH_TRANSMIT;
2490 return;
2491 }
2492 } else {
2493 if (!(status & SerialSignal_CTS)) {
2494 if ( debug_level >= DEBUG_LEVEL_ISR )
2495 printk("CTS tx stop...");
2496 info->port.tty->hw_stopped = 1;
2497 tx_stop(info);
2498 }
2499 }
2500 }
2501 }
2502 }
2503
2504 info->pending_bh |= BH_STATUS;
2505}
2506
2507
2508
2509
2510
2511
2512
2513
2514static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2515{
2516 SLMP_INFO *info = dev_id;
2517 unsigned char status, status0, status1=0;
2518 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2519 unsigned char timerstatus0, timerstatus1=0;
2520 unsigned char shift;
2521 unsigned int i;
2522 unsigned short tmp;
2523
2524 if ( debug_level >= DEBUG_LEVEL_ISR )
2525 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2526 __FILE__, __LINE__, info->irq_level);
2527
2528 spin_lock(&info->lock);
2529
2530 for(;;) {
2531
2532
2533 tmp = read_reg16(info, ISR0);
2534 status0 = (unsigned char)tmp;
2535 dmastatus0 = (unsigned char)(tmp>>8);
2536 timerstatus0 = read_reg(info, ISR2);
2537
2538 if ( debug_level >= DEBUG_LEVEL_ISR )
2539 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2540 __FILE__, __LINE__, info->device_name,
2541 status0, dmastatus0, timerstatus0);
2542
2543 if (info->port_count == 4) {
2544
2545 tmp = read_reg16(info->port_array[2], ISR0);
2546 status1 = (unsigned char)tmp;
2547 dmastatus1 = (unsigned char)(tmp>>8);
2548 timerstatus1 = read_reg(info->port_array[2], ISR2);
2549
2550 if ( debug_level >= DEBUG_LEVEL_ISR )
2551 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2552 __FILE__,__LINE__,info->device_name,
2553 status1,dmastatus1,timerstatus1);
2554 }
2555
2556 if (!status0 && !dmastatus0 && !timerstatus0 &&
2557 !status1 && !dmastatus1 && !timerstatus1)
2558 break;
2559
2560 for(i=0; i < info->port_count ; i++) {
2561 if (info->port_array[i] == NULL)
2562 continue;
2563 if (i < 2) {
2564 status = status0;
2565 dmastatus = dmastatus0;
2566 } else {
2567 status = status1;
2568 dmastatus = dmastatus1;
2569 }
2570
2571 shift = i & 1 ? 4 :0;
2572
2573 if (status & BIT0 << shift)
2574 isr_rxrdy(info->port_array[i]);
2575 if (status & BIT1 << shift)
2576 isr_txrdy(info->port_array[i]);
2577 if (status & BIT2 << shift)
2578 isr_rxint(info->port_array[i]);
2579 if (status & BIT3 << shift)
2580 isr_txint(info->port_array[i]);
2581
2582 if (dmastatus & BIT0 << shift)
2583 isr_rxdmaerror(info->port_array[i]);
2584 if (dmastatus & BIT1 << shift)
2585 isr_rxdmaok(info->port_array[i]);
2586 if (dmastatus & BIT2 << shift)
2587 isr_txdmaerror(info->port_array[i]);
2588 if (dmastatus & BIT3 << shift)
2589 isr_txdmaok(info->port_array[i]);
2590 }
2591
2592 if (timerstatus0 & (BIT5 | BIT4))
2593 isr_timer(info->port_array[0]);
2594 if (timerstatus0 & (BIT7 | BIT6))
2595 isr_timer(info->port_array[1]);
2596 if (timerstatus1 & (BIT5 | BIT4))
2597 isr_timer(info->port_array[2]);
2598 if (timerstatus1 & (BIT7 | BIT6))
2599 isr_timer(info->port_array[3]);
2600 }
2601
2602 for(i=0; i < info->port_count ; i++) {
2603 SLMP_INFO * port = info->port_array[i];
2604
2605
2606
2607
2608
2609
2610
2611
2612 if ( port && (port->port.count || port->netcount) &&
2613 port->pending_bh && !port->bh_running &&
2614 !port->bh_requested ) {
2615 if ( debug_level >= DEBUG_LEVEL_ISR )
2616 printk("%s(%d):%s queueing bh task.\n",
2617 __FILE__,__LINE__,port->device_name);
2618 schedule_work(&port->task);
2619 port->bh_requested = true;
2620 }
2621 }
2622
2623 spin_unlock(&info->lock);
2624
2625 if ( debug_level >= DEBUG_LEVEL_ISR )
2626 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2627 __FILE__, __LINE__, info->irq_level);
2628 return IRQ_HANDLED;
2629}
2630
2631
2632
2633static int startup(SLMP_INFO * info)
2634{
2635 if ( debug_level >= DEBUG_LEVEL_INFO )
2636 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2637
2638 if (tty_port_initialized(&info->port))
2639 return 0;
2640
2641 if (!info->tx_buf) {
2642 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2643 if (!info->tx_buf) {
2644 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2645 __FILE__,__LINE__,info->device_name);
2646 return -ENOMEM;
2647 }
2648 }
2649
2650 info->pending_bh = 0;
2651
2652 memset(&info->icount, 0, sizeof(info->icount));
2653
2654
2655 reset_port(info);
2656
2657 change_params(info);
2658
2659 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2660
2661 if (info->port.tty)
2662 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2663
2664 tty_port_set_initialized(&info->port, 1);
2665
2666 return 0;
2667}
2668
2669
2670
2671static void shutdown(SLMP_INFO * info)
2672{
2673 unsigned long flags;
2674
2675 if (!tty_port_initialized(&info->port))
2676 return;
2677
2678 if (debug_level >= DEBUG_LEVEL_INFO)
2679 printk("%s(%d):%s synclinkmp_shutdown()\n",
2680 __FILE__,__LINE__, info->device_name );
2681
2682
2683
2684 wake_up_interruptible(&info->status_event_wait_q);
2685 wake_up_interruptible(&info->event_wait_q);
2686
2687 del_timer(&info->tx_timer);
2688 del_timer(&info->status_timer);
2689
2690 kfree(info->tx_buf);
2691 info->tx_buf = NULL;
2692
2693 spin_lock_irqsave(&info->lock,flags);
2694
2695 reset_port(info);
2696
2697 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2698 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2699 set_signals(info);
2700 }
2701
2702 spin_unlock_irqrestore(&info->lock,flags);
2703
2704 if (info->port.tty)
2705 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2706
2707 tty_port_set_initialized(&info->port, 0);
2708}
2709
2710static void program_hw(SLMP_INFO *info)
2711{
2712 unsigned long flags;
2713
2714 spin_lock_irqsave(&info->lock,flags);
2715
2716 rx_stop(info);
2717 tx_stop(info);
2718
2719 info->tx_count = info->tx_put = info->tx_get = 0;
2720
2721 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2722 hdlc_mode(info);
2723 else
2724 async_mode(info);
2725
2726 set_signals(info);
2727
2728 info->dcd_chkcount = 0;
2729 info->cts_chkcount = 0;
2730 info->ri_chkcount = 0;
2731 info->dsr_chkcount = 0;
2732
2733 info->ie1_value |= (CDCD|CCTS);
2734 write_reg(info, IE1, info->ie1_value);
2735
2736 get_signals(info);
2737
2738 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2739 rx_start(info);
2740
2741 spin_unlock_irqrestore(&info->lock,flags);
2742}
2743
2744
2745
2746static void change_params(SLMP_INFO *info)
2747{
2748 unsigned cflag;
2749 int bits_per_char;
2750
2751 if (!info->port.tty)
2752 return;
2753
2754 if (debug_level >= DEBUG_LEVEL_INFO)
2755 printk("%s(%d):%s change_params()\n",
2756 __FILE__,__LINE__, info->device_name );
2757
2758 cflag = info->port.tty->termios.c_cflag;
2759
2760
2761
2762 if (cflag & CBAUD)
2763 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2764 else
2765 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2766
2767
2768
2769 switch (cflag & CSIZE) {
2770 case CS5: info->params.data_bits = 5; break;
2771 case CS6: info->params.data_bits = 6; break;
2772 case CS7: info->params.data_bits = 7; break;
2773 case CS8: info->params.data_bits = 8; break;
2774
2775 default: info->params.data_bits = 7; break;
2776 }
2777
2778 if (cflag & CSTOPB)
2779 info->params.stop_bits = 2;
2780 else
2781 info->params.stop_bits = 1;
2782
2783 info->params.parity = ASYNC_PARITY_NONE;
2784 if (cflag & PARENB) {
2785 if (cflag & PARODD)
2786 info->params.parity = ASYNC_PARITY_ODD;
2787 else
2788 info->params.parity = ASYNC_PARITY_EVEN;
2789#ifdef CMSPAR
2790 if (cflag & CMSPAR)
2791 info->params.parity = ASYNC_PARITY_SPACE;
2792#endif
2793 }
2794
2795
2796
2797
2798 bits_per_char = info->params.data_bits +
2799 info->params.stop_bits + 1;
2800
2801
2802
2803
2804
2805 if (info->params.data_rate <= 460800) {
2806 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2807 }
2808
2809 if ( info->params.data_rate ) {
2810 info->timeout = (32*HZ*bits_per_char) /
2811 info->params.data_rate;
2812 }
2813 info->timeout += HZ/50;
2814
2815 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2816 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2817
2818
2819
2820 info->read_status_mask2 = OVRN;
2821 if (I_INPCK(info->port.tty))
2822 info->read_status_mask2 |= PE | FRME;
2823 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2824 info->read_status_mask1 |= BRKD;
2825 if (I_IGNPAR(info->port.tty))
2826 info->ignore_status_mask2 |= PE | FRME;
2827 if (I_IGNBRK(info->port.tty)) {
2828 info->ignore_status_mask1 |= BRKD;
2829
2830
2831
2832 if (I_IGNPAR(info->port.tty))
2833 info->ignore_status_mask2 |= OVRN;
2834 }
2835
2836 program_hw(info);
2837}
2838
2839static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2840{
2841 int err;
2842
2843 if (debug_level >= DEBUG_LEVEL_INFO)
2844 printk("%s(%d):%s get_params()\n",
2845 __FILE__,__LINE__, info->device_name);
2846
2847 if (!user_icount) {
2848 memset(&info->icount, 0, sizeof(info->icount));
2849 } else {
2850 mutex_lock(&info->port.mutex);
2851 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2852 mutex_unlock(&info->port.mutex);
2853 if (err)
2854 return -EFAULT;
2855 }
2856
2857 return 0;
2858}
2859
2860static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2861{
2862 int err;
2863 if (debug_level >= DEBUG_LEVEL_INFO)
2864 printk("%s(%d):%s get_params()\n",
2865 __FILE__,__LINE__, info->device_name);
2866
2867 mutex_lock(&info->port.mutex);
2868 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2869 mutex_unlock(&info->port.mutex);
2870 if (err) {
2871 if ( debug_level >= DEBUG_LEVEL_INFO )
2872 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2873 __FILE__,__LINE__,info->device_name);
2874 return -EFAULT;
2875 }
2876
2877 return 0;
2878}
2879
2880static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2881{
2882 unsigned long flags;
2883 MGSL_PARAMS tmp_params;
2884 int err;
2885
2886 if (debug_level >= DEBUG_LEVEL_INFO)
2887 printk("%s(%d):%s set_params\n",
2888 __FILE__,__LINE__,info->device_name );
2889 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2890 if (err) {
2891 if ( debug_level >= DEBUG_LEVEL_INFO )
2892 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2893 __FILE__,__LINE__,info->device_name);
2894 return -EFAULT;
2895 }
2896
2897 mutex_lock(&info->port.mutex);
2898 spin_lock_irqsave(&info->lock,flags);
2899 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2900 spin_unlock_irqrestore(&info->lock,flags);
2901
2902 change_params(info);
2903 mutex_unlock(&info->port.mutex);
2904
2905 return 0;
2906}
2907
2908static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2909{
2910 int err;
2911
2912 if (debug_level >= DEBUG_LEVEL_INFO)
2913 printk("%s(%d):%s get_txidle()=%d\n",
2914 __FILE__,__LINE__, info->device_name, info->idle_mode);
2915
2916 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2917 if (err) {
2918 if ( debug_level >= DEBUG_LEVEL_INFO )
2919 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2920 __FILE__,__LINE__,info->device_name);
2921 return -EFAULT;
2922 }
2923
2924 return 0;
2925}
2926
2927static int set_txidle(SLMP_INFO * info, int idle_mode)
2928{
2929 unsigned long flags;
2930
2931 if (debug_level >= DEBUG_LEVEL_INFO)
2932 printk("%s(%d):%s set_txidle(%d)\n",
2933 __FILE__,__LINE__,info->device_name, idle_mode );
2934
2935 spin_lock_irqsave(&info->lock,flags);
2936 info->idle_mode = idle_mode;
2937 tx_set_idle( info );
2938 spin_unlock_irqrestore(&info->lock,flags);
2939 return 0;
2940}
2941
2942static int tx_enable(SLMP_INFO * info, int enable)
2943{
2944 unsigned long flags;
2945
2946 if (debug_level >= DEBUG_LEVEL_INFO)
2947 printk("%s(%d):%s tx_enable(%d)\n",
2948 __FILE__,__LINE__,info->device_name, enable);
2949
2950 spin_lock_irqsave(&info->lock,flags);
2951 if ( enable ) {
2952 if ( !info->tx_enabled ) {
2953 tx_start(info);
2954 }
2955 } else {
2956 if ( info->tx_enabled )
2957 tx_stop(info);
2958 }
2959 spin_unlock_irqrestore(&info->lock,flags);
2960 return 0;
2961}
2962
2963
2964
2965static int tx_abort(SLMP_INFO * info)
2966{
2967 unsigned long flags;
2968
2969 if (debug_level >= DEBUG_LEVEL_INFO)
2970 printk("%s(%d):%s tx_abort()\n",
2971 __FILE__,__LINE__,info->device_name);
2972
2973 spin_lock_irqsave(&info->lock,flags);
2974 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2975 info->ie1_value &= ~UDRN;
2976 info->ie1_value |= IDLE;
2977 write_reg(info, IE1, info->ie1_value);
2978 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
2979
2980 write_reg(info, TXDMA + DSR, 0);
2981 write_reg(info, TXDMA + DCMD, SWABORT);
2982
2983 write_reg(info, CMD, TXABORT);
2984 }
2985 spin_unlock_irqrestore(&info->lock,flags);
2986 return 0;
2987}
2988
2989static int rx_enable(SLMP_INFO * info, int enable)
2990{
2991 unsigned long flags;
2992
2993 if (debug_level >= DEBUG_LEVEL_INFO)
2994 printk("%s(%d):%s rx_enable(%d)\n",
2995 __FILE__,__LINE__,info->device_name,enable);
2996
2997 spin_lock_irqsave(&info->lock,flags);
2998 if ( enable ) {
2999 if ( !info->rx_enabled )
3000 rx_start(info);
3001 } else {
3002 if ( info->rx_enabled )
3003 rx_stop(info);
3004 }
3005 spin_unlock_irqrestore(&info->lock,flags);
3006 return 0;
3007}
3008
3009
3010
3011static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3012{
3013 unsigned long flags;
3014 int s;
3015 int rc=0;
3016 struct mgsl_icount cprev, cnow;
3017 int events;
3018 int mask;
3019 struct _input_signal_events oldsigs, newsigs;
3020 DECLARE_WAITQUEUE(wait, current);
3021
3022 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3023 if (rc) {
3024 return -EFAULT;
3025 }
3026
3027 if (debug_level >= DEBUG_LEVEL_INFO)
3028 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3029 __FILE__,__LINE__,info->device_name,mask);
3030
3031 spin_lock_irqsave(&info->lock,flags);
3032
3033
3034 get_signals(info);
3035 s = info->serial_signals;
3036
3037 events = mask &
3038 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3039 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3040 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3041 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3042 if (events) {
3043 spin_unlock_irqrestore(&info->lock,flags);
3044 goto exit;
3045 }
3046
3047
3048 cprev = info->icount;
3049 oldsigs = info->input_signal_events;
3050
3051
3052 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3053 unsigned char oldval = info->ie1_value;
3054 unsigned char newval = oldval +
3055 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3056 (mask & MgslEvent_IdleReceived ? IDLD:0);
3057 if ( oldval != newval ) {
3058 info->ie1_value = newval;
3059 write_reg(info, IE1, info->ie1_value);
3060 }
3061 }
3062
3063 set_current_state(TASK_INTERRUPTIBLE);
3064 add_wait_queue(&info->event_wait_q, &wait);
3065
3066 spin_unlock_irqrestore(&info->lock,flags);
3067
3068 for(;;) {
3069 schedule();
3070 if (signal_pending(current)) {
3071 rc = -ERESTARTSYS;
3072 break;
3073 }
3074
3075
3076 spin_lock_irqsave(&info->lock,flags);
3077 cnow = info->icount;
3078 newsigs = info->input_signal_events;
3079 set_current_state(TASK_INTERRUPTIBLE);
3080 spin_unlock_irqrestore(&info->lock,flags);
3081
3082
3083 if (newsigs.dsr_up == oldsigs.dsr_up &&
3084 newsigs.dsr_down == oldsigs.dsr_down &&
3085 newsigs.dcd_up == oldsigs.dcd_up &&
3086 newsigs.dcd_down == oldsigs.dcd_down &&
3087 newsigs.cts_up == oldsigs.cts_up &&
3088 newsigs.cts_down == oldsigs.cts_down &&
3089 newsigs.ri_up == oldsigs.ri_up &&
3090 newsigs.ri_down == oldsigs.ri_down &&
3091 cnow.exithunt == cprev.exithunt &&
3092 cnow.rxidle == cprev.rxidle) {
3093 rc = -EIO;
3094 break;
3095 }
3096
3097 events = mask &
3098 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3099 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3100 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3101 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3102 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3103 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3104 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3105 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3106 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3107 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3108 if (events)
3109 break;
3110
3111 cprev = cnow;
3112 oldsigs = newsigs;
3113 }
3114
3115 remove_wait_queue(&info->event_wait_q, &wait);
3116 set_current_state(TASK_RUNNING);
3117
3118
3119 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3120 spin_lock_irqsave(&info->lock,flags);
3121 if (!waitqueue_active(&info->event_wait_q)) {
3122
3123 info->ie1_value &= ~(FLGD|IDLD);
3124 write_reg(info, IE1, info->ie1_value);
3125 }
3126 spin_unlock_irqrestore(&info->lock,flags);
3127 }
3128exit:
3129 if ( rc == 0 )
3130 PUT_USER(rc, events, mask_ptr);
3131
3132 return rc;
3133}
3134
3135static int modem_input_wait(SLMP_INFO *info,int arg)
3136{
3137 unsigned long flags;
3138 int rc;
3139 struct mgsl_icount cprev, cnow;
3140 DECLARE_WAITQUEUE(wait, current);
3141
3142
3143 spin_lock_irqsave(&info->lock,flags);
3144 cprev = info->icount;
3145 add_wait_queue(&info->status_event_wait_q, &wait);
3146 set_current_state(TASK_INTERRUPTIBLE);
3147 spin_unlock_irqrestore(&info->lock,flags);
3148
3149 for(;;) {
3150 schedule();
3151 if (signal_pending(current)) {
3152 rc = -ERESTARTSYS;
3153 break;
3154 }
3155
3156
3157 spin_lock_irqsave(&info->lock,flags);
3158 cnow = info->icount;
3159 set_current_state(TASK_INTERRUPTIBLE);
3160 spin_unlock_irqrestore(&info->lock,flags);
3161
3162
3163 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3164 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3165 rc = -EIO;
3166 break;
3167 }
3168
3169
3170 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3171 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3172 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3173 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3174 rc = 0;
3175 break;
3176 }
3177
3178 cprev = cnow;
3179 }
3180 remove_wait_queue(&info->status_event_wait_q, &wait);
3181 set_current_state(TASK_RUNNING);
3182 return rc;
3183}
3184
3185
3186
3187static int tiocmget(struct tty_struct *tty)
3188{
3189 SLMP_INFO *info = tty->driver_data;
3190 unsigned int result;
3191 unsigned long flags;
3192
3193 spin_lock_irqsave(&info->lock,flags);
3194 get_signals(info);
3195 spin_unlock_irqrestore(&info->lock,flags);
3196
3197 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3198 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3199 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3200 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3201 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3202 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3203
3204 if (debug_level >= DEBUG_LEVEL_INFO)
3205 printk("%s(%d):%s tiocmget() value=%08X\n",
3206 __FILE__,__LINE__, info->device_name, result );
3207 return result;
3208}
3209
3210
3211
3212static int tiocmset(struct tty_struct *tty,
3213 unsigned int set, unsigned int clear)
3214{
3215 SLMP_INFO *info = tty->driver_data;
3216 unsigned long flags;
3217
3218 if (debug_level >= DEBUG_LEVEL_INFO)
3219 printk("%s(%d):%s tiocmset(%x,%x)\n",
3220 __FILE__,__LINE__,info->device_name, set, clear);
3221
3222 if (set & TIOCM_RTS)
3223 info->serial_signals |= SerialSignal_RTS;
3224 if (set & TIOCM_DTR)
3225 info->serial_signals |= SerialSignal_DTR;
3226 if (clear & TIOCM_RTS)
3227 info->serial_signals &= ~SerialSignal_RTS;
3228 if (clear & TIOCM_DTR)
3229 info->serial_signals &= ~SerialSignal_DTR;
3230
3231 spin_lock_irqsave(&info->lock,flags);
3232 set_signals(info);
3233 spin_unlock_irqrestore(&info->lock,flags);
3234
3235 return 0;
3236}
3237
3238static int carrier_raised(struct tty_port *port)
3239{
3240 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3241 unsigned long flags;
3242
3243 spin_lock_irqsave(&info->lock,flags);
3244 get_signals(info);
3245 spin_unlock_irqrestore(&info->lock,flags);
3246
3247 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3248}
3249
3250static void dtr_rts(struct tty_port *port, int on)
3251{
3252 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3253 unsigned long flags;
3254
3255 spin_lock_irqsave(&info->lock,flags);
3256 if (on)
3257 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3258 else
3259 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3260 set_signals(info);
3261 spin_unlock_irqrestore(&info->lock,flags);
3262}
3263
3264
3265
3266static int block_til_ready(struct tty_struct *tty, struct file *filp,
3267 SLMP_INFO *info)
3268{
3269 DECLARE_WAITQUEUE(wait, current);
3270 int retval;
3271 bool do_clocal = false;
3272 unsigned long flags;
3273 int cd;
3274 struct tty_port *port = &info->port;
3275
3276 if (debug_level >= DEBUG_LEVEL_INFO)
3277 printk("%s(%d):%s block_til_ready()\n",
3278 __FILE__,__LINE__, tty->driver->name );
3279
3280 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3281
3282
3283 tty_port_set_active(port, 1);
3284 return 0;
3285 }
3286
3287 if (C_CLOCAL(tty))
3288 do_clocal = true;
3289
3290
3291
3292
3293
3294
3295
3296
3297 retval = 0;
3298 add_wait_queue(&port->open_wait, &wait);
3299
3300 if (debug_level >= DEBUG_LEVEL_INFO)
3301 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3302 __FILE__,__LINE__, tty->driver->name, port->count );
3303
3304 spin_lock_irqsave(&info->lock, flags);
3305 port->count--;
3306 spin_unlock_irqrestore(&info->lock, flags);
3307 port->blocked_open++;
3308
3309 while (1) {
3310 if (C_BAUD(tty) && tty_port_initialized(port))
3311 tty_port_raise_dtr_rts(port);
3312
3313 set_current_state(TASK_INTERRUPTIBLE);
3314
3315 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3316 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3317 -EAGAIN : -ERESTARTSYS;
3318 break;
3319 }
3320
3321 cd = tty_port_carrier_raised(port);
3322 if (do_clocal || cd)
3323 break;
3324
3325 if (signal_pending(current)) {
3326 retval = -ERESTARTSYS;
3327 break;
3328 }
3329
3330 if (debug_level >= DEBUG_LEVEL_INFO)
3331 printk("%s(%d):%s block_til_ready() count=%d\n",
3332 __FILE__,__LINE__, tty->driver->name, port->count );
3333
3334 tty_unlock(tty);
3335 schedule();
3336 tty_lock(tty);
3337 }
3338
3339 set_current_state(TASK_RUNNING);
3340 remove_wait_queue(&port->open_wait, &wait);
3341 if (!tty_hung_up_p(filp))
3342 port->count++;
3343 port->blocked_open--;
3344
3345 if (debug_level >= DEBUG_LEVEL_INFO)
3346 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3347 __FILE__,__LINE__, tty->driver->name, port->count );
3348
3349 if (!retval)
3350 tty_port_set_active(port, 1);
3351
3352 return retval;
3353}
3354
3355static int alloc_dma_bufs(SLMP_INFO *info)
3356{
3357 unsigned short BuffersPerFrame;
3358 unsigned short BufferCount;
3359
3360
3361
3362
3363
3364
3365 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3366
3367
3368
3369
3370
3371
3372 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3373 if ( info->max_frame_size % SCABUFSIZE )
3374 BuffersPerFrame++;
3375
3376
3377
3378
3379
3380 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3381
3382
3383 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3384 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3385
3386
3387 info->tx_buf_count = BuffersPerFrame + 1;
3388
3389
3390 if (info->tx_buf_count > (BufferCount/2))
3391 info->tx_buf_count = BufferCount/2;
3392
3393 if (info->tx_buf_count > SCAMAXDESC)
3394 info->tx_buf_count = SCAMAXDESC;
3395
3396
3397 info->rx_buf_count = BufferCount - info->tx_buf_count;
3398
3399 if (info->rx_buf_count > SCAMAXDESC)
3400 info->rx_buf_count = SCAMAXDESC;
3401
3402 if ( debug_level >= DEBUG_LEVEL_INFO )
3403 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3404 __FILE__,__LINE__, info->device_name,
3405 info->tx_buf_count,info->rx_buf_count);
3406
3407 if ( alloc_buf_list( info ) < 0 ||
3408 alloc_frame_bufs(info,
3409 info->rx_buf_list,
3410 info->rx_buf_list_ex,
3411 info->rx_buf_count) < 0 ||
3412 alloc_frame_bufs(info,
3413 info->tx_buf_list,
3414 info->tx_buf_list_ex,
3415 info->tx_buf_count) < 0 ||
3416 alloc_tmp_rx_buf(info) < 0 ) {
3417 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3418 __FILE__,__LINE__, info->device_name);
3419 return -ENOMEM;
3420 }
3421
3422 rx_reset_buffers( info );
3423
3424 return 0;
3425}
3426
3427
3428
3429static int alloc_buf_list(SLMP_INFO *info)
3430{
3431 unsigned int i;
3432
3433
3434 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3435 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3436 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3437
3438 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3439
3440
3441
3442
3443 info->rx_buf_list = (SCADESC *)info->buffer_list;
3444
3445 info->tx_buf_list = (SCADESC *)info->buffer_list;
3446 info->tx_buf_list += info->rx_buf_count;
3447
3448
3449
3450
3451
3452
3453
3454 for ( i = 0; i < info->rx_buf_count; i++ ) {
3455
3456 info->rx_buf_list_ex[i].phys_entry =
3457 info->buffer_list_phys + (i * SCABUFSIZE);
3458
3459
3460
3461 info->rx_buf_list[i].next = info->buffer_list_phys;
3462 if ( i < info->rx_buf_count - 1 )
3463 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3464
3465 info->rx_buf_list[i].length = SCABUFSIZE;
3466 }
3467
3468 for ( i = 0; i < info->tx_buf_count; i++ ) {
3469
3470 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3471 ((info->rx_buf_count + i) * sizeof(SCADESC));
3472
3473
3474
3475
3476 info->tx_buf_list[i].next = info->buffer_list_phys +
3477 info->rx_buf_count * sizeof(SCADESC);
3478
3479 if ( i < info->tx_buf_count - 1 )
3480 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3481 }
3482
3483 return 0;
3484}
3485
3486
3487
3488static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3489{
3490 int i;
3491 unsigned long phys_addr;
3492
3493 for ( i = 0; i < count; i++ ) {
3494 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3495 phys_addr = info->port_array[0]->last_mem_alloc;
3496 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3497
3498 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3499 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3500 }
3501
3502 return 0;
3503}
3504
3505static void free_dma_bufs(SLMP_INFO *info)
3506{
3507 info->buffer_list = NULL;
3508 info->rx_buf_list = NULL;
3509 info->tx_buf_list = NULL;
3510}
3511
3512
3513
3514
3515static int alloc_tmp_rx_buf(SLMP_INFO *info)
3516{
3517 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3518 if (info->tmp_rx_buf == NULL)
3519 return -ENOMEM;
3520
3521 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3522 if (!info->flag_buf) {
3523 kfree(info->tmp_rx_buf);
3524 info->tmp_rx_buf = NULL;
3525 return -ENOMEM;
3526 }
3527 return 0;
3528}
3529
3530static void free_tmp_rx_buf(SLMP_INFO *info)
3531{
3532 kfree(info->tmp_rx_buf);
3533 info->tmp_rx_buf = NULL;
3534 kfree(info->flag_buf);
3535 info->flag_buf = NULL;
3536}
3537
3538static int claim_resources(SLMP_INFO *info)
3539{
3540 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3541 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3542 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3543 info->init_error = DiagStatus_AddressConflict;
3544 goto errout;
3545 }
3546 else
3547 info->shared_mem_requested = true;
3548
3549 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3550 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3551 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3552 info->init_error = DiagStatus_AddressConflict;
3553 goto errout;
3554 }
3555 else
3556 info->lcr_mem_requested = true;
3557
3558 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3559 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3560 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3561 info->init_error = DiagStatus_AddressConflict;
3562 goto errout;
3563 }
3564 else
3565 info->sca_base_requested = true;
3566
3567 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3568 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3569 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3570 info->init_error = DiagStatus_AddressConflict;
3571 goto errout;
3572 }
3573 else
3574 info->sca_statctrl_requested = true;
3575
3576 info->memory_base = ioremap_nocache(info->phys_memory_base,
3577 SCA_MEM_SIZE);
3578 if (!info->memory_base) {
3579 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3580 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3581 info->init_error = DiagStatus_CantAssignPciResources;
3582 goto errout;
3583 }
3584
3585 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3586 if (!info->lcr_base) {
3587 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3588 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3589 info->init_error = DiagStatus_CantAssignPciResources;
3590 goto errout;
3591 }
3592 info->lcr_base += info->lcr_offset;
3593
3594 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3595 if (!info->sca_base) {
3596 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3597 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3598 info->init_error = DiagStatus_CantAssignPciResources;
3599 goto errout;
3600 }
3601 info->sca_base += info->sca_offset;
3602
3603 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3604 PAGE_SIZE);
3605 if (!info->statctrl_base) {
3606 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3607 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3608 info->init_error = DiagStatus_CantAssignPciResources;
3609 goto errout;
3610 }
3611 info->statctrl_base += info->statctrl_offset;
3612
3613 if ( !memory_test(info) ) {
3614 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3615 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3616 info->init_error = DiagStatus_MemoryError;
3617 goto errout;
3618 }
3619
3620 return 0;
3621
3622errout:
3623 release_resources( info );
3624 return -ENODEV;
3625}
3626
3627static void release_resources(SLMP_INFO *info)
3628{
3629 if ( debug_level >= DEBUG_LEVEL_INFO )
3630 printk( "%s(%d):%s release_resources() entry\n",
3631 __FILE__,__LINE__,info->device_name );
3632
3633 if ( info->irq_requested ) {
3634 free_irq(info->irq_level, info);
3635 info->irq_requested = false;
3636 }
3637
3638 if ( info->shared_mem_requested ) {
3639 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3640 info->shared_mem_requested = false;
3641 }
3642 if ( info->lcr_mem_requested ) {
3643 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3644 info->lcr_mem_requested = false;
3645 }
3646 if ( info->sca_base_requested ) {
3647 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3648 info->sca_base_requested = false;
3649 }
3650 if ( info->sca_statctrl_requested ) {
3651 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3652 info->sca_statctrl_requested = false;
3653 }
3654
3655 if (info->memory_base){
3656 iounmap(info->memory_base);
3657 info->memory_base = NULL;
3658 }
3659
3660 if (info->sca_base) {
3661 iounmap(info->sca_base - info->sca_offset);
3662 info->sca_base=NULL;
3663 }
3664
3665 if (info->statctrl_base) {
3666 iounmap(info->statctrl_base - info->statctrl_offset);
3667 info->statctrl_base=NULL;
3668 }
3669
3670 if (info->lcr_base){
3671 iounmap(info->lcr_base - info->lcr_offset);
3672 info->lcr_base = NULL;
3673 }
3674
3675 if ( debug_level >= DEBUG_LEVEL_INFO )
3676 printk( "%s(%d):%s release_resources() exit\n",
3677 __FILE__,__LINE__,info->device_name );
3678}
3679
3680
3681
3682
3683static int add_device(SLMP_INFO *info)
3684{
3685 info->next_device = NULL;
3686 info->line = synclinkmp_device_count;
3687 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3688
3689 if (info->line < MAX_DEVICES) {
3690 if (maxframe[info->line])
3691 info->max_frame_size = maxframe[info->line];
3692 }
3693
3694 synclinkmp_device_count++;
3695
3696 if ( !synclinkmp_device_list )
3697 synclinkmp_device_list = info;
3698 else {
3699 SLMP_INFO *current_dev = synclinkmp_device_list;
3700 while( current_dev->next_device )
3701 current_dev = current_dev->next_device;
3702 current_dev->next_device = info;
3703 }
3704
3705 if ( info->max_frame_size < 4096 )
3706 info->max_frame_size = 4096;
3707 else if ( info->max_frame_size > 65535 )
3708 info->max_frame_size = 65535;
3709
3710 printk( "SyncLink MultiPort %s: "
3711 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3712 info->device_name,
3713 info->phys_sca_base,
3714 info->phys_memory_base,
3715 info->phys_statctrl_base,
3716 info->phys_lcr_base,
3717 info->irq_level,
3718 info->max_frame_size );
3719
3720#if SYNCLINK_GENERIC_HDLC
3721 return hdlcdev_init(info);
3722#else
3723 return 0;
3724#endif
3725}
3726
3727static const struct tty_port_operations port_ops = {
3728 .carrier_raised = carrier_raised,
3729 .dtr_rts = dtr_rts,
3730};
3731
3732
3733
3734
3735
3736static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3737{
3738 SLMP_INFO *info;
3739
3740 info = kzalloc(sizeof(SLMP_INFO),
3741 GFP_KERNEL);
3742
3743 if (!info) {
3744 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3745 __FILE__,__LINE__, adapter_num, port_num);
3746 } else {
3747 tty_port_init(&info->port);
3748 info->port.ops = &port_ops;
3749 info->magic = MGSL_MAGIC;
3750 INIT_WORK(&info->task, bh_handler);
3751 info->max_frame_size = 4096;
3752 info->port.close_delay = 5*HZ/10;
3753 info->port.closing_wait = 30*HZ;
3754 init_waitqueue_head(&info->status_event_wait_q);
3755 init_waitqueue_head(&info->event_wait_q);
3756 spin_lock_init(&info->netlock);
3757 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3758 info->idle_mode = HDLC_TXIDLE_FLAGS;
3759 info->adapter_num = adapter_num;
3760 info->port_num = port_num;
3761
3762
3763 info->irq_level = pdev->irq;
3764 info->phys_lcr_base = pci_resource_start(pdev,0);
3765 info->phys_sca_base = pci_resource_start(pdev,2);
3766 info->phys_memory_base = pci_resource_start(pdev,3);
3767 info->phys_statctrl_base = pci_resource_start(pdev,4);
3768
3769
3770
3771
3772
3773 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3774 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3775
3776 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3777 info->phys_sca_base &= ~(PAGE_SIZE-1);
3778
3779 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3780 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3781
3782 info->bus_type = MGSL_BUS_TYPE_PCI;
3783 info->irq_flags = IRQF_SHARED;
3784
3785 timer_setup(&info->tx_timer, tx_timeout, 0);
3786 timer_setup(&info->status_timer, status_timeout, 0);
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797 info->misc_ctrl_value = 0x087e4546;
3798
3799
3800
3801
3802
3803
3804
3805 info->init_error = -1;
3806 }
3807
3808 return info;
3809}
3810
3811static int device_init(int adapter_num, struct pci_dev *pdev)
3812{
3813 SLMP_INFO *port_array[SCA_MAX_PORTS];
3814 int port, rc;
3815
3816
3817 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3818 port_array[port] = alloc_dev(adapter_num,port,pdev);
3819 if( port_array[port] == NULL ) {
3820 for (--port; port >= 0; --port) {
3821 tty_port_destroy(&port_array[port]->port);
3822 kfree(port_array[port]);
3823 }
3824 return -ENOMEM;
3825 }
3826 }
3827
3828
3829 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3830 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3831 rc = add_device( port_array[port] );
3832 if (rc)
3833 goto err_add;
3834 spin_lock_init(&port_array[port]->lock);
3835 }
3836
3837
3838 if ( !claim_resources(port_array[0]) ) {
3839
3840 alloc_dma_bufs(port_array[0]);
3841
3842
3843 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3844 port_array[port]->lock = port_array[0]->lock;
3845 port_array[port]->irq_level = port_array[0]->irq_level;
3846 port_array[port]->memory_base = port_array[0]->memory_base;
3847 port_array[port]->sca_base = port_array[0]->sca_base;
3848 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3849 port_array[port]->lcr_base = port_array[0]->lcr_base;
3850 alloc_dma_bufs(port_array[port]);
3851 }
3852
3853 rc = request_irq(port_array[0]->irq_level,
3854 synclinkmp_interrupt,
3855 port_array[0]->irq_flags,
3856 port_array[0]->device_name,
3857 port_array[0]);
3858 if ( rc ) {
3859 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3860 __FILE__,__LINE__,
3861 port_array[0]->device_name,
3862 port_array[0]->irq_level );
3863 goto err_irq;
3864 }
3865 port_array[0]->irq_requested = true;
3866 adapter_test(port_array[0]);
3867 }
3868 return 0;
3869err_irq:
3870 release_resources( port_array[0] );
3871err_add:
3872 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3873 tty_port_destroy(&port_array[port]->port);
3874 kfree(port_array[port]);
3875 }
3876 return rc;
3877}
3878
3879static const struct tty_operations ops = {
3880 .install = install,
3881 .open = open,
3882 .close = close,
3883 .write = write,
3884 .put_char = put_char,
3885 .flush_chars = flush_chars,
3886 .write_room = write_room,
3887 .chars_in_buffer = chars_in_buffer,
3888 .flush_buffer = flush_buffer,
3889 .ioctl = ioctl,
3890 .throttle = throttle,
3891 .unthrottle = unthrottle,
3892 .send_xchar = send_xchar,
3893 .break_ctl = set_break,
3894 .wait_until_sent = wait_until_sent,
3895 .set_termios = set_termios,
3896 .stop = tx_hold,
3897 .start = tx_release,
3898 .hangup = hangup,
3899 .tiocmget = tiocmget,
3900 .tiocmset = tiocmset,
3901 .get_icount = get_icount,
3902 .proc_fops = &synclinkmp_proc_fops,
3903};
3904
3905
3906static void synclinkmp_cleanup(void)
3907{
3908 int rc;
3909 SLMP_INFO *info;
3910 SLMP_INFO *tmp;
3911
3912 printk("Unloading %s %s\n", driver_name, driver_version);
3913
3914 if (serial_driver) {
3915 rc = tty_unregister_driver(serial_driver);
3916 if (rc)
3917 printk("%s(%d) failed to unregister tty driver err=%d\n",
3918 __FILE__,__LINE__,rc);
3919 put_tty_driver(serial_driver);
3920 }
3921
3922
3923 info = synclinkmp_device_list;
3924 while(info) {
3925 reset_port(info);
3926 info = info->next_device;
3927 }
3928
3929
3930 info = synclinkmp_device_list;
3931 while(info) {
3932#if SYNCLINK_GENERIC_HDLC
3933 hdlcdev_exit(info);
3934#endif
3935 free_dma_bufs(info);
3936 free_tmp_rx_buf(info);
3937 if ( info->port_num == 0 ) {
3938 if (info->sca_base)
3939 write_reg(info, LPR, 1);
3940 release_resources(info);
3941 }
3942 tmp = info;
3943 info = info->next_device;
3944 tty_port_destroy(&tmp->port);
3945 kfree(tmp);
3946 }
3947
3948 pci_unregister_driver(&synclinkmp_pci_driver);
3949}
3950
3951
3952
3953
3954static int __init synclinkmp_init(void)
3955{
3956 int rc;
3957
3958 if (break_on_load) {
3959 synclinkmp_get_text_ptr();
3960 BREAKPOINT();
3961 }
3962
3963 printk("%s %s\n", driver_name, driver_version);
3964
3965 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3966 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3967 return rc;
3968 }
3969
3970 serial_driver = alloc_tty_driver(128);
3971 if (!serial_driver) {
3972 rc = -ENOMEM;
3973 goto error;
3974 }
3975
3976
3977
3978 serial_driver->driver_name = "synclinkmp";
3979 serial_driver->name = "ttySLM";
3980 serial_driver->major = ttymajor;
3981 serial_driver->minor_start = 64;
3982 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3983 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3984 serial_driver->init_termios = tty_std_termios;
3985 serial_driver->init_termios.c_cflag =
3986 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3987 serial_driver->init_termios.c_ispeed = 9600;
3988 serial_driver->init_termios.c_ospeed = 9600;
3989 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3990 tty_set_operations(serial_driver, &ops);
3991 if ((rc = tty_register_driver(serial_driver)) < 0) {
3992 printk("%s(%d):Couldn't register serial driver\n",
3993 __FILE__,__LINE__);
3994 put_tty_driver(serial_driver);
3995 serial_driver = NULL;
3996 goto error;
3997 }
3998
3999 printk("%s %s, tty major#%d\n",
4000 driver_name, driver_version,
4001 serial_driver->major);
4002
4003 return 0;
4004
4005error:
4006 synclinkmp_cleanup();
4007 return rc;
4008}
4009
4010static void __exit synclinkmp_exit(void)
4011{
4012 synclinkmp_cleanup();
4013}
4014
4015module_init(synclinkmp_init);
4016module_exit(synclinkmp_exit);
4017
4018
4019
4020
4021
4022static void enable_loopback(SLMP_INFO *info, int enable)
4023{
4024 if (enable) {
4025
4026
4027
4028 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4029
4030
4031 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4032 write_control_reg(info);
4033
4034
4035
4036
4037
4038
4039 write_reg(info, RXS, 0x40);
4040 write_reg(info, TXS, 0x40);
4041
4042 } else {
4043
4044
4045
4046 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4047
4048
4049
4050
4051
4052
4053 write_reg(info, RXS, 0x00);
4054 write_reg(info, TXS, 0x00);
4055 }
4056
4057
4058 if (info->params.clock_speed)
4059 set_rate(info, info->params.clock_speed);
4060 else
4061 set_rate(info, 3686400);
4062}
4063
4064
4065
4066
4067
4068
4069static void set_rate( SLMP_INFO *info, u32 data_rate )
4070{
4071 u32 TMCValue;
4072 unsigned char BRValue;
4073 u32 Divisor=0;
4074
4075
4076
4077 if (data_rate != 0) {
4078 Divisor = 14745600/data_rate;
4079 if (!Divisor)
4080 Divisor = 1;
4081
4082 TMCValue = Divisor;
4083
4084 BRValue = 0;
4085 if (TMCValue != 1 && TMCValue != 2) {
4086
4087
4088
4089
4090 BRValue = 1;
4091 TMCValue >>= 1;
4092 }
4093
4094
4095
4096
4097 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4098 TMCValue >>= 1;
4099
4100 write_reg(info, TXS,
4101 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4102 write_reg(info, RXS,
4103 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4104 write_reg(info, TMC, (unsigned char)TMCValue);
4105 }
4106 else {
4107 write_reg(info, TXS,0);
4108 write_reg(info, RXS,0);
4109 write_reg(info, TMC, 0);
4110 }
4111}
4112
4113
4114
4115static void rx_stop(SLMP_INFO *info)
4116{
4117 if (debug_level >= DEBUG_LEVEL_ISR)
4118 printk("%s(%d):%s rx_stop()\n",
4119 __FILE__,__LINE__, info->device_name );
4120
4121 write_reg(info, CMD, RXRESET);
4122
4123 info->ie0_value &= ~RXRDYE;
4124 write_reg(info, IE0, info->ie0_value);
4125
4126 write_reg(info, RXDMA + DSR, 0);
4127 write_reg(info, RXDMA + DCMD, SWABORT);
4128 write_reg(info, RXDMA + DIR, 0);
4129
4130 info->rx_enabled = false;
4131 info->rx_overflow = false;
4132}
4133
4134
4135
4136static void rx_start(SLMP_INFO *info)
4137{
4138 int i;
4139
4140 if (debug_level >= DEBUG_LEVEL_ISR)
4141 printk("%s(%d):%s rx_start()\n",
4142 __FILE__,__LINE__, info->device_name );
4143
4144 write_reg(info, CMD, RXRESET);
4145
4146 if ( info->params.mode == MGSL_MODE_HDLC ) {
4147
4148 info->ie0_value &= ~RXRDYE;
4149 write_reg(info, IE0, info->ie0_value);
4150
4151
4152 write_reg(info, RXDMA + DSR, 0);
4153 write_reg(info, RXDMA + DCMD, SWABORT);
4154
4155 for (i = 0; i < info->rx_buf_count; i++) {
4156 info->rx_buf_list[i].status = 0xff;
4157
4158
4159
4160 if (!(i % 4))
4161 read_status_reg(info);
4162 }
4163 info->current_rx_buf = 0;
4164
4165
4166 write_reg16(info, RXDMA + CDA,
4167 info->rx_buf_list_ex[0].phys_entry);
4168
4169
4170 write_reg16(info, RXDMA + EDA,
4171 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4172
4173
4174 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4175
4176 write_reg(info, RXDMA + DIR, 0x60);
4177 write_reg(info, RXDMA + DSR, 0xf2);
4178 } else {
4179
4180 info->ie0_value |= RXRDYE;
4181 write_reg(info, IE0, info->ie0_value);
4182 }
4183
4184 write_reg(info, CMD, RXENABLE);
4185
4186 info->rx_overflow = false;
4187 info->rx_enabled = true;
4188}
4189
4190
4191
4192
4193static void tx_start(SLMP_INFO *info)
4194{
4195 if (debug_level >= DEBUG_LEVEL_ISR)
4196 printk("%s(%d):%s tx_start() tx_count=%d\n",
4197 __FILE__,__LINE__, info->device_name,info->tx_count );
4198
4199 if (!info->tx_enabled ) {
4200 write_reg(info, CMD, TXRESET);
4201 write_reg(info, CMD, TXENABLE);
4202 info->tx_enabled = true;
4203 }
4204
4205 if ( info->tx_count ) {
4206
4207
4208
4209
4210
4211 info->drop_rts_on_tx_done = false;
4212
4213 if (info->params.mode != MGSL_MODE_ASYNC) {
4214
4215 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4216 get_signals( info );
4217 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4218 info->serial_signals |= SerialSignal_RTS;
4219 set_signals( info );
4220 info->drop_rts_on_tx_done = true;
4221 }
4222 }
4223
4224 write_reg16(info, TRC0,
4225 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4226
4227 write_reg(info, TXDMA + DSR, 0);
4228 write_reg(info, TXDMA + DCMD, SWABORT);
4229
4230
4231 write_reg16(info, TXDMA + CDA,
4232 info->tx_buf_list_ex[0].phys_entry);
4233
4234
4235 write_reg16(info, TXDMA + EDA,
4236 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4237
4238
4239 info->ie1_value &= ~IDLE;
4240 info->ie1_value |= UDRN;
4241 write_reg(info, IE1, info->ie1_value);
4242 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4243
4244 write_reg(info, TXDMA + DIR, 0x40);
4245 write_reg(info, TXDMA + DSR, 0xf2);
4246
4247 mod_timer(&info->tx_timer, jiffies +
4248 msecs_to_jiffies(5000));
4249 }
4250 else {
4251 tx_load_fifo(info);
4252
4253 info->ie0_value |= TXRDYE;
4254 write_reg(info, IE0, info->ie0_value);
4255 }
4256
4257 info->tx_active = true;
4258 }
4259}
4260
4261
4262
4263static void tx_stop( SLMP_INFO *info )
4264{
4265 if (debug_level >= DEBUG_LEVEL_ISR)
4266 printk("%s(%d):%s tx_stop()\n",
4267 __FILE__,__LINE__, info->device_name );
4268
4269 del_timer(&info->tx_timer);
4270
4271 write_reg(info, TXDMA + DSR, 0);
4272 write_reg(info, TXDMA + DCMD, SWABORT);
4273
4274 write_reg(info, CMD, TXRESET);
4275
4276 info->ie1_value &= ~(UDRN + IDLE);
4277 write_reg(info, IE1, info->ie1_value);
4278 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4279
4280 info->ie0_value &= ~TXRDYE;
4281 write_reg(info, IE0, info->ie0_value);
4282
4283 info->tx_enabled = false;
4284 info->tx_active = false;
4285}
4286
4287
4288
4289
4290static void tx_load_fifo(SLMP_INFO *info)
4291{
4292 u8 TwoBytes[2];
4293
4294
4295
4296 if ( !info->tx_count && !info->x_char )
4297 return;
4298
4299
4300
4301 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4302
4303
4304
4305
4306 if ( (info->tx_count > 1) && !info->x_char ) {
4307
4308 TwoBytes[0] = info->tx_buf[info->tx_get++];
4309 if (info->tx_get >= info->max_frame_size)
4310 info->tx_get -= info->max_frame_size;
4311 TwoBytes[1] = info->tx_buf[info->tx_get++];
4312 if (info->tx_get >= info->max_frame_size)
4313 info->tx_get -= info->max_frame_size;
4314
4315 write_reg16(info, TRB, *((u16 *)TwoBytes));
4316
4317 info->tx_count -= 2;
4318 info->icount.tx += 2;
4319 } else {
4320
4321
4322 if (info->x_char) {
4323
4324 write_reg(info, TRB, info->x_char);
4325 info->x_char = 0;
4326 } else {
4327 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4328 if (info->tx_get >= info->max_frame_size)
4329 info->tx_get -= info->max_frame_size;
4330 info->tx_count--;
4331 }
4332 info->icount.tx++;
4333 }
4334 }
4335}
4336
4337
4338
4339static void reset_port(SLMP_INFO *info)
4340{
4341 if (info->sca_base) {
4342
4343 tx_stop(info);
4344 rx_stop(info);
4345
4346 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4347 set_signals(info);
4348
4349
4350 info->ie0_value = 0;
4351 info->ie1_value = 0;
4352 info->ie2_value = 0;
4353 write_reg(info, IE0, info->ie0_value);
4354 write_reg(info, IE1, info->ie1_value);
4355 write_reg(info, IE2, info->ie2_value);
4356
4357 write_reg(info, CMD, CHRESET);
4358 }
4359}
4360
4361
4362
4363static void reset_adapter(SLMP_INFO *info)
4364{
4365 int i;
4366
4367 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4368 if (info->port_array[i])
4369 reset_port(info->port_array[i]);
4370 }
4371}
4372
4373
4374
4375static void async_mode(SLMP_INFO *info)
4376{
4377
4378 unsigned char RegValue;
4379
4380 tx_stop(info);
4381 rx_stop(info);
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393 RegValue = 0x00;
4394 if (info->params.stop_bits != 1)
4395 RegValue |= BIT1;
4396 write_reg(info, MD0, RegValue);
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407 RegValue = 0x40;
4408 switch (info->params.data_bits) {
4409 case 7: RegValue |= BIT4 + BIT2; break;
4410 case 6: RegValue |= BIT5 + BIT3; break;
4411 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4412 }
4413 if (info->params.parity != ASYNC_PARITY_NONE) {
4414 RegValue |= BIT1;
4415 if (info->params.parity == ASYNC_PARITY_ODD)
4416 RegValue |= BIT0;
4417 }
4418 write_reg(info, MD1, RegValue);
4419
4420
4421
4422
4423
4424
4425
4426
4427 RegValue = 0x00;
4428 if (info->params.loopback)
4429 RegValue |= (BIT1 + BIT0);
4430 write_reg(info, MD2, RegValue);
4431
4432
4433
4434
4435
4436
4437
4438 RegValue=BIT6;
4439 write_reg(info, RXS, RegValue);
4440
4441
4442
4443
4444
4445
4446
4447 RegValue=BIT6;
4448 write_reg(info, TXS, RegValue);
4449
4450
4451
4452
4453
4454 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4455 write_control_reg(info);
4456
4457 tx_set_idle(info);
4458
4459
4460
4461
4462
4463
4464 write_reg(info, RRC, 0x00);
4465
4466
4467
4468
4469
4470
4471 write_reg(info, TRC0, 0x10);
4472
4473
4474
4475
4476
4477
4478 write_reg(info, TRC1, 0x1e);
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492 RegValue = 0x10;
4493 if (!(info->serial_signals & SerialSignal_RTS))
4494 RegValue |= 0x01;
4495 write_reg(info, CTL, RegValue);
4496
4497
4498 info->ie0_value |= TXINTE + RXINTE;
4499 write_reg(info, IE0, info->ie0_value);
4500
4501
4502 info->ie1_value = BRKD;
4503 write_reg(info, IE1, info->ie1_value);
4504
4505
4506 info->ie2_value = OVRN;
4507 write_reg(info, IE2, info->ie2_value);
4508
4509 set_rate( info, info->params.data_rate * 16 );
4510}
4511
4512
4513
4514static void hdlc_mode(SLMP_INFO *info)
4515{
4516 unsigned char RegValue;
4517 u32 DpllDivisor;
4518
4519
4520
4521
4522
4523 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4524
4525
4526 write_reg(info, TXDMA + DIR, 0);
4527 write_reg(info, RXDMA + DIR, 0);
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540 RegValue = 0x81;
4541 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4542 RegValue |= BIT4;
4543 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4544 RegValue |= BIT4;
4545 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4546 RegValue |= BIT2 + BIT1;
4547 write_reg(info, MD0, RegValue);
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558 RegValue = 0x00;
4559 write_reg(info, MD1, RegValue);
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571 RegValue = 0x00;
4572 switch(info->params.encoding) {
4573 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4574 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break;
4575 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break;
4576 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;
4577#if 0
4578 case HDLC_ENCODING_NRZB:
4579 case HDLC_ENCODING_NRZI_MARK:
4580 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4581#endif
4582 }
4583 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4584 DpllDivisor = 16;
4585 RegValue |= BIT3;
4586 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4587 DpllDivisor = 8;
4588 } else {
4589 DpllDivisor = 32;
4590 RegValue |= BIT4;
4591 }
4592 write_reg(info, MD2, RegValue);
4593
4594
4595
4596
4597
4598
4599
4600
4601 RegValue=0;
4602 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4603 RegValue |= BIT6;
4604 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4605 RegValue |= BIT6 + BIT5;
4606 write_reg(info, RXS, RegValue);
4607
4608
4609
4610
4611
4612
4613
4614 RegValue=0;
4615 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4616 RegValue |= BIT6;
4617 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4618 RegValue |= BIT6 + BIT5;
4619 write_reg(info, TXS, RegValue);
4620
4621 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4622 set_rate(info, info->params.clock_speed * DpllDivisor);
4623 else
4624 set_rate(info, info->params.clock_speed);
4625
4626
4627
4628
4629
4630 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4631 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4632 else
4633 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4634 write_control_reg(info);
4635
4636
4637
4638
4639
4640
4641 write_reg(info, RRC, rx_active_fifo_level);
4642
4643
4644
4645
4646
4647
4648 write_reg(info, TRC0, tx_active_fifo_level);
4649
4650
4651
4652
4653
4654
4655 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668 write_reg(info, TXDMA + DMR, 0x14);
4669 write_reg(info, RXDMA + DMR, 0x14);
4670
4671
4672 write_reg(info, RXDMA + CPB,
4673 (unsigned char)(info->buffer_list_phys >> 16));
4674
4675
4676 write_reg(info, TXDMA + CPB,
4677 (unsigned char)(info->buffer_list_phys >> 16));
4678
4679
4680
4681
4682 info->ie0_value |= TXINTE + RXINTE;
4683 write_reg(info, IE0, info->ie0_value);
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697 RegValue = 0x10;
4698 if (!(info->serial_signals & SerialSignal_RTS))
4699 RegValue |= 0x01;
4700 write_reg(info, CTL, RegValue);
4701
4702
4703
4704 tx_set_idle(info);
4705 tx_stop(info);
4706 rx_stop(info);
4707
4708 set_rate(info, info->params.clock_speed);
4709
4710 if (info->params.loopback)
4711 enable_loopback(info,1);
4712}
4713
4714
4715
4716static void tx_set_idle(SLMP_INFO *info)
4717{
4718 unsigned char RegValue = 0xff;
4719
4720
4721 switch(info->idle_mode) {
4722 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4723 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4724 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4725 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4726 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4727 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4728 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4729 }
4730
4731 write_reg(info, IDL, RegValue);
4732}
4733
4734
4735
4736static void get_signals(SLMP_INFO *info)
4737{
4738 u16 status = read_reg(info, SR3);
4739 u16 gpstatus = read_status_reg(info);
4740 u16 testbit;
4741
4742
4743 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4744
4745
4746
4747 if (!(status & BIT3))
4748 info->serial_signals |= SerialSignal_CTS;
4749
4750 if ( !(status & BIT2))
4751 info->serial_signals |= SerialSignal_DCD;
4752
4753 testbit = BIT1 << (info->port_num * 2);
4754 if (!(gpstatus & testbit))
4755 info->serial_signals |= SerialSignal_RI;
4756
4757 testbit = BIT0 << (info->port_num * 2);
4758 if (!(gpstatus & testbit))
4759 info->serial_signals |= SerialSignal_DSR;
4760}
4761
4762
4763
4764
4765static void set_signals(SLMP_INFO *info)
4766{
4767 unsigned char RegValue;
4768 u16 EnableBit;
4769
4770 RegValue = read_reg(info, CTL);
4771 if (info->serial_signals & SerialSignal_RTS)
4772 RegValue &= ~BIT0;
4773 else
4774 RegValue |= BIT0;
4775 write_reg(info, CTL, RegValue);
4776
4777
4778 EnableBit = BIT1 << (info->port_num*2);
4779 if (info->serial_signals & SerialSignal_DTR)
4780 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4781 else
4782 info->port_array[0]->ctrlreg_value |= EnableBit;
4783 write_control_reg(info);
4784}
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794static void rx_reset_buffers(SLMP_INFO *info)
4795{
4796 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4797}
4798
4799
4800
4801
4802
4803
4804
4805static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4806{
4807 bool done = false;
4808
4809 while(!done) {
4810
4811 info->rx_buf_list[first].status = 0xff;
4812
4813 if (first == last) {
4814 done = true;
4815
4816 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4817 }
4818
4819 first++;
4820 if (first == info->rx_buf_count)
4821 first = 0;
4822 }
4823
4824
4825 info->current_rx_buf = first;
4826}
4827
4828
4829
4830
4831
4832
4833static bool rx_get_frame(SLMP_INFO *info)
4834{
4835 unsigned int StartIndex, EndIndex;
4836 unsigned short status;
4837 unsigned int framesize = 0;
4838 bool ReturnCode = false;
4839 unsigned long flags;
4840 struct tty_struct *tty = info->port.tty;
4841 unsigned char addr_field = 0xff;
4842 SCADESC *desc;
4843 SCADESC_EX *desc_ex;
4844
4845CheckAgain:
4846
4847 framesize = 0;
4848 addr_field = 0xff;
4849
4850
4851
4852
4853
4854
4855
4856 StartIndex = EndIndex = info->current_rx_buf;
4857
4858 for ( ;; ) {
4859 desc = &info->rx_buf_list[EndIndex];
4860 desc_ex = &info->rx_buf_list_ex[EndIndex];
4861
4862 if (desc->status == 0xff)
4863 goto Cleanup;
4864
4865 if (framesize == 0 && info->params.addr_filter != 0xff)
4866 addr_field = desc_ex->virt_addr[0];
4867
4868 framesize += desc->length;
4869
4870
4871 if (desc->status)
4872 break;
4873
4874 EndIndex++;
4875 if (EndIndex == info->rx_buf_count)
4876 EndIndex = 0;
4877
4878 if (EndIndex == info->current_rx_buf) {
4879
4880
4881 if ( info->rx_enabled ){
4882 spin_lock_irqsave(&info->lock,flags);
4883 rx_start(info);
4884 spin_unlock_irqrestore(&info->lock,flags);
4885 }
4886 goto Cleanup;
4887 }
4888
4889 }
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903 status = desc->status;
4904
4905
4906
4907 if (info->params.crc_type == HDLC_CRC_NONE)
4908 status &= ~BIT2;
4909
4910 if (framesize == 0 ||
4911 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4912
4913
4914
4915 rx_free_frame_buffers(info, StartIndex, EndIndex);
4916 goto CheckAgain;
4917 }
4918
4919 if (framesize < 2)
4920 status |= BIT6;
4921
4922 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4923
4924
4925
4926 if (status & BIT6)
4927 info->icount.rxshort++;
4928 else if (status & BIT5)
4929 info->icount.rxabort++;
4930 else if (status & BIT3)
4931 info->icount.rxover++;
4932 else
4933 info->icount.rxcrc++;
4934
4935 framesize = 0;
4936#if SYNCLINK_GENERIC_HDLC
4937 {
4938 info->netdev->stats.rx_errors++;
4939 info->netdev->stats.rx_frame_errors++;
4940 }
4941#endif
4942 }
4943
4944 if ( debug_level >= DEBUG_LEVEL_BH )
4945 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4946 __FILE__,__LINE__,info->device_name,status,framesize);
4947
4948 if ( debug_level >= DEBUG_LEVEL_DATA )
4949 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4950 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4951
4952 if (framesize) {
4953 if (framesize > info->max_frame_size)
4954 info->icount.rxlong++;
4955 else {
4956
4957 int copy_count = framesize;
4958 int index = StartIndex;
4959 unsigned char *ptmp = info->tmp_rx_buf;
4960 info->tmp_rx_buf_count = framesize;
4961
4962 info->icount.rxok++;
4963
4964 while(copy_count) {
4965 int partial_count = min(copy_count,SCABUFSIZE);
4966 memcpy( ptmp,
4967 info->rx_buf_list_ex[index].virt_addr,
4968 partial_count );
4969 ptmp += partial_count;
4970 copy_count -= partial_count;
4971
4972 if ( ++index == info->rx_buf_count )
4973 index = 0;
4974 }
4975
4976#if SYNCLINK_GENERIC_HDLC
4977 if (info->netcount)
4978 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4979 else
4980#endif
4981 ldisc_receive_buf(tty,info->tmp_rx_buf,
4982 info->flag_buf, framesize);
4983 }
4984 }
4985
4986 rx_free_frame_buffers( info, StartIndex, EndIndex );
4987
4988 ReturnCode = true;
4989
4990Cleanup:
4991 if ( info->rx_enabled && info->rx_overflow ) {
4992
4993
4994
4995 if (info->rx_buf_list[EndIndex].status == 0xff) {
4996 spin_lock_irqsave(&info->lock,flags);
4997 rx_start(info);
4998 spin_unlock_irqrestore(&info->lock,flags);
4999 }
5000 }
5001
5002 return ReturnCode;
5003}
5004
5005
5006
5007static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5008{
5009 unsigned short copy_count;
5010 unsigned int i = 0;
5011 SCADESC *desc;
5012 SCADESC_EX *desc_ex;
5013
5014 if ( debug_level >= DEBUG_LEVEL_DATA )
5015 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5016
5017
5018
5019
5020 for(i=0;;)
5021 {
5022 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5023
5024 desc = &info->tx_buf_list[i];
5025 desc_ex = &info->tx_buf_list_ex[i];
5026
5027 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5028
5029 desc->length = copy_count;
5030 desc->status = 0;
5031
5032 buf += copy_count;
5033 count -= copy_count;
5034
5035 if (!count)
5036 break;
5037
5038 i++;
5039 if (i >= info->tx_buf_count)
5040 i = 0;
5041 }
5042
5043 info->tx_buf_list[i].status = 0x81;
5044 info->last_tx_buf = ++i;
5045}
5046
5047static bool register_test(SLMP_INFO *info)
5048{
5049 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5050 static unsigned int count = ARRAY_SIZE(testval);
5051 unsigned int i;
5052 bool rc = true;
5053 unsigned long flags;
5054
5055 spin_lock_irqsave(&info->lock,flags);
5056 reset_port(info);
5057
5058
5059 info->init_error = DiagStatus_AddressFailure;
5060
5061
5062
5063
5064 for (i = 0 ; i < count ; i++) {
5065 write_reg(info, TMC, testval[i]);
5066 write_reg(info, IDL, testval[(i+1)%count]);
5067 write_reg(info, SA0, testval[(i+2)%count]);
5068 write_reg(info, SA1, testval[(i+3)%count]);
5069
5070 if ( (read_reg(info, TMC) != testval[i]) ||
5071 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5072 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5073 (read_reg(info, SA1) != testval[(i+3)%count]) )
5074 {
5075 rc = false;
5076 break;
5077 }
5078 }
5079
5080 reset_port(info);
5081 spin_unlock_irqrestore(&info->lock,flags);
5082
5083 return rc;
5084}
5085
5086static bool irq_test(SLMP_INFO *info)
5087{
5088 unsigned long timeout;
5089 unsigned long flags;
5090
5091 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5092
5093 spin_lock_irqsave(&info->lock,flags);
5094 reset_port(info);
5095
5096
5097 info->init_error = DiagStatus_IrqFailure;
5098 info->irq_occurred = false;
5099
5100
5101
5102
5103 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5104
5105 write_reg(info, (unsigned char)(timer + TEPR), 0);
5106 write_reg16(info, (unsigned char)(timer + TCONR), 1);
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5120
5121 spin_unlock_irqrestore(&info->lock,flags);
5122
5123 timeout=100;
5124 while( timeout-- && !info->irq_occurred ) {
5125 msleep_interruptible(10);
5126 }
5127
5128 spin_lock_irqsave(&info->lock,flags);
5129 reset_port(info);
5130 spin_unlock_irqrestore(&info->lock,flags);
5131
5132 return info->irq_occurred;
5133}
5134
5135
5136
5137static bool sca_init(SLMP_INFO *info)
5138{
5139
5140 write_reg(info, PABR0, 0);
5141 write_reg(info, PABR1, 0);
5142 write_reg(info, WCRL, 0);
5143 write_reg(info, WCRM, 0);
5144 write_reg(info, WCRH, 0);
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155 write_reg(info, DPCR, dma_priority);
5156
5157
5158 write_reg(info, DMER, 0x80);
5159
5160
5161 write_reg(info, IER0, 0xff);
5162 write_reg(info, IER1, 0xff);
5163 write_reg(info, IER2, 0xf0);
5164
5165
5166
5167
5168
5169
5170
5171 write_reg(info, ITCR, 0);
5172
5173 return true;
5174}
5175
5176
5177
5178static bool init_adapter(SLMP_INFO *info)
5179{
5180 int i;
5181
5182
5183 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5184 u32 readval;
5185
5186 info->misc_ctrl_value |= BIT30;
5187 *MiscCtrl = info->misc_ctrl_value;
5188
5189
5190
5191
5192
5193
5194 for(i=0;i<10;i++)
5195 readval = *MiscCtrl;
5196
5197 info->misc_ctrl_value &= ~BIT30;
5198 *MiscCtrl = info->misc_ctrl_value;
5199
5200
5201 info->ctrlreg_value = 0xaa;
5202 write_control_reg(info);
5203
5204 {
5205 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5206 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5207
5208 switch(read_ahead_count)
5209 {
5210 case 16:
5211 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5212 break;
5213 case 8:
5214 lcr1_brdr_value |= BIT5 + BIT4;
5215 break;
5216 case 4:
5217 lcr1_brdr_value |= BIT5 + BIT3;
5218 break;
5219 case 0:
5220 lcr1_brdr_value |= BIT5;
5221 break;
5222 }
5223
5224 *LCR1BRDR = lcr1_brdr_value;
5225 *MiscCtrl = misc_ctrl_value;
5226 }
5227
5228 sca_init(info->port_array[0]);
5229 sca_init(info->port_array[2]);
5230
5231 return true;
5232}
5233
5234
5235
5236
5237static bool loopback_test(SLMP_INFO *info)
5238{
5239#define TESTFRAMESIZE 20
5240
5241 unsigned long timeout;
5242 u16 count = TESTFRAMESIZE;
5243 unsigned char buf[TESTFRAMESIZE];
5244 bool rc = false;
5245 unsigned long flags;
5246
5247 struct tty_struct *oldtty = info->port.tty;
5248 u32 speed = info->params.clock_speed;
5249
5250 info->params.clock_speed = 3686400;
5251 info->port.tty = NULL;
5252
5253
5254 info->init_error = DiagStatus_DmaFailure;
5255
5256
5257 for (count = 0; count < TESTFRAMESIZE;++count)
5258 buf[count] = (unsigned char)count;
5259
5260 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5261
5262
5263 spin_lock_irqsave(&info->lock,flags);
5264 hdlc_mode(info);
5265 enable_loopback(info,1);
5266 rx_start(info);
5267 info->tx_count = count;
5268 tx_load_dma_buffer(info,buf,count);
5269 tx_start(info);
5270 spin_unlock_irqrestore(&info->lock,flags);
5271
5272
5273
5274 for ( timeout = 100; timeout; --timeout ) {
5275 msleep_interruptible(10);
5276
5277 if (rx_get_frame(info)) {
5278 rc = true;
5279 break;
5280 }
5281 }
5282
5283
5284 if (rc &&
5285 ( info->tmp_rx_buf_count != count ||
5286 memcmp(buf, info->tmp_rx_buf,count))) {
5287 rc = false;
5288 }
5289
5290 spin_lock_irqsave(&info->lock,flags);
5291 reset_adapter(info);
5292 spin_unlock_irqrestore(&info->lock,flags);
5293
5294 info->params.clock_speed = speed;
5295 info->port.tty = oldtty;
5296
5297 return rc;
5298}
5299
5300
5301
5302static int adapter_test( SLMP_INFO *info )
5303{
5304 unsigned long flags;
5305 if ( debug_level >= DEBUG_LEVEL_INFO )
5306 printk( "%s(%d):Testing device %s\n",
5307 __FILE__,__LINE__,info->device_name );
5308
5309 spin_lock_irqsave(&info->lock,flags);
5310 init_adapter(info);
5311 spin_unlock_irqrestore(&info->lock,flags);
5312
5313 info->port_array[0]->port_count = 0;
5314
5315 if ( register_test(info->port_array[0]) &&
5316 register_test(info->port_array[1])) {
5317
5318 info->port_array[0]->port_count = 2;
5319
5320 if ( register_test(info->port_array[2]) &&
5321 register_test(info->port_array[3]) )
5322 info->port_array[0]->port_count += 2;
5323 }
5324 else {
5325 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5326 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5327 return -ENODEV;
5328 }
5329
5330 if ( !irq_test(info->port_array[0]) ||
5331 !irq_test(info->port_array[1]) ||
5332 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5333 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5334 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5335 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5336 return -ENODEV;
5337 }
5338
5339 if (!loopback_test(info->port_array[0]) ||
5340 !loopback_test(info->port_array[1]) ||
5341 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5342 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5343 printk( "%s(%d):DMA test failure for device %s\n",
5344 __FILE__,__LINE__,info->device_name);
5345 return -ENODEV;
5346 }
5347
5348 if ( debug_level >= DEBUG_LEVEL_INFO )
5349 printk( "%s(%d):device %s passed diagnostics\n",
5350 __FILE__,__LINE__,info->device_name );
5351
5352 info->port_array[0]->init_error = 0;
5353 info->port_array[1]->init_error = 0;
5354 if ( info->port_count > 2 ) {
5355 info->port_array[2]->init_error = 0;
5356 info->port_array[3]->init_error = 0;
5357 }
5358
5359 return 0;
5360}
5361
5362
5363
5364static bool memory_test(SLMP_INFO *info)
5365{
5366 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5367 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5368 unsigned long count = ARRAY_SIZE(testval);
5369 unsigned long i;
5370 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5371 unsigned long * addr = (unsigned long *)info->memory_base;
5372
5373
5374
5375 for ( i = 0 ; i < count ; i++ ) {
5376 *addr = testval[i];
5377 if ( *addr != testval[i] )
5378 return false;
5379 }
5380
5381
5382
5383
5384 for ( i = 0 ; i < limit ; i++ ) {
5385 *addr = i * 4;
5386 addr++;
5387 }
5388
5389 addr = (unsigned long *)info->memory_base;
5390
5391 for ( i = 0 ; i < limit ; i++ ) {
5392 if ( *addr != i * 4 )
5393 return false;
5394 addr++;
5395 }
5396
5397 memset( info->memory_base, 0, SCA_MEM_SIZE );
5398 return true;
5399}
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5417{
5418
5419
5420
5421 unsigned short interval = count / sca_pci_load_interval;
5422 unsigned short i;
5423
5424 for ( i = 0 ; i < interval ; i++ )
5425 {
5426 memcpy(dest, src, sca_pci_load_interval);
5427 read_status_reg(info);
5428 dest += sca_pci_load_interval;
5429 src += sca_pci_load_interval;
5430 }
5431
5432 memcpy(dest, src, count % sca_pci_load_interval);
5433}
5434
5435static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5436{
5437 int i;
5438 int linecount;
5439 if (xmit)
5440 printk("%s tx data:\n",info->device_name);
5441 else
5442 printk("%s rx data:\n",info->device_name);
5443
5444 while(count) {
5445 if (count > 16)
5446 linecount = 16;
5447 else
5448 linecount = count;
5449
5450 for(i=0;i<linecount;i++)
5451 printk("%02X ",(unsigned char)data[i]);
5452 for(;i<17;i++)
5453 printk(" ");
5454 for(i=0;i<linecount;i++) {
5455 if (data[i]>=040 && data[i]<=0176)
5456 printk("%c",data[i]);
5457 else
5458 printk(".");
5459 }
5460 printk("\n");
5461
5462 data += linecount;
5463 count -= linecount;
5464 }
5465}
5466
5467
5468
5469
5470static void tx_timeout(struct timer_list *t)
5471{
5472 SLMP_INFO *info = from_timer(info, t, tx_timer);
5473 unsigned long flags;
5474
5475 if ( debug_level >= DEBUG_LEVEL_INFO )
5476 printk( "%s(%d):%s tx_timeout()\n",
5477 __FILE__,__LINE__,info->device_name);
5478 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5479 info->icount.txtimeout++;
5480 }
5481 spin_lock_irqsave(&info->lock,flags);
5482 info->tx_active = false;
5483 info->tx_count = info->tx_put = info->tx_get = 0;
5484
5485 spin_unlock_irqrestore(&info->lock,flags);
5486
5487#if SYNCLINK_GENERIC_HDLC
5488 if (info->netcount)
5489 hdlcdev_tx_done(info);
5490 else
5491#endif
5492 bh_transmit(info);
5493}
5494
5495
5496
5497static void status_timeout(struct timer_list *t)
5498{
5499 u16 status = 0;
5500 SLMP_INFO *info = from_timer(info, t, status_timer);
5501 unsigned long flags;
5502 unsigned char delta;
5503
5504
5505 spin_lock_irqsave(&info->lock,flags);
5506 get_signals(info);
5507 spin_unlock_irqrestore(&info->lock,flags);
5508
5509
5510
5511 delta = info->old_signals ^ info->serial_signals;
5512 info->old_signals = info->serial_signals;
5513
5514 if (delta & SerialSignal_DSR)
5515 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5516
5517 if (delta & SerialSignal_RI)
5518 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5519
5520 if (delta & SerialSignal_DCD)
5521 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5522
5523 if (delta & SerialSignal_CTS)
5524 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5525
5526 if (status)
5527 isr_io_pin(info,status);
5528
5529 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5530}
5531
5532
5533
5534
5535
5536#define CALC_REGADDR() \
5537 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5538 if (info->port_num > 1) \
5539 RegAddr += 256; \
5540 if ( info->port_num & 1) { \
5541 if (Addr > 0x7f) \
5542 RegAddr += 0x40; \
5543 else if (Addr > 0x1f && Addr < 0x60) \
5544 RegAddr += 0x20; \
5545 }
5546
5547
5548static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5549{
5550 CALC_REGADDR();
5551 return *RegAddr;
5552}
5553static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5554{
5555 CALC_REGADDR();
5556 *RegAddr = Value;
5557}
5558
5559static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5560{
5561 CALC_REGADDR();
5562 return *((u16 *)RegAddr);
5563}
5564
5565static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5566{
5567 CALC_REGADDR();
5568 *((u16 *)RegAddr) = Value;
5569}
5570
5571static unsigned char read_status_reg(SLMP_INFO * info)
5572{
5573 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5574 return *RegAddr;
5575}
5576
5577static void write_control_reg(SLMP_INFO * info)
5578{
5579 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5580 *RegAddr = info->port_array[0]->ctrlreg_value;
5581}
5582
5583
5584static int synclinkmp_init_one (struct pci_dev *dev,
5585 const struct pci_device_id *ent)
5586{
5587 if (pci_enable_device(dev)) {
5588 printk("error enabling pci device %p\n", dev);
5589 return -EIO;
5590 }
5591 return device_init( ++synclinkmp_adapter_count, dev );
5592}
5593
5594static void synclinkmp_remove_one (struct pci_dev *dev)
5595{
5596}
5597