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16typedef __u32 __bitwise __hc32;
17typedef __u16 __bitwise __hc16;
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25
26struct ed {
27
28 __hc32 hwINFO;
29
30#define ED_DEQUEUE (1 << 27)
31
32#define ED_ISO (1 << 15)
33#define ED_SKIP (1 << 14)
34#define ED_LOWSPEED (1 << 13)
35#define ED_OUT (0x01 << 11)
36#define ED_IN (0x02 << 11)
37 __hc32 hwTailP;
38 __hc32 hwHeadP;
39#define ED_C (0x02)
40#define ED_H (0x01)
41 __hc32 hwNextED;
42
43
44 dma_addr_t dma;
45 struct td *dummy;
46
47
48 struct ed *ed_next;
49 struct ed *ed_prev;
50 struct list_head td_list;
51 struct list_head in_use_list;
52
53
54
55
56 u8 state;
57#define ED_IDLE 0x00
58#define ED_UNLINK 0x01
59#define ED_OPER 0x02
60
61 u8 type;
62
63
64 u8 branch;
65 u16 interval;
66 u16 load;
67 u16 last_iso;
68
69
70 u16 tick;
71
72
73 unsigned takeback_wdh_cnt;
74 struct td *pending_td;
75#define OKAY_TO_TAKEBACK(ohci, ed) \
76 ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0)
77
78} __attribute__ ((aligned(16)));
79
80#define ED_MASK ((u32)~0x0f)
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86
87
88struct td {
89
90 __hc32 hwINFO;
91
92
93#define TD_CC 0xf0000000
94#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
95
96#define TD_DI 0x00E00000
97#define TD_DI_SET(X) (((X) & 0x07)<< 21)
98
99
100
101#define TD_DONE 0x00020000
102#define TD_ISO 0x00010000
103
104
105#define TD_EC 0x0C000000
106#define TD_T 0x03000000
107#define TD_T_DATA0 0x02000000
108#define TD_T_DATA1 0x03000000
109#define TD_T_TOGGLE 0x00000000
110#define TD_DP 0x00180000
111#define TD_DP_SETUP 0x00000000
112#define TD_DP_IN 0x00100000
113#define TD_DP_OUT 0x00080000
114
115#define TD_R 0x00040000
116
117
118
119 __hc32 hwCBP;
120 __hc32 hwNextTD;
121 __hc32 hwBE;
122
123
124
125
126#define MAXPSW 2
127 __hc16 hwPSW [MAXPSW];
128
129
130 __u8 index;
131 struct ed *ed;
132 struct td *td_hash;
133 struct td *next_dl_td;
134 struct urb *urb;
135
136 dma_addr_t td_dma;
137 dma_addr_t data_dma;
138
139 struct list_head td_list;
140} __attribute__ ((aligned(32)));
141
142#define TD_MASK ((u32)~0x1f)
143
144
145
146
147#define TD_CC_NOERROR 0x00
148#define TD_CC_CRC 0x01
149#define TD_CC_BITSTUFFING 0x02
150#define TD_CC_DATATOGGLEM 0x03
151#define TD_CC_STALL 0x04
152#define TD_DEVNOTRESP 0x05
153#define TD_PIDCHECKFAIL 0x06
154#define TD_UNEXPECTEDPID 0x07
155#define TD_DATAOVERRUN 0x08
156#define TD_DATAUNDERRUN 0x09
157
158#define TD_BUFFEROVERRUN 0x0C
159#define TD_BUFFERUNDERRUN 0x0D
160
161#define TD_NOTACCESSED 0x0F
162
163
164
165static const int cc_to_error [16] = {
166 0,
167 -EILSEQ,
168 -EPROTO,
169 -EILSEQ,
170 -EPIPE,
171 -ETIME,
172 -EPROTO,
173 -EPROTO,
174 -EOVERFLOW,
175 -EREMOTEIO,
176 -EIO,
177 -EIO,
178 -ECOMM,
179 -ENOSR,
180 -EALREADY,
181 -EALREADY
182};
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189
190struct ohci_hcca {
191#define NUM_INTS 32
192 __hc32 int_table [NUM_INTS];
193
194
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196
197
198
199 __hc32 frame_no;
200 __hc32 done_head;
201 u8 reserved_for_hc [116];
202 u8 what [4];
203} __attribute__ ((aligned(256)));
204
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208
209
210struct ohci_regs {
211
212 __hc32 revision;
213 __hc32 control;
214 __hc32 cmdstatus;
215 __hc32 intrstatus;
216 __hc32 intrenable;
217 __hc32 intrdisable;
218
219
220 __hc32 hcca;
221 __hc32 ed_periodcurrent;
222 __hc32 ed_controlhead;
223 __hc32 ed_controlcurrent;
224 __hc32 ed_bulkhead;
225 __hc32 ed_bulkcurrent;
226 __hc32 donehead;
227
228
229 __hc32 fminterval;
230 __hc32 fmremaining;
231 __hc32 fmnumber;
232 __hc32 periodicstart;
233 __hc32 lsthresh;
234
235
236 struct ohci_roothub_regs {
237 __hc32 a;
238 __hc32 b;
239 __hc32 status;
240#define MAX_ROOT_PORTS 15
241 __hc32 portstatus [MAX_ROOT_PORTS];
242 } roothub;
243
244
245
246} __attribute__ ((aligned(32)));
247
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253
254#define OHCI_CTRL_CBSR (3 << 0)
255#define OHCI_CTRL_PLE (1 << 2)
256#define OHCI_CTRL_IE (1 << 3)
257#define OHCI_CTRL_CLE (1 << 4)
258#define OHCI_CTRL_BLE (1 << 5)
259#define OHCI_CTRL_HCFS (3 << 6)
260#define OHCI_CTRL_IR (1 << 8)
261#define OHCI_CTRL_RWC (1 << 9)
262#define OHCI_CTRL_RWE (1 << 10)
263
264
265# define OHCI_USB_RESET (0 << 6)
266# define OHCI_USB_RESUME (1 << 6)
267# define OHCI_USB_OPER (2 << 6)
268# define OHCI_USB_SUSPEND (3 << 6)
269
270
271
272
273#define OHCI_HCR (1 << 0)
274#define OHCI_CLF (1 << 1)
275#define OHCI_BLF (1 << 2)
276#define OHCI_OCR (1 << 3)
277#define OHCI_SOC (3 << 16)
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283
284
285#define OHCI_INTR_SO (1 << 0)
286#define OHCI_INTR_WDH (1 << 1)
287#define OHCI_INTR_SF (1 << 2)
288#define OHCI_INTR_RD (1 << 3)
289#define OHCI_INTR_UE (1 << 4)
290#define OHCI_INTR_FNO (1 << 5)
291#define OHCI_INTR_RHSC (1 << 6)
292#define OHCI_INTR_OC (1 << 30)
293#define OHCI_INTR_MIE (1 << 31)
294
295
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297
298
299#define RH_PS_CCS 0x00000001
300#define RH_PS_PES 0x00000002
301#define RH_PS_PSS 0x00000004
302#define RH_PS_POCI 0x00000008
303#define RH_PS_PRS 0x00000010
304#define RH_PS_PPS 0x00000100
305#define RH_PS_LSDA 0x00000200
306#define RH_PS_CSC 0x00010000
307#define RH_PS_PESC 0x00020000
308#define RH_PS_PSSC 0x00040000
309#define RH_PS_OCIC 0x00080000
310#define RH_PS_PRSC 0x00100000
311
312
313#define RH_HS_LPS 0x00000001
314#define RH_HS_OCI 0x00000002
315#define RH_HS_DRWE 0x00008000
316#define RH_HS_LPSC 0x00010000
317#define RH_HS_OCIC 0x00020000
318#define RH_HS_CRWE 0x80000000
319
320
321#define RH_B_DR 0x0000ffff
322#define RH_B_PPCM 0xffff0000
323
324
325#define RH_A_NDP (0xff << 0)
326#define RH_A_PSM (1 << 8)
327#define RH_A_NPS (1 << 9)
328#define RH_A_DT (1 << 10)
329#define RH_A_OCPM (1 << 11)
330#define RH_A_NOCP (1 << 12)
331#define RH_A_POTPGT (0xff << 24)
332
333
334
335typedef struct urb_priv {
336 struct ed *ed;
337 u16 length;
338 u16 td_cnt;
339 struct list_head pending;
340 struct td *td [0];
341
342} urb_priv_t;
343
344#define TD_HASH_SIZE 64
345
346#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
347
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355
356enum ohci_rh_state {
357 OHCI_RH_HALTED,
358 OHCI_RH_SUSPENDED,
359 OHCI_RH_RUNNING
360};
361
362struct ohci_hcd {
363 spinlock_t lock;
364
365
366
367
368 struct ohci_regs __iomem *regs;
369
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374
375 struct ohci_hcca *hcca;
376 dma_addr_t hcca_dma;
377
378 struct ed *ed_rm_list;
379
380 struct ed *ed_bulktail;
381 struct ed *ed_controltail;
382 struct ed *periodic [NUM_INTS];
383
384 void (*start_hnp)(struct ohci_hcd *ohci);
385
386
387
388
389 struct dma_pool *td_cache;
390 struct dma_pool *ed_cache;
391 struct td *td_hash [TD_HASH_SIZE];
392 struct td *dl_start, *dl_end;
393 struct list_head pending;
394 struct list_head eds_in_use;
395
396
397
398
399 enum ohci_rh_state rh_state;
400 int num_ports;
401 int load [NUM_INTS];
402 u32 hc_control;
403 unsigned long next_statechange;
404 u32 fminterval;
405 unsigned autostop:1;
406 unsigned working:1;
407 unsigned restart_work:1;
408
409 unsigned long flags;
410#define OHCI_QUIRK_AMD756 0x01
411#define OHCI_QUIRK_SUPERIO 0x02
412#define OHCI_QUIRK_INITRESET 0x04
413#define OHCI_QUIRK_BE_DESC 0x08
414#define OHCI_QUIRK_BE_MMIO 0x10
415#define OHCI_QUIRK_ZFMICRO 0x20
416#define OHCI_QUIRK_NEC 0x40
417#define OHCI_QUIRK_FRAME_NO 0x80
418#define OHCI_QUIRK_HUB_POWER 0x100
419#define OHCI_QUIRK_AMD_PLL 0x200
420#define OHCI_QUIRK_AMD_PREFETCH 0x400
421#define OHCI_QUIRK_GLOBAL_SUSPEND 0x800
422#define OHCI_QUIRK_QEMU 0x1000
423
424
425
426 unsigned prev_frame_no;
427 unsigned wdh_cnt, prev_wdh_cnt;
428 u32 prev_donehead;
429 struct timer_list io_watchdog;
430
431 struct work_struct nec_work;
432
433 struct dentry *debug_dir;
434 struct dentry *debug_async;
435 struct dentry *debug_periodic;
436 struct dentry *debug_registers;
437
438
439 unsigned long priv[0] __aligned(sizeof(s64));
440
441};
442
443#ifdef CONFIG_USB_PCI
444static inline int quirk_nec(struct ohci_hcd *ohci)
445{
446 return ohci->flags & OHCI_QUIRK_NEC;
447}
448static inline int quirk_zfmicro(struct ohci_hcd *ohci)
449{
450 return ohci->flags & OHCI_QUIRK_ZFMICRO;
451}
452static inline int quirk_amdiso(struct ohci_hcd *ohci)
453{
454 return ohci->flags & OHCI_QUIRK_AMD_PLL;
455}
456static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
457{
458 return ohci->flags & OHCI_QUIRK_AMD_PREFETCH;
459}
460#else
461static inline int quirk_nec(struct ohci_hcd *ohci)
462{
463 return 0;
464}
465static inline int quirk_zfmicro(struct ohci_hcd *ohci)
466{
467 return 0;
468}
469static inline int quirk_amdiso(struct ohci_hcd *ohci)
470{
471 return 0;
472}
473static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
474{
475 return 0;
476}
477#endif
478
479
480static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd)
481{
482 return (struct ohci_hcd *) (hcd->hcd_priv);
483}
484static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci)
485{
486 return container_of ((void *) ohci, struct usb_hcd, hcd_priv);
487}
488
489
490
491#define ohci_dbg(ohci, fmt, args...) \
492 dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
493#define ohci_err(ohci, fmt, args...) \
494 dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
495#define ohci_info(ohci, fmt, args...) \
496 dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
497#define ohci_warn(ohci, fmt, args...) \
498 dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
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537#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
538#ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
539#define big_endian_desc(ohci) (ohci->flags & OHCI_QUIRK_BE_DESC)
540#else
541#define big_endian_desc(ohci) 1
542#endif
543#else
544#define big_endian_desc(ohci) 0
545#endif
546
547#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
548#ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
549#define big_endian_mmio(ohci) (ohci->flags & OHCI_QUIRK_BE_MMIO)
550#else
551#define big_endian_mmio(ohci) 1
552#endif
553#else
554#define big_endian_mmio(ohci) 0
555#endif
556
557
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559
560
561
562static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
563 __hc32 __iomem * regs)
564{
565#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
566 return big_endian_mmio(ohci) ?
567 readl_be (regs) :
568 readl (regs);
569#else
570 return readl (regs);
571#endif
572}
573
574static inline void _ohci_writel (const struct ohci_hcd *ohci,
575 const unsigned int val, __hc32 __iomem *regs)
576{
577#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
578 big_endian_mmio(ohci) ?
579 writel_be (val, regs) :
580 writel (val, regs);
581#else
582 writel (val, regs);
583#endif
584}
585
586#define ohci_readl(o,r) _ohci_readl(o,r)
587#define ohci_writel(o,v,r) _ohci_writel(o,v,r)
588
589
590
591
592
593static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x)
594{
595 return big_endian_desc(ohci) ?
596 (__force __hc16)cpu_to_be16(x) :
597 (__force __hc16)cpu_to_le16(x);
598}
599
600static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x)
601{
602 return big_endian_desc(ohci) ?
603 cpu_to_be16p(x) :
604 cpu_to_le16p(x);
605}
606
607static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x)
608{
609 return big_endian_desc(ohci) ?
610 (__force __hc32)cpu_to_be32(x) :
611 (__force __hc32)cpu_to_le32(x);
612}
613
614static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x)
615{
616 return big_endian_desc(ohci) ?
617 cpu_to_be32p(x) :
618 cpu_to_le32p(x);
619}
620
621
622static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x)
623{
624 return big_endian_desc(ohci) ?
625 be16_to_cpu((__force __be16)x) :
626 le16_to_cpu((__force __le16)x);
627}
628
629static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x)
630{
631 return big_endian_desc(ohci) ?
632 be16_to_cpup((__force __be16 *)x) :
633 le16_to_cpup((__force __le16 *)x);
634}
635
636static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x)
637{
638 return big_endian_desc(ohci) ?
639 be32_to_cpu((__force __be32)x) :
640 le32_to_cpu((__force __le32)x);
641}
642
643static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
644{
645 return big_endian_desc(ohci) ?
646 be32_to_cpup((__force __be32 *)x) :
647 le32_to_cpup((__force __le32 *)x);
648}
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661
662static inline u16 ohci_frame_no(const struct ohci_hcd *ohci)
663{
664 u32 tmp;
665 if (big_endian_desc(ohci)) {
666 tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no);
667 if (!(ohci->flags & OHCI_QUIRK_FRAME_NO))
668 tmp >>= 16;
669 } else
670 tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no);
671
672 return (u16)tmp;
673}
674
675static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci,
676 const struct td *td, int index)
677{
678 return (__hc16 *)(big_endian_desc(ohci) ?
679 &td->hwPSW[index ^ 1] : &td->hwPSW[index]);
680}
681
682static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci,
683 const struct td *td, int index)
684{
685 return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index));
686}
687
688
689
690#define FI 0x2edf
691#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
692#define FIT (1 << 31)
693#define LSTHRESH 0x628
694
695static inline void periodic_reinit (struct ohci_hcd *ohci)
696{
697 u32 fi = ohci->fminterval & 0x03fff;
698 u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT;
699
700 ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval,
701 &ohci->regs->fminterval);
702 ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff,
703 &ohci->regs->periodicstart);
704}
705
706
707
708
709
710#define read_roothub(hc, register, mask) ({ \
711 u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \
712 if (temp == -1) \
713 hc->rh_state = OHCI_RH_HALTED; \
714 else if (hc->flags & OHCI_QUIRK_AMD756) \
715 while (temp & mask) \
716 temp = ohci_readl (hc, &hc->regs->roothub.register); \
717 temp; })
718
719static inline u32 roothub_a (struct ohci_hcd *hc)
720 { return read_roothub (hc, a, 0xfc0fe000); }
721static inline u32 roothub_b (struct ohci_hcd *hc)
722 { return ohci_readl (hc, &hc->regs->roothub.b); }
723static inline u32 roothub_status (struct ohci_hcd *hc)
724 { return ohci_readl (hc, &hc->regs->roothub.status); }
725static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
726 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
727
728
729
730struct ohci_driver_overrides {
731 const char *product_desc;
732 size_t extra_priv_size;
733 int (*reset)(struct usb_hcd *hcd);
734};
735
736extern void ohci_init_driver(struct hc_driver *drv,
737 const struct ohci_driver_overrides *over);
738extern int ohci_restart(struct ohci_hcd *ohci);
739extern int ohci_setup(struct usb_hcd *hcd);
740extern int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
741extern int ohci_resume(struct usb_hcd *hcd, bool hibernated);
742extern int ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
743 u16 wIndex, char *buf, u16 wLength);
744extern int ohci_hub_status_data(struct usb_hcd *hcd, char *buf);
745