1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Host interface registers 4 */ 5 6#define OXU_DEVICEID 0x00 7 #define OXU_REV_MASK 0xffff0000 8 #define OXU_REV_SHIFT 16 9 #define OXU_REV_2100 0x2100 10 #define OXU_BO_SHIFT 8 11 #define OXU_BO_MASK (0x3 << OXU_BO_SHIFT) 12 #define OXU_MAJ_REV_SHIFT 4 13 #define OXU_MAJ_REV_MASK (0xf << OXU_MAJ_REV_SHIFT) 14 #define OXU_MIN_REV_SHIFT 0 15 #define OXU_MIN_REV_MASK (0xf << OXU_MIN_REV_SHIFT) 16#define OXU_HOSTIFCONFIG 0x04 17#define OXU_SOFTRESET 0x08 18 #define OXU_SRESET (1 << 0) 19 20#define OXU_PIOBURSTREADCTRL 0x0C 21 22#define OXU_CHIPIRQSTATUS 0x10 23#define OXU_CHIPIRQEN_SET 0x14 24#define OXU_CHIPIRQEN_CLR 0x18 25 #define OXU_USBSPHLPWUI 0x00000080 26 #define OXU_USBOTGLPWUI 0x00000040 27 #define OXU_USBSPHI 0x00000002 28 #define OXU_USBOTGI 0x00000001 29 30#define OXU_CLKCTRL_SET 0x1C 31 #define OXU_SYSCLKEN 0x00000008 32 #define OXU_USBSPHCLKEN 0x00000002 33 #define OXU_USBOTGCLKEN 0x00000001 34 35#define OXU_ASO 0x68 36 #define OXU_SPHPOEN 0x00000100 37 #define OXU_OVRCCURPUPDEN 0x00000800 38 #define OXU_ASO_OP (1 << 10) 39 #define OXU_COMPARATOR 0x000004000 40 41#define OXU_USBMODE 0x1A8 42 #define OXU_VBPS 0x00000020 43 #define OXU_ES_LITTLE 0x00000000 44 #define OXU_CM_HOST_ONLY 0x00000003 45 46/* 47 * Proper EHCI structs & defines 48 */ 49 50/* Magic numbers that can affect system performance */ 51#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 52#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 53#define EHCI_TUNE_RL_TT 0 54#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 55#define EHCI_TUNE_MULT_TT 1 56#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 57 58struct oxu_hcd; 59 60/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 61 62/* Section 2.2 Host Controller Capability Registers */ 63struct ehci_caps { 64 /* these fields are specified as 8 and 16 bit registers, 65 * but some hosts can't perform 8 or 16 bit PCI accesses. 66 */ 67 u32 hc_capbase; 68#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 69#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 70 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 71#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 72#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 73#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 74#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 75#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 76#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 77#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 78 79 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 80#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 81#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 82#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 83#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 84#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 85#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 86 u8 portroute[8]; /* nibbles for routing - offset 0xC */ 87} __attribute__ ((packed)); 88 89 90/* Section 2.3 Host Controller Operational Registers */ 91struct ehci_regs { 92 /* USBCMD: offset 0x00 */ 93 u32 command; 94/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 95#define CMD_PARK (1<<11) /* enable "park" on async qh */ 96#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 97#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 98#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 99#define CMD_ASE (1<<5) /* async schedule enable */ 100#define CMD_PSE (1<<4) /* periodic schedule enable */ 101/* 3:2 is periodic frame list size */ 102#define CMD_RESET (1<<1) /* reset HC not bus */ 103#define CMD_RUN (1<<0) /* start/stop HC */ 104 105 /* USBSTS: offset 0x04 */ 106 u32 status; 107#define STS_ASS (1<<15) /* Async Schedule Status */ 108#define STS_PSS (1<<14) /* Periodic Schedule Status */ 109#define STS_RECL (1<<13) /* Reclamation */ 110#define STS_HALT (1<<12) /* Not running (any reason) */ 111/* some bits reserved */ 112 /* these STS_* flags are also intr_enable bits (USBINTR) */ 113#define STS_IAA (1<<5) /* Interrupted on async advance */ 114#define STS_FATAL (1<<4) /* such as some PCI access errors */ 115#define STS_FLR (1<<3) /* frame list rolled over */ 116#define STS_PCD (1<<2) /* port change detect */ 117#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 118#define STS_INT (1<<0) /* "normal" completion (short, ...) */ 119 120#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 121 122 /* USBINTR: offset 0x08 */ 123 u32 intr_enable; 124 125 /* FRINDEX: offset 0x0C */ 126 u32 frame_index; /* current microframe number */ 127 /* CTRLDSSEGMENT: offset 0x10 */ 128 u32 segment; /* address bits 63:32 if needed */ 129 /* PERIODICLISTBASE: offset 0x14 */ 130 u32 frame_list; /* points to periodic list */ 131 /* ASYNCLISTADDR: offset 0x18 */ 132 u32 async_next; /* address of next async queue head */ 133 134 u32 reserved[9]; 135 136 /* CONFIGFLAG: offset 0x40 */ 137 u32 configured_flag; 138#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 139 140 /* PORTSC: offset 0x44 */ 141 u32 port_status[0]; /* up to N_PORTS */ 142/* 31:23 reserved */ 143#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 144#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 145#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 146/* 19:16 for port testing */ 147#define PORT_LED_OFF (0<<14) 148#define PORT_LED_AMBER (1<<14) 149#define PORT_LED_GREEN (2<<14) 150#define PORT_LED_MASK (3<<14) 151#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 152#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 153#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ 154/* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 155/* 9 reserved */ 156#define PORT_RESET (1<<8) /* reset port */ 157#define PORT_SUSPEND (1<<7) /* suspend port */ 158#define PORT_RESUME (1<<6) /* resume it */ 159#define PORT_OCC (1<<5) /* over current change */ 160#define PORT_OC (1<<4) /* over current active */ 161#define PORT_PEC (1<<3) /* port enable change */ 162#define PORT_PE (1<<2) /* port enable */ 163#define PORT_CSC (1<<1) /* connect status change */ 164#define PORT_CONNECT (1<<0) /* device connected */ 165#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 166} __attribute__ ((packed)); 167 168/* Appendix C, Debug port ... intended for use with special "debug devices" 169 * that can help if there's no serial console. (nonstandard enumeration.) 170 */ 171struct ehci_dbg_port { 172 u32 control; 173#define DBGP_OWNER (1<<30) 174#define DBGP_ENABLED (1<<28) 175#define DBGP_DONE (1<<16) 176#define DBGP_INUSE (1<<10) 177#define DBGP_ERRCODE(x) (((x)>>7)&0x07) 178# define DBGP_ERR_BAD 1 179# define DBGP_ERR_SIGNAL 2 180#define DBGP_ERROR (1<<6) 181#define DBGP_GO (1<<5) 182#define DBGP_OUT (1<<4) 183#define DBGP_LEN(x) (((x)>>0)&0x0f) 184 u32 pids; 185#define DBGP_PID_GET(x) (((x)>>16)&0xff) 186#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok)) 187 u32 data03; 188 u32 data47; 189 u32 address; 190#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) 191} __attribute__ ((packed)); 192 193 194#define QTD_NEXT(dma) cpu_to_le32((u32)dma) 195 196/* 197 * EHCI Specification 0.95 Section 3.5 198 * QTD: describe data transfer components (buffer, direction, ...) 199 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 200 * 201 * These are associated only with "QH" (Queue Head) structures, 202 * used with control, bulk, and interrupt transfers. 203 */ 204struct ehci_qtd { 205 /* first part defined by EHCI spec */ 206 __le32 hw_next; /* see EHCI 3.5.1 */ 207 __le32 hw_alt_next; /* see EHCI 3.5.2 */ 208 __le32 hw_token; /* see EHCI 3.5.3 */ 209#define QTD_TOGGLE (1 << 31) /* data toggle */ 210#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 211#define QTD_IOC (1 << 15) /* interrupt on complete */ 212#define QTD_CERR(tok) (((tok)>>10) & 0x3) 213#define QTD_PID(tok) (((tok)>>8) & 0x3) 214#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 215#define QTD_STS_HALT (1 << 6) /* halted on error */ 216#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 217#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 218#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 219#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 220#define QTD_STS_STS (1 << 1) /* split transaction state */ 221#define QTD_STS_PING (1 << 0) /* issue PING? */ 222 __le32 hw_buf[5]; /* see EHCI 3.5.4 */ 223 __le32 hw_buf_hi[5]; /* Appendix B */ 224 225 /* the rest is HCD-private */ 226 dma_addr_t qtd_dma; /* qtd address */ 227 struct list_head qtd_list; /* sw qtd list */ 228 struct urb *urb; /* qtd's urb */ 229 size_t length; /* length of buffer */ 230 231 u32 qtd_buffer_len; 232 void *buffer; 233 dma_addr_t buffer_dma; 234 void *transfer_buffer; 235 void *transfer_dma; 236} __attribute__ ((aligned(32))); 237 238/* mask NakCnt+T in qh->hw_alt_next */ 239#define QTD_MASK cpu_to_le32 (~0x1f) 240 241#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) 242 243/* Type tag from {qh, itd, sitd, fstn}->hw_next */ 244#define Q_NEXT_TYPE(dma) ((dma) & cpu_to_le32 (3 << 1)) 245 246/* values for that type tag */ 247#define Q_TYPE_QH cpu_to_le32 (1 << 1) 248 249/* next async queue entry, or pointer to interrupt/periodic QH */ 250#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH) 251 252/* for periodic/async schedules and qtd lists, mark end of list */ 253#define EHCI_LIST_END cpu_to_le32(1) /* "null pointer" to hw */ 254 255/* 256 * Entries in periodic shadow table are pointers to one of four kinds 257 * of data structure. That's dictated by the hardware; a type tag is 258 * encoded in the low bits of the hardware's periodic schedule. Use 259 * Q_NEXT_TYPE to get the tag. 260 * 261 * For entries in the async schedule, the type tag always says "qh". 262 */ 263union ehci_shadow { 264 struct ehci_qh *qh; /* Q_TYPE_QH */ 265 __le32 *hw_next; /* (all types) */ 266 void *ptr; 267}; 268 269/* 270 * EHCI Specification 0.95 Section 3.6 271 * QH: describes control/bulk/interrupt endpoints 272 * See Fig 3-7 "Queue Head Structure Layout". 273 * 274 * These appear in both the async and (for interrupt) periodic schedules. 275 */ 276 277struct ehci_qh { 278 /* first part defined by EHCI spec */ 279 __le32 hw_next; /* see EHCI 3.6.1 */ 280 __le32 hw_info1; /* see EHCI 3.6.2 */ 281#define QH_HEAD 0x00008000 282 __le32 hw_info2; /* see EHCI 3.6.2 */ 283#define QH_SMASK 0x000000ff 284#define QH_CMASK 0x0000ff00 285#define QH_HUBADDR 0x007f0000 286#define QH_HUBPORT 0x3f800000 287#define QH_MULT 0xc0000000 288 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */ 289 290 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 291 __le32 hw_qtd_next; 292 __le32 hw_alt_next; 293 __le32 hw_token; 294 __le32 hw_buf[5]; 295 __le32 hw_buf_hi[5]; 296 297 /* the rest is HCD-private */ 298 dma_addr_t qh_dma; /* address of qh */ 299 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 300 struct list_head qtd_list; /* sw qtd list */ 301 struct ehci_qtd *dummy; 302 struct ehci_qh *reclaim; /* next to reclaim */ 303 304 struct oxu_hcd *oxu; 305 struct kref kref; 306 unsigned stamp; 307 308 u8 qh_state; 309#define QH_STATE_LINKED 1 /* HC sees this */ 310#define QH_STATE_UNLINK 2 /* HC may still see this */ 311#define QH_STATE_IDLE 3 /* HC doesn't see this */ 312#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 313#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 314 315 /* periodic schedule info */ 316 u8 usecs; /* intr bandwidth */ 317 u8 gap_uf; /* uframes split/csplit gap */ 318 u8 c_usecs; /* ... split completion bw */ 319 u16 tt_usecs; /* tt downstream bandwidth */ 320 unsigned short period; /* polling interval */ 321 unsigned short start; /* where polling starts */ 322#define NO_FRAME ((unsigned short)~0) /* pick new start */ 323 struct usb_device *dev; /* access to TT */ 324} __attribute__ ((aligned(32))); 325 326/* 327 * Proper OXU210HP structs 328 */ 329 330#define OXU_OTG_CORE_OFFSET 0x00400 331#define OXU_OTG_CAP_OFFSET (OXU_OTG_CORE_OFFSET + 0x100) 332#define OXU_SPH_CORE_OFFSET 0x00800 333#define OXU_SPH_CAP_OFFSET (OXU_SPH_CORE_OFFSET + 0x100) 334 335#define OXU_OTG_MEM 0xE000 336#define OXU_SPH_MEM 0x16000 337 338/* Only how many elements & element structure are specifies here. */ 339/* 2 host controllers are enabled - total size <= 28 kbytes */ 340#define DEFAULT_I_TDPS 1024 341#define QHEAD_NUM 16 342#define QTD_NUM 32 343#define SITD_NUM 8 344#define MURB_NUM 8 345 346#define BUFFER_NUM 8 347#define BUFFER_SIZE 512 348 349struct oxu_info { 350 struct usb_hcd *hcd[2]; 351}; 352 353struct oxu_buf { 354 u8 buffer[BUFFER_SIZE]; 355} __attribute__ ((aligned(BUFFER_SIZE))); 356 357struct oxu_onchip_mem { 358 struct oxu_buf db_pool[BUFFER_NUM]; 359 360 u32 frame_list[DEFAULT_I_TDPS]; 361 struct ehci_qh qh_pool[QHEAD_NUM]; 362 struct ehci_qtd qtd_pool[QTD_NUM]; 363} __attribute__ ((aligned(4 << 10))); 364 365#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 366 367struct oxu_murb { 368 struct urb urb; 369 struct urb *main; 370 u8 last; 371}; 372 373struct oxu_hcd { /* one per controller */ 374 unsigned int is_otg:1; 375 376 u8 qh_used[QHEAD_NUM]; 377 u8 qtd_used[QTD_NUM]; 378 u8 db_used[BUFFER_NUM]; 379 u8 murb_used[MURB_NUM]; 380 381 struct oxu_onchip_mem __iomem *mem; 382 spinlock_t mem_lock; 383 384 struct timer_list urb_timer; 385 386 struct ehci_caps __iomem *caps; 387 struct ehci_regs __iomem *regs; 388 389 __u32 hcs_params; /* cached register copy */ 390 spinlock_t lock; 391 392 /* async schedule support */ 393 struct ehci_qh *async; 394 struct ehci_qh *reclaim; 395 unsigned reclaim_ready:1; 396 unsigned scanning:1; 397 398 /* periodic schedule support */ 399 unsigned periodic_size; 400 __le32 *periodic; /* hw periodic table */ 401 dma_addr_t periodic_dma; 402 unsigned i_thresh; /* uframes HC might cache */ 403 404 union ehci_shadow *pshadow; /* mirror hw periodic table */ 405 int next_uframe; /* scan periodic, start here */ 406 unsigned periodic_sched; /* periodic activity count */ 407 408 /* per root hub port */ 409 unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; 410 /* bit vectors (one bit per port) */ 411 unsigned long bus_suspended; /* which ports were 412 * already suspended at the 413 * start of a bus suspend 414 */ 415 unsigned long companion_ports;/* which ports are dedicated 416 * to the companion controller 417 */ 418 419 struct timer_list watchdog; 420 unsigned long actions; 421 unsigned stamp; 422 unsigned long next_statechange; 423 u32 command; 424 425 /* SILICON QUIRKS */ 426 struct list_head urb_list; /* this is the head to urb 427 * queue that didn't get enough 428 * resources 429 */ 430 struct oxu_murb *murb_pool; /* murb per split big urb */ 431 unsigned urb_len; 432 433 u8 sbrn; /* packed release number */ 434}; 435 436#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */ 437#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 438#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 439#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ 440 441enum ehci_timer_action { 442 TIMER_IO_WATCHDOG, 443 TIMER_IAA_WATCHDOG, 444 TIMER_ASYNC_SHRINK, 445 TIMER_ASYNC_OFF, 446}; 447 448#include <linux/oxu210hp.h> 449