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12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25
26#define XHCI_SBRN_OFFSET (0x60)
27
28
29#define MAX_HC_SLOTS 256
30
31#define MAX_HC_PORTS 127
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49
50struct xhci_cap_regs {
51 __le32 hc_capbase;
52 __le32 hcs_params1;
53 __le32 hcs_params2;
54 __le32 hcs_params3;
55 __le32 hcc_params;
56 __le32 db_off;
57 __le32 run_regs_off;
58 __le32 hcc_params2;
59
60};
61
62
63
64#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
65
66#define HC_VERSION(p) (((p) >> 16) & 0xffff)
67
68
69
70#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71#define HCS_SLOTS_MASK 0xff
72
73#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74
75#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
76
77
78
79
80#define HCS_IST(p) (((p) >> 0) & 0xf)
81
82#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83
84
85
86#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
87
88
89
90#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91
92#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
93
94
95
96#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97
98#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99
100
101
102#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103
104#define HCC_PPC(p) ((p) & (1 << 3))
105
106#define HCS_INDICATOR(p) ((p) & (1 << 4))
107
108#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109
110#define HCC_LTC(p) ((p) & (1 << 6))
111
112#define HCC_NSS(p) ((p) & (1 << 7))
113
114#define HCC_SPC(p) ((p) & (1 << 9))
115
116#define HCC_CFC(p) ((p) & (1 << 11))
117
118#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119
120#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
121
122#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
123
124
125#define DBOFF_MASK (~0x3)
126
127
128#define RTSOFF_MASK (~0x1f)
129
130
131
132#define HCC2_U3C(p) ((p) & (1 << 0))
133
134#define HCC2_CMC(p) ((p) & (1 << 1))
135
136#define HCC2_FSC(p) ((p) & (1 << 2))
137
138#define HCC2_CTC(p) ((p) & (1 << 3))
139
140#define HCC2_LEC(p) ((p) & (1 << 4))
141
142#define HCC2_CIC(p) ((p) & (1 << 5))
143
144#define HCC2_ETC(p) ((p) & (1 << 6))
145
146
147#define NUM_PORT_REGS 4
148
149#define PORTSC 0
150#define PORTPMSC 1
151#define PORTLI 2
152#define PORTHLPMC 3
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176struct xhci_op_regs {
177 __le32 command;
178 __le32 status;
179 __le32 page_size;
180 __le32 reserved1;
181 __le32 reserved2;
182 __le32 dev_notification;
183 __le64 cmd_ring;
184
185 __le32 reserved3[4];
186 __le64 dcbaa_ptr;
187 __le32 config_reg;
188
189 __le32 reserved4[241];
190
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
194 __le32 reserved5;
195
196 __le32 reserved6[NUM_PORT_REGS*254];
197};
198
199
200
201#define CMD_RUN XHCI_CMD_RUN
202
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204
205
206#define CMD_RESET (1 << 1)
207
208#define CMD_EIE XHCI_CMD_EIE
209
210#define CMD_HSEIE XHCI_CMD_HSEIE
211
212
213#define CMD_LRESET (1 << 7)
214
215#define CMD_CSS (1 << 8)
216#define CMD_CRS (1 << 9)
217
218#define CMD_EWE XHCI_CMD_EWE
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223
224#define CMD_PM_INDEX (1 << 11)
225
226#define CMD_ETE (1 << 14)
227
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229
230#define IMAN_IE (1 << 1)
231#define IMAN_IP (1 << 0)
232
233
234
235#define STS_HALT XHCI_STS_HALT
236
237#define STS_FATAL (1 << 2)
238
239#define STS_EINT (1 << 3)
240
241#define STS_PORT (1 << 4)
242
243
244#define STS_SAVE (1 << 8)
245
246#define STS_RESTORE (1 << 9)
247
248#define STS_SRE (1 << 10)
249
250#define STS_CNR XHCI_STS_CNR
251
252#define STS_HCE (1 << 12)
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260#define DEV_NOTE_MASK (0xffff)
261#define ENABLE_DEV_NOTE(x) (1 << (x))
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264
265#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
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269
270#define CMD_RING_PAUSE (1 << 1)
271
272#define CMD_RING_ABORT (1 << 2)
273
274#define CMD_RING_RUNNING (1 << 3)
275
276
277#define CMD_RING_RSVD_BITS (0x3f)
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281#define MAX_DEVS(p) ((p) & 0xff)
282
283#define CONFIG_U3E (1 << 8)
284
285#define CONFIG_CIE (1 << 9)
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289
290#define PORT_CONNECT (1 << 0)
291
292#define PORT_PE (1 << 1)
293
294
295#define PORT_OC (1 << 3)
296
297#define PORT_RESET (1 << 4)
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301
302#define PORT_PLS_MASK (0xf << 5)
303#define XDEV_U0 (0x0 << 5)
304#define XDEV_U1 (0x1 << 5)
305#define XDEV_U2 (0x2 << 5)
306#define XDEV_U3 (0x3 << 5)
307#define XDEV_DISABLED (0x4 << 5)
308#define XDEV_RXDETECT (0x5 << 5)
309#define XDEV_INACTIVE (0x6 << 5)
310#define XDEV_POLLING (0x7 << 5)
311#define XDEV_RECOVERY (0x8 << 5)
312#define XDEV_HOT_RESET (0x9 << 5)
313#define XDEV_COMP_MODE (0xa << 5)
314#define XDEV_TEST_MODE (0xb << 5)
315#define XDEV_RESUME (0xf << 5)
316
317
318#define PORT_POWER (1 << 9)
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327#define DEV_SPEED_MASK (0xf << 10)
328#define XDEV_FS (0x1 << 10)
329#define XDEV_LS (0x2 << 10)
330#define XDEV_HS (0x3 << 10)
331#define XDEV_SS (0x4 << 10)
332#define XDEV_SSP (0x5 << 10)
333#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
334#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
335#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
336#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
337#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
338#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
339#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
340#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
341
342
343#define SLOT_SPEED_FS (XDEV_FS << 10)
344#define SLOT_SPEED_LS (XDEV_LS << 10)
345#define SLOT_SPEED_HS (XDEV_HS << 10)
346#define SLOT_SPEED_SS (XDEV_SS << 10)
347#define SLOT_SPEED_SSP (XDEV_SSP << 10)
348
349#define PORT_LED_OFF (0 << 14)
350#define PORT_LED_AMBER (1 << 14)
351#define PORT_LED_GREEN (2 << 14)
352#define PORT_LED_MASK (3 << 14)
353
354#define PORT_LINK_STROBE (1 << 16)
355
356#define PORT_CSC (1 << 17)
357
358#define PORT_PEC (1 << 18)
359
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364#define PORT_WRC (1 << 19)
365
366#define PORT_OCC (1 << 20)
367
368#define PORT_RC (1 << 21)
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381
382#define PORT_PLC (1 << 22)
383
384#define PORT_CEC (1 << 23)
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389#define PORT_CAS (1 << 24)
390
391#define PORT_WKCONN_E (1 << 25)
392
393#define PORT_WKDISC_E (1 << 26)
394
395#define PORT_WKOC_E (1 << 27)
396
397
398#define PORT_DEV_REMOVE (1 << 30)
399
400#define PORT_WR (1 << 31)
401
402
403#define DUPLICATE_ENTRY ((u8)(-1))
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409#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
410#define PORT_U1_TIMEOUT_MASK 0xff
411
412#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
413#define PORT_U2_TIMEOUT_MASK (0xff << 8)
414
415
416
417#define PORT_L1S_MASK 7
418#define PORT_L1S_SUCCESS 1
419#define PORT_RWE (1 << 3)
420#define PORT_HIRD(p) (((p) & 0xf) << 4)
421#define PORT_HIRD_MASK (0xf << 4)
422#define PORT_L1DS_MASK (0xff << 8)
423#define PORT_L1DS(p) (((p) & 0xff) << 8)
424#define PORT_HLE (1 << 16)
425#define PORT_TEST_MODE_SHIFT 28
426
427
428#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
429#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
430
431
432#define PORT_HIRDM(p)((p) & 3)
433#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
434#define PORT_BESLD(p)(((p) & 0xf) << 10)
435
436
437#define XHCI_L1_TIMEOUT 512
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449#define XHCI_DEFAULT_BESL 4
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468struct xhci_intr_reg {
469 __le32 irq_pending;
470 __le32 irq_control;
471 __le32 erst_size;
472 __le32 rsvd;
473 __le64 erst_base;
474 __le64 erst_dequeue;
475};
476
477
478#define ER_IRQ_PENDING(p) ((p) & 0x1)
479
480
481#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
482#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
483#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
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489
490#define ER_IRQ_INTERVAL_MASK (0xffff)
491
492#define ER_IRQ_COUNTER_MASK (0xffff << 16)
493
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496#define ERST_SIZE_MASK (0xffff << 16)
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501
502#define ERST_DESI_MASK (0x7)
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506#define ERST_EHB (1 << 3)
507#define ERST_PTR_MASK (0xf)
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518struct xhci_run_regs {
519 __le32 microframe_index;
520 __le32 rsvd[7];
521 struct xhci_intr_reg ir_set[128];
522};
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533struct xhci_doorbell_array {
534 __le32 doorbell[256];
535};
536
537#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
538#define DB_VALUE_HOST 0x00000000
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548struct xhci_protocol_caps {
549 u32 revision;
550 u32 name_string;
551 u32 port_info;
552};
553
554#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
555#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
556#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
557#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
558#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
559
560#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
561#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
562#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
563#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
564#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
565#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
566
567#define PLT_MASK (0x03 << 6)
568#define PLT_SYM (0x00 << 6)
569#define PLT_ASYM_RX (0x02 << 6)
570#define PLT_ASYM_TX (0x03 << 6)
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582struct xhci_container_ctx {
583 unsigned type;
584#define XHCI_CTX_TYPE_DEVICE 0x1
585#define XHCI_CTX_TYPE_INPUT 0x2
586
587 int size;
588
589 u8 *bytes;
590 dma_addr_t dma;
591};
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604struct xhci_slot_ctx {
605 __le32 dev_info;
606 __le32 dev_info2;
607 __le32 tt_info;
608 __le32 dev_state;
609
610 __le32 reserved[4];
611};
612
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614
615#define ROUTE_STRING_MASK (0xfffff)
616
617#define DEV_SPEED (0xf << 20)
618#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
619
620
621#define DEV_MTT (0x1 << 25)
622
623#define DEV_HUB (0x1 << 26)
624
625#define LAST_CTX_MASK (0x1f << 27)
626#define LAST_CTX(p) ((p) << 27)
627#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
628#define SLOT_FLAG (1 << 0)
629#define EP0_FLAG (1 << 1)
630
631
632
633#define MAX_EXIT (0xffff)
634
635#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
636#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
637
638#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
639#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
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646
647#define TT_SLOT (0xff)
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652#define TT_PORT (0xff << 8)
653#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
654#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
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658#define DEV_ADDR_MASK (0xff)
659
660
661#define SLOT_STATE (0x1f << 27)
662#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
663
664#define SLOT_STATE_DISABLED 0
665#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
666#define SLOT_STATE_DEFAULT 1
667#define SLOT_STATE_ADDRESSED 2
668#define SLOT_STATE_CONFIGURED 3
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688struct xhci_ep_ctx {
689 __le32 ep_info;
690 __le32 ep_info2;
691 __le64 deq;
692 __le32 tx_info;
693
694 __le32 reserved[3];
695};
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706
707#define EP_STATE_MASK (0xf)
708#define EP_STATE_DISABLED 0
709#define EP_STATE_RUNNING 1
710#define EP_STATE_HALTED 2
711#define EP_STATE_STOPPED 3
712#define EP_STATE_ERROR 4
713#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
714
715
716#define EP_MULT(p) (((p) & 0x3) << 8)
717#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
718
719
720
721#define EP_INTERVAL(p) (((p) & 0xff) << 16)
722#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
723#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
724#define EP_MAXPSTREAMS_MASK (0x1f << 10)
725#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
726#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
727
728#define EP_HAS_LSA (1 << 15)
729
730#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
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736
737#define FORCE_EVENT (0x1)
738#define ERROR_COUNT(p) (((p) & 0x3) << 1)
739#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
740#define EP_TYPE(p) ((p) << 3)
741#define ISOC_OUT_EP 1
742#define BULK_OUT_EP 2
743#define INT_OUT_EP 3
744#define CTRL_EP 4
745#define ISOC_IN_EP 5
746#define BULK_IN_EP 6
747#define INT_IN_EP 7
748
749
750#define MAX_BURST(p) (((p)&0xff) << 8)
751#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
752#define MAX_PACKET(p) (((p)&0xffff) << 16)
753#define MAX_PACKET_MASK (0xffff << 16)
754#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
755
756
757#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
758#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
759#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
760#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
761
762
763#define EP_CTX_CYCLE_MASK (1 << 0)
764#define SCTX_DEQ_MASK (~0xfL)
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774struct xhci_input_control_ctx {
775 __le32 drop_flags;
776 __le32 add_flags;
777 __le32 rsvd2[6];
778};
779
780#define EP_IS_ADDED(ctrl_ctx, i) \
781 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
782#define EP_IS_DROPPED(ctrl_ctx, i) \
783 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
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788
789struct xhci_command {
790
791 struct xhci_container_ctx *in_ctx;
792 u32 status;
793 int slot_id;
794
795
796
797 struct completion *completion;
798 union xhci_trb *command_trb;
799 struct list_head cmd_list;
800};
801
802
803#define DROP_EP(x) (0x1 << x)
804
805#define ADD_EP(x) (0x1 << x)
806
807struct xhci_stream_ctx {
808
809 __le64 stream_ring;
810
811 __le32 reserved[2];
812};
813
814
815#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
816
817#define SCT_SEC_TR 0
818
819#define SCT_PRI_TR 1
820
821#define SCT_SSA_8 2
822#define SCT_SSA_16 3
823#define SCT_SSA_32 4
824#define SCT_SSA_64 5
825#define SCT_SSA_128 6
826#define SCT_SSA_256 7
827
828
829struct xhci_stream_info {
830 struct xhci_ring **stream_rings;
831
832 unsigned int num_streams;
833
834
835
836 struct xhci_stream_ctx *stream_ctx_array;
837 unsigned int num_stream_ctxs;
838 dma_addr_t ctx_array_dma;
839
840 struct radix_tree_root trb_address_map;
841 struct xhci_command *free_streams_command;
842};
843
844#define SMALL_STREAM_ARRAY_SIZE 256
845#define MEDIUM_STREAM_ARRAY_SIZE 1024
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853struct xhci_bw_info {
854
855 unsigned int ep_interval;
856
857 unsigned int mult;
858 unsigned int num_packets;
859 unsigned int max_packet_size;
860 unsigned int max_esit_payload;
861 unsigned int type;
862};
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867
868
869#define FS_BLOCK 1
870#define HS_BLOCK 4
871#define SS_BLOCK 16
872#define DMI_BLOCK 32
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878
879#define DMI_OVERHEAD 8
880#define DMI_OVERHEAD_BURST 4
881#define SS_OVERHEAD 8
882#define SS_OVERHEAD_BURST 32
883#define HS_OVERHEAD 26
884#define FS_OVERHEAD 20
885#define LS_OVERHEAD 128
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890
891#define TT_HS_OVERHEAD (31 + 94)
892#define TT_DMI_OVERHEAD (25 + 12)
893
894
895#define FS_BW_LIMIT 1285
896#define TT_BW_LIMIT 1320
897#define HS_BW_LIMIT 1607
898#define SS_BW_LIMIT_IN 3906
899#define DMI_BW_LIMIT_IN 3906
900#define SS_BW_LIMIT_OUT 3906
901#define DMI_BW_LIMIT_OUT 3906
902
903
904#define FS_BW_RESERVED 10
905#define HS_BW_RESERVED 20
906#define SS_BW_RESERVED 10
907
908struct xhci_virt_ep {
909 struct xhci_ring *ring;
910
911 struct xhci_stream_info *stream_info;
912
913
914
915 struct xhci_ring *new_ring;
916 unsigned int ep_state;
917#define SET_DEQ_PENDING (1 << 0)
918#define EP_HALTED (1 << 1)
919#define EP_STOP_CMD_PENDING (1 << 2)
920
921#define EP_GETTING_STREAMS (1 << 3)
922#define EP_HAS_STREAMS (1 << 4)
923
924#define EP_GETTING_NO_STREAMS (1 << 5)
925#define EP_HARD_CLEAR_TOGGLE (1 << 6)
926#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
927
928 struct list_head cancelled_td_list;
929
930 struct timer_list stop_cmd_timer;
931 struct xhci_hcd *xhci;
932
933
934
935
936 struct xhci_segment *queued_deq_seg;
937 union xhci_trb *queued_deq_ptr;
938
939
940
941
942
943
944
945 bool skip;
946
947 struct xhci_bw_info bw_info;
948 struct list_head bw_endpoint_list;
949
950 int next_frame_id;
951
952 bool use_extended_tbc;
953};
954
955enum xhci_overhead_type {
956 LS_OVERHEAD_TYPE = 0,
957 FS_OVERHEAD_TYPE,
958 HS_OVERHEAD_TYPE,
959};
960
961struct xhci_interval_bw {
962 unsigned int num_packets;
963
964
965
966 struct list_head endpoints;
967
968 unsigned int overhead[3];
969};
970
971#define XHCI_MAX_INTERVAL 16
972
973struct xhci_interval_bw_table {
974 unsigned int interval0_esit_payload;
975 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
976
977 unsigned int bw_used;
978 unsigned int ss_bw_in;
979 unsigned int ss_bw_out;
980};
981
982
983struct xhci_virt_device {
984 struct usb_device *udev;
985
986
987
988
989
990
991
992
993 struct xhci_container_ctx *out_ctx;
994
995 struct xhci_container_ctx *in_ctx;
996 struct xhci_virt_ep eps[31];
997 u8 fake_port;
998 u8 real_port;
999 struct xhci_interval_bw_table *bw_table;
1000 struct xhci_tt_bw_info *tt_info;
1001
1002 u16 current_mel;
1003
1004 void *debugfs_private;
1005};
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015struct xhci_root_port_bw_info {
1016 struct list_head tts;
1017 unsigned int num_active_tts;
1018 struct xhci_interval_bw_table bw_table;
1019};
1020
1021struct xhci_tt_bw_info {
1022 struct list_head tt_list;
1023 int slot_id;
1024 int ttport;
1025 struct xhci_interval_bw_table bw_table;
1026 int active_eps;
1027};
1028
1029
1030
1031
1032
1033
1034struct xhci_device_context_array {
1035
1036 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1037
1038 dma_addr_t dma;
1039};
1040
1041
1042
1043
1044
1045
1046
1047struct xhci_transfer_event {
1048
1049 __le64 buffer;
1050 __le32 transfer_len;
1051
1052 __le32 flags;
1053};
1054
1055
1056
1057#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1058
1059
1060#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1061
1062
1063#define COMP_CODE_MASK (0xff << 24)
1064#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1065#define COMP_INVALID 0
1066#define COMP_SUCCESS 1
1067#define COMP_DATA_BUFFER_ERROR 2
1068#define COMP_BABBLE_DETECTED_ERROR 3
1069#define COMP_USB_TRANSACTION_ERROR 4
1070#define COMP_TRB_ERROR 5
1071#define COMP_STALL_ERROR 6
1072#define COMP_RESOURCE_ERROR 7
1073#define COMP_BANDWIDTH_ERROR 8
1074#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1075#define COMP_INVALID_STREAM_TYPE_ERROR 10
1076#define COMP_SLOT_NOT_ENABLED_ERROR 11
1077#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1078#define COMP_SHORT_PACKET 13
1079#define COMP_RING_UNDERRUN 14
1080#define COMP_RING_OVERRUN 15
1081#define COMP_VF_EVENT_RING_FULL_ERROR 16
1082#define COMP_PARAMETER_ERROR 17
1083#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1084#define COMP_CONTEXT_STATE_ERROR 19
1085#define COMP_NO_PING_RESPONSE_ERROR 20
1086#define COMP_EVENT_RING_FULL_ERROR 21
1087#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1088#define COMP_MISSED_SERVICE_ERROR 23
1089#define COMP_COMMAND_RING_STOPPED 24
1090#define COMP_COMMAND_ABORTED 25
1091#define COMP_STOPPED 26
1092#define COMP_STOPPED_LENGTH_INVALID 27
1093#define COMP_STOPPED_SHORT_PACKET 28
1094#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1095#define COMP_ISOCH_BUFFER_OVERRUN 31
1096#define COMP_EVENT_LOST_ERROR 32
1097#define COMP_UNDEFINED_ERROR 33
1098#define COMP_INVALID_STREAM_ID_ERROR 34
1099#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1100#define COMP_SPLIT_TRANSACTION_ERROR 36
1101
1102static inline const char *xhci_trb_comp_code_string(u8 status)
1103{
1104 switch (status) {
1105 case COMP_INVALID:
1106 return "Invalid";
1107 case COMP_SUCCESS:
1108 return "Success";
1109 case COMP_DATA_BUFFER_ERROR:
1110 return "Data Buffer Error";
1111 case COMP_BABBLE_DETECTED_ERROR:
1112 return "Babble Detected";
1113 case COMP_USB_TRANSACTION_ERROR:
1114 return "USB Transaction Error";
1115 case COMP_TRB_ERROR:
1116 return "TRB Error";
1117 case COMP_STALL_ERROR:
1118 return "Stall Error";
1119 case COMP_RESOURCE_ERROR:
1120 return "Resource Error";
1121 case COMP_BANDWIDTH_ERROR:
1122 return "Bandwidth Error";
1123 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1124 return "No Slots Available Error";
1125 case COMP_INVALID_STREAM_TYPE_ERROR:
1126 return "Invalid Stream Type Error";
1127 case COMP_SLOT_NOT_ENABLED_ERROR:
1128 return "Slot Not Enabled Error";
1129 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1130 return "Endpoint Not Enabled Error";
1131 case COMP_SHORT_PACKET:
1132 return "Short Packet";
1133 case COMP_RING_UNDERRUN:
1134 return "Ring Underrun";
1135 case COMP_RING_OVERRUN:
1136 return "Ring Overrun";
1137 case COMP_VF_EVENT_RING_FULL_ERROR:
1138 return "VF Event Ring Full Error";
1139 case COMP_PARAMETER_ERROR:
1140 return "Parameter Error";
1141 case COMP_BANDWIDTH_OVERRUN_ERROR:
1142 return "Bandwidth Overrun Error";
1143 case COMP_CONTEXT_STATE_ERROR:
1144 return "Context State Error";
1145 case COMP_NO_PING_RESPONSE_ERROR:
1146 return "No Ping Response Error";
1147 case COMP_EVENT_RING_FULL_ERROR:
1148 return "Event Ring Full Error";
1149 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1150 return "Incompatible Device Error";
1151 case COMP_MISSED_SERVICE_ERROR:
1152 return "Missed Service Error";
1153 case COMP_COMMAND_RING_STOPPED:
1154 return "Command Ring Stopped";
1155 case COMP_COMMAND_ABORTED:
1156 return "Command Aborted";
1157 case COMP_STOPPED:
1158 return "Stopped";
1159 case COMP_STOPPED_LENGTH_INVALID:
1160 return "Stopped - Length Invalid";
1161 case COMP_STOPPED_SHORT_PACKET:
1162 return "Stopped - Short Packet";
1163 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1164 return "Max Exit Latency Too Large Error";
1165 case COMP_ISOCH_BUFFER_OVERRUN:
1166 return "Isoch Buffer Overrun";
1167 case COMP_EVENT_LOST_ERROR:
1168 return "Event Lost Error";
1169 case COMP_UNDEFINED_ERROR:
1170 return "Undefined Error";
1171 case COMP_INVALID_STREAM_ID_ERROR:
1172 return "Invalid Stream ID Error";
1173 case COMP_SECONDARY_BANDWIDTH_ERROR:
1174 return "Secondary Bandwidth Error";
1175 case COMP_SPLIT_TRANSACTION_ERROR:
1176 return "Split Transaction Error";
1177 default:
1178 return "Unknown!!";
1179 }
1180}
1181
1182struct xhci_link_trb {
1183
1184 __le64 segment_ptr;
1185 __le32 intr_target;
1186 __le32 control;
1187};
1188
1189
1190#define LINK_TOGGLE (0x1<<1)
1191
1192
1193struct xhci_event_cmd {
1194
1195 __le64 cmd_trb;
1196 __le32 status;
1197 __le32 flags;
1198};
1199
1200
1201
1202
1203#define TRB_BSR (1<<9)
1204
1205
1206#define TRB_DC (1<<9)
1207
1208
1209#define TRB_TSP (1<<9)
1210
1211enum xhci_ep_reset_type {
1212 EP_HARD_RESET,
1213 EP_SOFT_RESET,
1214};
1215
1216
1217#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1218#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1219
1220
1221#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1222
1223
1224#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1225
1226
1227#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1228#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1229
1230enum xhci_setup_dev {
1231 SETUP_CONTEXT_ONLY,
1232 SETUP_CONTEXT_ADDRESS,
1233};
1234
1235
1236
1237#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1238#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1239
1240
1241#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1242#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1243
1244#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1245#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1246#define LAST_EP_INDEX 30
1247
1248
1249#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1250#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1251#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1252
1253
1254#define TRB_TC (1<<1)
1255
1256
1257
1258#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1259
1260#define EVENT_DATA (1 << 2)
1261
1262
1263
1264#define TRB_LEN(p) ((p) & 0x1ffff)
1265
1266#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1267#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1268
1269#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1270
1271#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1272#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1273
1274#define TRB_TBC(p) (((p) & 0x3) << 7)
1275#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1276
1277
1278#define TRB_CYCLE (1<<0)
1279
1280
1281
1282
1283#define TRB_ENT (1<<1)
1284
1285#define TRB_ISP (1<<2)
1286
1287#define TRB_NO_SNOOP (1<<3)
1288
1289#define TRB_CHAIN (1<<4)
1290
1291#define TRB_IOC (1<<5)
1292
1293#define TRB_IDT (1<<6)
1294
1295
1296#define TRB_BEI (1<<9)
1297
1298
1299#define TRB_DIR_IN (1<<16)
1300#define TRB_TX_TYPE(p) ((p) << 16)
1301#define TRB_DATA_OUT 2
1302#define TRB_DATA_IN 3
1303
1304
1305#define TRB_SIA (1<<31)
1306#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1307
1308struct xhci_generic_trb {
1309 __le32 field[4];
1310};
1311
1312union xhci_trb {
1313 struct xhci_link_trb link;
1314 struct xhci_transfer_event trans_event;
1315 struct xhci_event_cmd event_cmd;
1316 struct xhci_generic_trb generic;
1317};
1318
1319
1320#define TRB_TYPE_BITMASK (0xfc00)
1321#define TRB_TYPE(p) ((p) << 10)
1322#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1323
1324
1325#define TRB_NORMAL 1
1326
1327#define TRB_SETUP 2
1328
1329#define TRB_DATA 3
1330
1331#define TRB_STATUS 4
1332
1333#define TRB_ISOC 5
1334
1335#define TRB_LINK 6
1336#define TRB_EVENT_DATA 7
1337
1338#define TRB_TR_NOOP 8
1339
1340
1341#define TRB_ENABLE_SLOT 9
1342
1343#define TRB_DISABLE_SLOT 10
1344
1345#define TRB_ADDR_DEV 11
1346
1347#define TRB_CONFIG_EP 12
1348
1349#define TRB_EVAL_CONTEXT 13
1350
1351#define TRB_RESET_EP 14
1352
1353#define TRB_STOP_RING 15
1354
1355#define TRB_SET_DEQ 16
1356
1357#define TRB_RESET_DEV 17
1358
1359#define TRB_FORCE_EVENT 18
1360
1361#define TRB_NEG_BANDWIDTH 19
1362
1363#define TRB_SET_LT 20
1364
1365#define TRB_GET_BW 21
1366
1367#define TRB_FORCE_HEADER 22
1368
1369#define TRB_CMD_NOOP 23
1370
1371
1372
1373#define TRB_TRANSFER 32
1374
1375#define TRB_COMPLETION 33
1376
1377#define TRB_PORT_STATUS 34
1378
1379#define TRB_BANDWIDTH_EVENT 35
1380
1381#define TRB_DOORBELL 36
1382
1383#define TRB_HC_EVENT 37
1384
1385#define TRB_DEV_NOTE 38
1386
1387#define TRB_MFINDEX_WRAP 39
1388
1389
1390
1391#define TRB_NEC_CMD_COMP 48
1392
1393#define TRB_NEC_GET_FW 49
1394
1395static inline const char *xhci_trb_type_string(u8 type)
1396{
1397 switch (type) {
1398 case TRB_NORMAL:
1399 return "Normal";
1400 case TRB_SETUP:
1401 return "Setup Stage";
1402 case TRB_DATA:
1403 return "Data Stage";
1404 case TRB_STATUS:
1405 return "Status Stage";
1406 case TRB_ISOC:
1407 return "Isoch";
1408 case TRB_LINK:
1409 return "Link";
1410 case TRB_EVENT_DATA:
1411 return "Event Data";
1412 case TRB_TR_NOOP:
1413 return "No-Op";
1414 case TRB_ENABLE_SLOT:
1415 return "Enable Slot Command";
1416 case TRB_DISABLE_SLOT:
1417 return "Disable Slot Command";
1418 case TRB_ADDR_DEV:
1419 return "Address Device Command";
1420 case TRB_CONFIG_EP:
1421 return "Configure Endpoint Command";
1422 case TRB_EVAL_CONTEXT:
1423 return "Evaluate Context Command";
1424 case TRB_RESET_EP:
1425 return "Reset Endpoint Command";
1426 case TRB_STOP_RING:
1427 return "Stop Ring Command";
1428 case TRB_SET_DEQ:
1429 return "Set TR Dequeue Pointer Command";
1430 case TRB_RESET_DEV:
1431 return "Reset Device Command";
1432 case TRB_FORCE_EVENT:
1433 return "Force Event Command";
1434 case TRB_NEG_BANDWIDTH:
1435 return "Negotiate Bandwidth Command";
1436 case TRB_SET_LT:
1437 return "Set Latency Tolerance Value Command";
1438 case TRB_GET_BW:
1439 return "Get Port Bandwidth Command";
1440 case TRB_FORCE_HEADER:
1441 return "Force Header Command";
1442 case TRB_CMD_NOOP:
1443 return "No-Op Command";
1444 case TRB_TRANSFER:
1445 return "Transfer Event";
1446 case TRB_COMPLETION:
1447 return "Command Completion Event";
1448 case TRB_PORT_STATUS:
1449 return "Port Status Change Event";
1450 case TRB_BANDWIDTH_EVENT:
1451 return "Bandwidth Request Event";
1452 case TRB_DOORBELL:
1453 return "Doorbell Event";
1454 case TRB_HC_EVENT:
1455 return "Host Controller Event";
1456 case TRB_DEV_NOTE:
1457 return "Device Notification Event";
1458 case TRB_MFINDEX_WRAP:
1459 return "MFINDEX Wrap Event";
1460 case TRB_NEC_CMD_COMP:
1461 return "NEC Command Completion Event";
1462 case TRB_NEC_GET_FW:
1463 return "NET Get Firmware Revision Command";
1464 default:
1465 return "UNKNOWN";
1466 }
1467}
1468
1469#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1470
1471#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1472 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1473#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1474 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1475
1476#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1477#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1478
1479
1480
1481
1482
1483
1484#define TRBS_PER_SEGMENT 256
1485
1486#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1487#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1488#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1489
1490#define TRB_MAX_BUFF_SHIFT 16
1491#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1492
1493#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1494 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1495
1496struct xhci_segment {
1497 union xhci_trb *trbs;
1498
1499 struct xhci_segment *next;
1500 dma_addr_t dma;
1501
1502 dma_addr_t bounce_dma;
1503 void *bounce_buf;
1504 unsigned int bounce_offs;
1505 unsigned int bounce_len;
1506};
1507
1508struct xhci_td {
1509 struct list_head td_list;
1510 struct list_head cancelled_td_list;
1511 struct urb *urb;
1512 struct xhci_segment *start_seg;
1513 union xhci_trb *first_trb;
1514 union xhci_trb *last_trb;
1515 struct xhci_segment *bounce_seg;
1516
1517 bool urb_length_set;
1518};
1519
1520
1521#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1522
1523
1524struct xhci_cd {
1525 struct xhci_command *command;
1526 union xhci_trb *cmd_trb;
1527};
1528
1529struct xhci_dequeue_state {
1530 struct xhci_segment *new_deq_seg;
1531 union xhci_trb *new_deq_ptr;
1532 int new_cycle_state;
1533 unsigned int stream_id;
1534};
1535
1536enum xhci_ring_type {
1537 TYPE_CTRL = 0,
1538 TYPE_ISOC,
1539 TYPE_BULK,
1540 TYPE_INTR,
1541 TYPE_STREAM,
1542 TYPE_COMMAND,
1543 TYPE_EVENT,
1544};
1545
1546static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1547{
1548 switch (type) {
1549 case TYPE_CTRL:
1550 return "CTRL";
1551 case TYPE_ISOC:
1552 return "ISOC";
1553 case TYPE_BULK:
1554 return "BULK";
1555 case TYPE_INTR:
1556 return "INTR";
1557 case TYPE_STREAM:
1558 return "STREAM";
1559 case TYPE_COMMAND:
1560 return "CMD";
1561 case TYPE_EVENT:
1562 return "EVENT";
1563 }
1564
1565 return "UNKNOWN";
1566}
1567
1568struct xhci_ring {
1569 struct xhci_segment *first_seg;
1570 struct xhci_segment *last_seg;
1571 union xhci_trb *enqueue;
1572 struct xhci_segment *enq_seg;
1573 union xhci_trb *dequeue;
1574 struct xhci_segment *deq_seg;
1575 struct list_head td_list;
1576
1577
1578
1579
1580
1581 u32 cycle_state;
1582 unsigned int stream_id;
1583 unsigned int num_segs;
1584 unsigned int num_trbs_free;
1585 unsigned int num_trbs_free_temp;
1586 unsigned int bounce_buf_len;
1587 enum xhci_ring_type type;
1588 bool last_td_was_short;
1589 struct radix_tree_root *trb_address_map;
1590};
1591
1592struct xhci_erst_entry {
1593
1594 __le64 seg_addr;
1595 __le32 seg_size;
1596
1597 __le32 rsvd;
1598};
1599
1600struct xhci_erst {
1601 struct xhci_erst_entry *entries;
1602 unsigned int num_entries;
1603
1604 dma_addr_t erst_dma_addr;
1605
1606 unsigned int erst_size;
1607};
1608
1609struct xhci_scratchpad {
1610 u64 *sp_array;
1611 dma_addr_t sp_dma;
1612 void **sp_buffers;
1613};
1614
1615struct urb_priv {
1616 int num_tds;
1617 int num_tds_done;
1618 struct xhci_td td[0];
1619};
1620
1621
1622
1623
1624
1625
1626#define ERST_NUM_SEGS 1
1627
1628#define ERST_SIZE 64
1629
1630#define ERST_ENTRIES 1
1631
1632#define POLL_TIMEOUT 60
1633
1634#define XHCI_STOP_EP_CMD_TIMEOUT 5
1635
1636
1637struct s3_save {
1638 u32 command;
1639 u32 dev_nt;
1640 u64 dcbaa_ptr;
1641 u32 config_reg;
1642 u32 irq_pending;
1643 u32 irq_control;
1644 u32 erst_size;
1645 u64 erst_base;
1646 u64 erst_dequeue;
1647};
1648
1649
1650struct dev_info {
1651 u32 dev_id;
1652 struct list_head list;
1653};
1654
1655struct xhci_bus_state {
1656 unsigned long bus_suspended;
1657 unsigned long next_statechange;
1658
1659
1660
1661 u32 port_c_suspend;
1662 u32 suspended_ports;
1663 u32 port_remote_wakeup;
1664 unsigned long resume_done[USB_MAXCHILDREN];
1665
1666 unsigned long resuming_ports;
1667
1668 unsigned long rexit_ports;
1669 struct completion rexit_done[USB_MAXCHILDREN];
1670};
1671
1672
1673
1674
1675
1676
1677#define XHCI_MAX_REXIT_TIMEOUT (20 * 1000)
1678
1679static inline unsigned int hcd_index(struct usb_hcd *hcd)
1680{
1681 if (hcd->speed >= HCD_USB3)
1682 return 0;
1683 else
1684 return 1;
1685}
1686
1687struct xhci_hub {
1688 u8 maj_rev;
1689 u8 min_rev;
1690 u32 *psi;
1691 u8 psi_count;
1692 u8 psi_uid_count;
1693};
1694
1695
1696struct xhci_hcd {
1697 struct usb_hcd *main_hcd;
1698 struct usb_hcd *shared_hcd;
1699
1700 struct xhci_cap_regs __iomem *cap_regs;
1701 struct xhci_op_regs __iomem *op_regs;
1702 struct xhci_run_regs __iomem *run_regs;
1703 struct xhci_doorbell_array __iomem *dba;
1704
1705 struct xhci_intr_reg __iomem *ir_set;
1706
1707
1708 __u32 hcs_params1;
1709 __u32 hcs_params2;
1710 __u32 hcs_params3;
1711 __u32 hcc_params;
1712 __u32 hcc_params2;
1713
1714 spinlock_t lock;
1715
1716
1717 u8 sbrn;
1718 u16 hci_version;
1719 u8 max_slots;
1720 u8 max_interrupters;
1721 u8 max_ports;
1722 u8 isoc_threshold;
1723
1724 u32 imod_interval;
1725 int event_ring_max;
1726
1727 int page_size;
1728
1729 int page_shift;
1730
1731 int msix_count;
1732
1733 struct clk *clk;
1734 struct clk *reg_clk;
1735
1736 struct xhci_device_context_array *dcbaa;
1737 struct xhci_ring *cmd_ring;
1738 unsigned int cmd_ring_state;
1739#define CMD_RING_STATE_RUNNING (1 << 0)
1740#define CMD_RING_STATE_ABORTED (1 << 1)
1741#define CMD_RING_STATE_STOPPED (1 << 2)
1742 struct list_head cmd_list;
1743 unsigned int cmd_ring_reserved_trbs;
1744 struct delayed_work cmd_timer;
1745 struct completion cmd_ring_stop_completion;
1746 struct xhci_command *current_cmd;
1747 struct xhci_ring *event_ring;
1748 struct xhci_erst erst;
1749
1750 struct xhci_scratchpad *scratchpad;
1751
1752 struct list_head lpm_failed_devs;
1753
1754
1755
1756 struct mutex mutex;
1757
1758 struct xhci_command *lpm_command;
1759
1760 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1761
1762 struct xhci_root_port_bw_info *rh_bw;
1763
1764
1765 struct dma_pool *device_pool;
1766 struct dma_pool *segment_pool;
1767 struct dma_pool *small_streams_pool;
1768 struct dma_pool *medium_streams_pool;
1769
1770
1771 unsigned int xhc_state;
1772
1773 u32 command;
1774 struct s3_save s3;
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787#define XHCI_STATE_DYING (1 << 0)
1788#define XHCI_STATE_HALTED (1 << 1)
1789#define XHCI_STATE_REMOVING (1 << 2)
1790 unsigned int quirks;
1791#define XHCI_LINK_TRB_QUIRK (1 << 0)
1792#define XHCI_RESET_EP_QUIRK (1 << 1)
1793#define XHCI_NEC_HOST (1 << 2)
1794#define XHCI_AMD_PLL_FIX (1 << 3)
1795#define XHCI_SPURIOUS_SUCCESS (1 << 4)
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805#define XHCI_EP_LIMIT_QUIRK (1 << 5)
1806#define XHCI_BROKEN_MSI (1 << 6)
1807#define XHCI_RESET_ON_RESUME (1 << 7)
1808#define XHCI_SW_BW_CHECKING (1 << 8)
1809#define XHCI_AMD_0x96_HOST (1 << 9)
1810#define XHCI_TRUST_TX_LENGTH (1 << 10)
1811#define XHCI_LPM_SUPPORT (1 << 11)
1812#define XHCI_INTEL_HOST (1 << 12)
1813#define XHCI_SPURIOUS_REBOOT (1 << 13)
1814#define XHCI_COMP_MODE_QUIRK (1 << 14)
1815#define XHCI_AVOID_BEI (1 << 15)
1816#define XHCI_PLAT (1 << 16)
1817#define XHCI_SLOW_SUSPEND (1 << 17)
1818#define XHCI_SPURIOUS_WAKEUP (1 << 18)
1819
1820#define XHCI_BROKEN_STREAMS (1 << 19)
1821#define XHCI_PME_STUCK_QUIRK (1 << 20)
1822#define XHCI_MTK_HOST (1 << 21)
1823#define XHCI_SSIC_PORT_UNUSED (1 << 22)
1824#define XHCI_NO_64BIT_SUPPORT (1 << 23)
1825#define XHCI_MISSING_CAS (1 << 24)
1826
1827#define XHCI_BROKEN_PORT_PED (1 << 25)
1828#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)
1829#define XHCI_U2_DISABLE_WAKE (1 << 27)
1830#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
1831#define XHCI_HW_LPM_DISABLE (1 << 29)
1832#define XHCI_SUSPEND_DELAY (1 << 30)
1833#define XHCI_INTEL_USB_ROLE_SW (1 << 31)
1834
1835 unsigned int num_active_eps;
1836 unsigned int limit_active_eps;
1837
1838 struct xhci_bus_state bus_state[2];
1839
1840 u8 *port_array;
1841
1842 __le32 __iomem **usb3_ports;
1843 unsigned int num_usb3_ports;
1844
1845 __le32 __iomem **usb2_ports;
1846 struct xhci_hub usb2_rhub;
1847 struct xhci_hub usb3_rhub;
1848 unsigned int num_usb2_ports;
1849
1850 unsigned sw_lpm_support:1;
1851
1852 unsigned hw_lpm_support:1;
1853
1854 u32 *ext_caps;
1855 unsigned int num_ext_caps;
1856
1857 struct timer_list comp_mode_recovery_timer;
1858 u32 port_status_u0;
1859 u16 test_mode;
1860
1861#define COMP_MODE_RCVRY_MSECS 2000
1862
1863 struct dentry *debugfs_root;
1864 struct dentry *debugfs_slots;
1865 struct list_head regset_list;
1866
1867 void *dbc;
1868
1869 unsigned long priv[0] __aligned(sizeof(s64));
1870};
1871
1872
1873struct xhci_driver_overrides {
1874 size_t extra_priv_size;
1875 int (*reset)(struct usb_hcd *hcd);
1876 int (*start)(struct usb_hcd *hcd);
1877};
1878
1879#define XHCI_CFC_DELAY 10
1880
1881
1882static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1883{
1884 struct usb_hcd *primary_hcd;
1885
1886 if (usb_hcd_is_primary_hcd(hcd))
1887 primary_hcd = hcd;
1888 else
1889 primary_hcd = hcd->primary_hcd;
1890
1891 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1892}
1893
1894static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1895{
1896 return xhci->main_hcd;
1897}
1898
1899#define xhci_dbg(xhci, fmt, args...) \
1900 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1901#define xhci_err(xhci, fmt, args...) \
1902 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1903#define xhci_warn(xhci, fmt, args...) \
1904 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1905#define xhci_warn_ratelimited(xhci, fmt, args...) \
1906 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1907#define xhci_info(xhci, fmt, args...) \
1908 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1920 __le64 __iomem *regs)
1921{
1922 return lo_hi_readq(regs);
1923}
1924static inline void xhci_write_64(struct xhci_hcd *xhci,
1925 const u64 val, __le64 __iomem *regs)
1926{
1927 lo_hi_writeq(val, regs);
1928}
1929
1930static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1931{
1932 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1933}
1934
1935
1936char *xhci_get_slot_state(struct xhci_hcd *xhci,
1937 struct xhci_container_ctx *ctx);
1938void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1939 const char *fmt, ...);
1940
1941
1942void xhci_mem_cleanup(struct xhci_hcd *xhci);
1943int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1944void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1945int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1946int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1947void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1948 struct usb_device *udev);
1949unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1950unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1951unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1952void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1953void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1954 struct xhci_virt_device *virt_dev,
1955 int old_active_eps);
1956void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1957void xhci_update_bw_info(struct xhci_hcd *xhci,
1958 struct xhci_container_ctx *in_ctx,
1959 struct xhci_input_control_ctx *ctrl_ctx,
1960 struct xhci_virt_device *virt_dev);
1961void xhci_endpoint_copy(struct xhci_hcd *xhci,
1962 struct xhci_container_ctx *in_ctx,
1963 struct xhci_container_ctx *out_ctx,
1964 unsigned int ep_index);
1965void xhci_slot_copy(struct xhci_hcd *xhci,
1966 struct xhci_container_ctx *in_ctx,
1967 struct xhci_container_ctx *out_ctx);
1968int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1969 struct usb_device *udev, struct usb_host_endpoint *ep,
1970 gfp_t mem_flags);
1971struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1972 unsigned int num_segs, unsigned int cycle_state,
1973 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1974void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1975int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1976 unsigned int num_trbs, gfp_t flags);
1977int xhci_alloc_erst(struct xhci_hcd *xhci,
1978 struct xhci_ring *evt_ring,
1979 struct xhci_erst *erst,
1980 gfp_t flags);
1981void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1982void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1983 struct xhci_virt_device *virt_dev,
1984 unsigned int ep_index);
1985struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1986 unsigned int num_stream_ctxs,
1987 unsigned int num_streams,
1988 unsigned int max_packet, gfp_t flags);
1989void xhci_free_stream_info(struct xhci_hcd *xhci,
1990 struct xhci_stream_info *stream_info);
1991void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1992 struct xhci_ep_ctx *ep_ctx,
1993 struct xhci_stream_info *stream_info);
1994void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1995 struct xhci_virt_ep *ep);
1996void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1997 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1998struct xhci_ring *xhci_dma_to_transfer_ring(
1999 struct xhci_virt_ep *ep,
2000 u64 address);
2001struct xhci_ring *xhci_stream_id_to_ring(
2002 struct xhci_virt_device *dev,
2003 unsigned int ep_index,
2004 unsigned int stream_id);
2005struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2006 bool allocate_completion, gfp_t mem_flags);
2007struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2008 bool allocate_completion, gfp_t mem_flags);
2009void xhci_urb_free_priv(struct urb_priv *urb_priv);
2010void xhci_free_command(struct xhci_hcd *xhci,
2011 struct xhci_command *command);
2012struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2013 int type, gfp_t flags);
2014void xhci_free_container_ctx(struct xhci_hcd *xhci,
2015 struct xhci_container_ctx *ctx);
2016
2017
2018typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2019int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2020void xhci_quiesce(struct xhci_hcd *xhci);
2021int xhci_halt(struct xhci_hcd *xhci);
2022int xhci_start(struct xhci_hcd *xhci);
2023int xhci_reset(struct xhci_hcd *xhci);
2024int xhci_run(struct usb_hcd *hcd);
2025int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2026void xhci_init_driver(struct hc_driver *drv,
2027 const struct xhci_driver_overrides *over);
2028int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2029int xhci_ext_cap_init(struct xhci_hcd *xhci);
2030
2031int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2032int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2033
2034irqreturn_t xhci_irq(struct usb_hcd *hcd);
2035irqreturn_t xhci_msi_irq(int irq, void *hcd);
2036int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2037int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2038 struct xhci_virt_device *virt_dev,
2039 struct usb_device *hdev,
2040 struct usb_tt *tt, gfp_t mem_flags);
2041
2042
2043dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2044struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2045 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2046 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2047int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2048void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2049int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2050 u32 trb_type, u32 slot_id);
2051int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2052 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2053int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2054 u32 field1, u32 field2, u32 field3, u32 field4);
2055int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2056 int slot_id, unsigned int ep_index, int suspend);
2057int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2058 int slot_id, unsigned int ep_index);
2059int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2060 int slot_id, unsigned int ep_index);
2061int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2062 int slot_id, unsigned int ep_index);
2063int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2064 struct urb *urb, int slot_id, unsigned int ep_index);
2065int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2066 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2067 bool command_must_succeed);
2068int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2069 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2070int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2071 int slot_id, unsigned int ep_index,
2072 enum xhci_ep_reset_type reset_type);
2073int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2074 u32 slot_id);
2075void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2076 unsigned int slot_id, unsigned int ep_index,
2077 unsigned int stream_id, struct xhci_td *cur_td,
2078 struct xhci_dequeue_state *state);
2079void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2080 unsigned int slot_id, unsigned int ep_index,
2081 struct xhci_dequeue_state *deq_state);
2082void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2083 unsigned int stream_id, struct xhci_td *td);
2084void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2085void xhci_handle_command_timeout(struct work_struct *work);
2086
2087void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2088 unsigned int ep_index, unsigned int stream_id);
2089void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2090void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2091unsigned int count_trbs(u64 addr, u64 len);
2092
2093
2094void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
2095 int port_id, u32 link_state);
2096void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
2097 int port_id, u32 port_bit);
2098int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2099 char *buf, u16 wLength);
2100int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2101int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2102void xhci_hc_died(struct xhci_hcd *xhci);
2103
2104#ifdef CONFIG_PM
2105int xhci_bus_suspend(struct usb_hcd *hcd);
2106int xhci_bus_resume(struct usb_hcd *hcd);
2107#else
2108#define xhci_bus_suspend NULL
2109#define xhci_bus_resume NULL
2110#endif
2111
2112u32 xhci_port_state_to_neutral(u32 state);
2113int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2114 u16 port);
2115void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2116
2117
2118struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2119struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2120struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2121
2122struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2123 unsigned int slot_id, unsigned int ep_index,
2124 unsigned int stream_id);
2125
2126static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2127 struct urb *urb)
2128{
2129 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2130 xhci_get_endpoint_index(&urb->ep->desc),
2131 urb->stream_id);
2132}
2133
2134static inline char *xhci_slot_state_string(u32 state)
2135{
2136 switch (state) {
2137 case SLOT_STATE_ENABLED:
2138 return "enabled/disabled";
2139 case SLOT_STATE_DEFAULT:
2140 return "default";
2141 case SLOT_STATE_ADDRESSED:
2142 return "addressed";
2143 case SLOT_STATE_CONFIGURED:
2144 return "configured";
2145 default:
2146 return "reserved";
2147 }
2148}
2149
2150static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2151 u32 field3)
2152{
2153 static char str[256];
2154 int type = TRB_FIELD_TO_TYPE(field3);
2155
2156 switch (type) {
2157 case TRB_LINK:
2158 sprintf(str,
2159 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2160 field1, field0, GET_INTR_TARGET(field2),
2161 xhci_trb_type_string(type),
2162 field3 & TRB_IOC ? 'I' : 'i',
2163 field3 & TRB_CHAIN ? 'C' : 'c',
2164 field3 & TRB_TC ? 'T' : 't',
2165 field3 & TRB_CYCLE ? 'C' : 'c');
2166 break;
2167 case TRB_TRANSFER:
2168 case TRB_COMPLETION:
2169 case TRB_PORT_STATUS:
2170 case TRB_BANDWIDTH_EVENT:
2171 case TRB_DOORBELL:
2172 case TRB_HC_EVENT:
2173 case TRB_DEV_NOTE:
2174 case TRB_MFINDEX_WRAP:
2175 sprintf(str,
2176 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2177 field1, field0,
2178 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2179 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2180
2181 TRB_TO_EP_INDEX(field3) + 1,
2182 xhci_trb_type_string(type),
2183 field3 & EVENT_DATA ? 'E' : 'e',
2184 field3 & TRB_CYCLE ? 'C' : 'c');
2185
2186 break;
2187 case TRB_SETUP:
2188 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2189 field0 & 0xff,
2190 (field0 & 0xff00) >> 8,
2191 (field0 & 0xff000000) >> 24,
2192 (field0 & 0xff0000) >> 16,
2193 (field1 & 0xff00) >> 8,
2194 field1 & 0xff,
2195 (field1 & 0xff000000) >> 16 |
2196 (field1 & 0xff0000) >> 16,
2197 TRB_LEN(field2), GET_TD_SIZE(field2),
2198 GET_INTR_TARGET(field2),
2199 xhci_trb_type_string(type),
2200 field3 & TRB_IDT ? 'I' : 'i',
2201 field3 & TRB_IOC ? 'I' : 'i',
2202 field3 & TRB_CYCLE ? 'C' : 'c');
2203 break;
2204 case TRB_DATA:
2205 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2206 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2207 GET_INTR_TARGET(field2),
2208 xhci_trb_type_string(type),
2209 field3 & TRB_IDT ? 'I' : 'i',
2210 field3 & TRB_IOC ? 'I' : 'i',
2211 field3 & TRB_CHAIN ? 'C' : 'c',
2212 field3 & TRB_NO_SNOOP ? 'S' : 's',
2213 field3 & TRB_ISP ? 'I' : 'i',
2214 field3 & TRB_ENT ? 'E' : 'e',
2215 field3 & TRB_CYCLE ? 'C' : 'c');
2216 break;
2217 case TRB_STATUS:
2218 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2219 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2220 GET_INTR_TARGET(field2),
2221 xhci_trb_type_string(type),
2222 field3 & TRB_IOC ? 'I' : 'i',
2223 field3 & TRB_CHAIN ? 'C' : 'c',
2224 field3 & TRB_ENT ? 'E' : 'e',
2225 field3 & TRB_CYCLE ? 'C' : 'c');
2226 break;
2227 case TRB_NORMAL:
2228 case TRB_ISOC:
2229 case TRB_EVENT_DATA:
2230 case TRB_TR_NOOP:
2231 sprintf(str,
2232 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2233 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2234 GET_INTR_TARGET(field2),
2235 xhci_trb_type_string(type),
2236 field3 & TRB_BEI ? 'B' : 'b',
2237 field3 & TRB_IDT ? 'I' : 'i',
2238 field3 & TRB_IOC ? 'I' : 'i',
2239 field3 & TRB_CHAIN ? 'C' : 'c',
2240 field3 & TRB_NO_SNOOP ? 'S' : 's',
2241 field3 & TRB_ISP ? 'I' : 'i',
2242 field3 & TRB_ENT ? 'E' : 'e',
2243 field3 & TRB_CYCLE ? 'C' : 'c');
2244 break;
2245
2246 case TRB_CMD_NOOP:
2247 case TRB_ENABLE_SLOT:
2248 sprintf(str,
2249 "%s: flags %c",
2250 xhci_trb_type_string(type),
2251 field3 & TRB_CYCLE ? 'C' : 'c');
2252 break;
2253 case TRB_DISABLE_SLOT:
2254 case TRB_NEG_BANDWIDTH:
2255 sprintf(str,
2256 "%s: slot %d flags %c",
2257 xhci_trb_type_string(type),
2258 TRB_TO_SLOT_ID(field3),
2259 field3 & TRB_CYCLE ? 'C' : 'c');
2260 break;
2261 case TRB_ADDR_DEV:
2262 sprintf(str,
2263 "%s: ctx %08x%08x slot %d flags %c:%c",
2264 xhci_trb_type_string(type),
2265 field1, field0,
2266 TRB_TO_SLOT_ID(field3),
2267 field3 & TRB_BSR ? 'B' : 'b',
2268 field3 & TRB_CYCLE ? 'C' : 'c');
2269 break;
2270 case TRB_CONFIG_EP:
2271 sprintf(str,
2272 "%s: ctx %08x%08x slot %d flags %c:%c",
2273 xhci_trb_type_string(type),
2274 field1, field0,
2275 TRB_TO_SLOT_ID(field3),
2276 field3 & TRB_DC ? 'D' : 'd',
2277 field3 & TRB_CYCLE ? 'C' : 'c');
2278 break;
2279 case TRB_EVAL_CONTEXT:
2280 sprintf(str,
2281 "%s: ctx %08x%08x slot %d flags %c",
2282 xhci_trb_type_string(type),
2283 field1, field0,
2284 TRB_TO_SLOT_ID(field3),
2285 field3 & TRB_CYCLE ? 'C' : 'c');
2286 break;
2287 case TRB_RESET_EP:
2288 sprintf(str,
2289 "%s: ctx %08x%08x slot %d ep %d flags %c",
2290 xhci_trb_type_string(type),
2291 field1, field0,
2292 TRB_TO_SLOT_ID(field3),
2293
2294 TRB_TO_EP_INDEX(field3) + 1,
2295 field3 & TRB_CYCLE ? 'C' : 'c');
2296 break;
2297 case TRB_STOP_RING:
2298 sprintf(str,
2299 "%s: slot %d sp %d ep %d flags %c",
2300 xhci_trb_type_string(type),
2301 TRB_TO_SLOT_ID(field3),
2302 TRB_TO_SUSPEND_PORT(field3),
2303
2304 TRB_TO_EP_INDEX(field3) + 1,
2305 field3 & TRB_CYCLE ? 'C' : 'c');
2306 break;
2307 case TRB_SET_DEQ:
2308 sprintf(str,
2309 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2310 xhci_trb_type_string(type),
2311 field1, field0,
2312 TRB_TO_STREAM_ID(field2),
2313 TRB_TO_SLOT_ID(field3),
2314
2315 TRB_TO_EP_INDEX(field3) + 1,
2316 field3 & TRB_CYCLE ? 'C' : 'c');
2317 break;
2318 case TRB_RESET_DEV:
2319 sprintf(str,
2320 "%s: slot %d flags %c",
2321 xhci_trb_type_string(type),
2322 TRB_TO_SLOT_ID(field3),
2323 field3 & TRB_CYCLE ? 'C' : 'c');
2324 break;
2325 case TRB_FORCE_EVENT:
2326 sprintf(str,
2327 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2328 xhci_trb_type_string(type),
2329 field1, field0,
2330 TRB_TO_VF_INTR_TARGET(field2),
2331 TRB_TO_VF_ID(field3),
2332 field3 & TRB_CYCLE ? 'C' : 'c');
2333 break;
2334 case TRB_SET_LT:
2335 sprintf(str,
2336 "%s: belt %d flags %c",
2337 xhci_trb_type_string(type),
2338 TRB_TO_BELT(field3),
2339 field3 & TRB_CYCLE ? 'C' : 'c');
2340 break;
2341 case TRB_GET_BW:
2342 sprintf(str,
2343 "%s: ctx %08x%08x slot %d speed %d flags %c",
2344 xhci_trb_type_string(type),
2345 field1, field0,
2346 TRB_TO_SLOT_ID(field3),
2347 TRB_TO_DEV_SPEED(field3),
2348 field3 & TRB_CYCLE ? 'C' : 'c');
2349 break;
2350 case TRB_FORCE_HEADER:
2351 sprintf(str,
2352 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2353 xhci_trb_type_string(type),
2354 field2, field1, field0 & 0xffffffe0,
2355 TRB_TO_PACKET_TYPE(field0),
2356 TRB_TO_ROOTHUB_PORT(field3),
2357 field3 & TRB_CYCLE ? 'C' : 'c');
2358 break;
2359 default:
2360 sprintf(str,
2361 "type '%s' -> raw %08x %08x %08x %08x",
2362 xhci_trb_type_string(type),
2363 field0, field1, field2, field3);
2364 }
2365
2366 return str;
2367}
2368
2369static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2370 u32 tt_info, u32 state)
2371{
2372 static char str[1024];
2373 u32 speed;
2374 u32 hub;
2375 u32 mtt;
2376 int ret = 0;
2377
2378 speed = info & DEV_SPEED;
2379 hub = info & DEV_HUB;
2380 mtt = info & DEV_MTT;
2381
2382 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2383 info & ROUTE_STRING_MASK,
2384 ({ char *s;
2385 switch (speed) {
2386 case SLOT_SPEED_FS:
2387 s = "full-speed";
2388 break;
2389 case SLOT_SPEED_LS:
2390 s = "low-speed";
2391 break;
2392 case SLOT_SPEED_HS:
2393 s = "high-speed";
2394 break;
2395 case SLOT_SPEED_SS:
2396 s = "super-speed";
2397 break;
2398 case SLOT_SPEED_SSP:
2399 s = "super-speed plus";
2400 break;
2401 default:
2402 s = "UNKNOWN speed";
2403 } s; }),
2404 mtt ? " multi-TT" : "",
2405 hub ? " Hub" : "",
2406 (info & LAST_CTX_MASK) >> 27,
2407 info2 & MAX_EXIT,
2408 DEVINFO_TO_ROOT_HUB_PORT(info2),
2409 DEVINFO_TO_MAX_PORTS(info2));
2410
2411 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2412 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2413 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2414 state & DEV_ADDR_MASK,
2415 xhci_slot_state_string(GET_SLOT_STATE(state)));
2416
2417 return str;
2418}
2419
2420
2421static inline const char *xhci_portsc_link_state_string(u32 portsc)
2422{
2423 switch (portsc & PORT_PLS_MASK) {
2424 case XDEV_U0:
2425 return "U0";
2426 case XDEV_U1:
2427 return "U1";
2428 case XDEV_U2:
2429 return "U2";
2430 case XDEV_U3:
2431 return "U3";
2432 case XDEV_DISABLED:
2433 return "Disabled";
2434 case XDEV_RXDETECT:
2435 return "RxDetect";
2436 case XDEV_INACTIVE:
2437 return "Inactive";
2438 case XDEV_POLLING:
2439 return "Polling";
2440 case XDEV_RECOVERY:
2441 return "Recovery";
2442 case XDEV_HOT_RESET:
2443 return "Hot Reset";
2444 case XDEV_COMP_MODE:
2445 return "Compliance mode";
2446 case XDEV_TEST_MODE:
2447 return "Test mode";
2448 case XDEV_RESUME:
2449 return "Resume";
2450 default:
2451 break;
2452 }
2453 return "Unknown";
2454}
2455
2456static inline const char *xhci_decode_portsc(u32 portsc)
2457{
2458 static char str[256];
2459 int ret;
2460
2461 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2462 portsc & PORT_POWER ? "Powered" : "Powered-off",
2463 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2464 portsc & PORT_PE ? "Enabled" : "Disabled",
2465 xhci_portsc_link_state_string(portsc),
2466 DEV_PORT_SPEED(portsc));
2467
2468 if (portsc & PORT_OC)
2469 ret += sprintf(str + ret, "OverCurrent ");
2470 if (portsc & PORT_RESET)
2471 ret += sprintf(str + ret, "In-Reset ");
2472
2473 ret += sprintf(str + ret, "Change: ");
2474 if (portsc & PORT_CSC)
2475 ret += sprintf(str + ret, "CSC ");
2476 if (portsc & PORT_PEC)
2477 ret += sprintf(str + ret, "PEC ");
2478 if (portsc & PORT_WRC)
2479 ret += sprintf(str + ret, "WRC ");
2480 if (portsc & PORT_OCC)
2481 ret += sprintf(str + ret, "OCC ");
2482 if (portsc & PORT_RC)
2483 ret += sprintf(str + ret, "PRC ");
2484 if (portsc & PORT_PLC)
2485 ret += sprintf(str + ret, "PLC ");
2486 if (portsc & PORT_CEC)
2487 ret += sprintf(str + ret, "CEC ");
2488 if (portsc & PORT_CAS)
2489 ret += sprintf(str + ret, "CAS ");
2490
2491 ret += sprintf(str + ret, "Wake: ");
2492 if (portsc & PORT_WKCONN_E)
2493 ret += sprintf(str + ret, "WCE ");
2494 if (portsc & PORT_WKDISC_E)
2495 ret += sprintf(str + ret, "WDE ");
2496 if (portsc & PORT_WKOC_E)
2497 ret += sprintf(str + ret, "WOE ");
2498
2499 return str;
2500}
2501
2502static inline const char *xhci_ep_state_string(u8 state)
2503{
2504 switch (state) {
2505 case EP_STATE_DISABLED:
2506 return "disabled";
2507 case EP_STATE_RUNNING:
2508 return "running";
2509 case EP_STATE_HALTED:
2510 return "halted";
2511 case EP_STATE_STOPPED:
2512 return "stopped";
2513 case EP_STATE_ERROR:
2514 return "error";
2515 default:
2516 return "INVALID";
2517 }
2518}
2519
2520static inline const char *xhci_ep_type_string(u8 type)
2521{
2522 switch (type) {
2523 case ISOC_OUT_EP:
2524 return "Isoc OUT";
2525 case BULK_OUT_EP:
2526 return "Bulk OUT";
2527 case INT_OUT_EP:
2528 return "Int OUT";
2529 case CTRL_EP:
2530 return "Ctrl";
2531 case ISOC_IN_EP:
2532 return "Isoc IN";
2533 case BULK_IN_EP:
2534 return "Bulk IN";
2535 case INT_IN_EP:
2536 return "Int IN";
2537 default:
2538 return "INVALID";
2539 }
2540}
2541
2542static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2543 u32 tx_info)
2544{
2545 static char str[1024];
2546 int ret;
2547
2548 u32 esit;
2549 u16 maxp;
2550 u16 avg;
2551
2552 u8 max_pstr;
2553 u8 ep_state;
2554 u8 interval;
2555 u8 ep_type;
2556 u8 burst;
2557 u8 cerr;
2558 u8 mult;
2559
2560 bool lsa;
2561 bool hid;
2562
2563 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2564 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2565
2566 ep_state = info & EP_STATE_MASK;
2567 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2568 interval = CTX_TO_EP_INTERVAL(info);
2569 mult = CTX_TO_EP_MULT(info) + 1;
2570 lsa = !!(info & EP_HAS_LSA);
2571
2572 cerr = (info2 & (3 << 1)) >> 1;
2573 ep_type = CTX_TO_EP_TYPE(info2);
2574 hid = !!(info2 & (1 << 7));
2575 burst = CTX_TO_MAX_BURST(info2);
2576 maxp = MAX_PACKET_DECODED(info2);
2577
2578 avg = EP_AVG_TRB_LENGTH(tx_info);
2579
2580 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2581 xhci_ep_state_string(ep_state), mult,
2582 max_pstr, lsa ? "LSA " : "");
2583
2584 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2585 (1 << interval) * 125, esit, cerr);
2586
2587 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2588 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2589 burst, maxp, deq);
2590
2591 ret += sprintf(str + ret, "avg trb len %d", avg);
2592
2593 return str;
2594}
2595
2596#endif
2597