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24#ifndef _UAPI_VC4_DRM_H_
25#define _UAPI_VC4_DRM_H_
26
27#include "drm.h"
28
29#if defined(__cplusplus)
30extern "C" {
31#endif
32
33#define DRM_VC4_SUBMIT_CL 0x00
34#define DRM_VC4_WAIT_SEQNO 0x01
35#define DRM_VC4_WAIT_BO 0x02
36#define DRM_VC4_CREATE_BO 0x03
37#define DRM_VC4_MMAP_BO 0x04
38#define DRM_VC4_CREATE_SHADER_BO 0x05
39#define DRM_VC4_GET_HANG_STATE 0x06
40#define DRM_VC4_GET_PARAM 0x07
41#define DRM_VC4_SET_TILING 0x08
42#define DRM_VC4_GET_TILING 0x09
43#define DRM_VC4_LABEL_BO 0x0a
44#define DRM_VC4_GEM_MADVISE 0x0b
45#define DRM_VC4_PERFMON_CREATE 0x0c
46#define DRM_VC4_PERFMON_DESTROY 0x0d
47#define DRM_VC4_PERFMON_GET_VALUES 0x0e
48
49#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
50#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
51#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
52#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
53#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
54#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
55#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
56#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
57#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
58#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
59#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
60#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
61#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
62#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
63#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
64
65struct drm_vc4_submit_rcl_surface {
66 __u32 hindex;
67 __u32 offset;
68
69
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71
72 __u16 bits;
73
74#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
75 __u16 flags;
76};
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90
91struct drm_vc4_submit_cl {
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98
99 __u64 bin_cl;
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109
110 __u64 shader_rec;
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125
126 __u64 uniforms;
127 __u64 bo_handles;
128
129
130 __u32 bin_cl_size;
131
132 __u32 shader_rec_size;
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138
139 __u32 shader_rec_count;
140
141 __u32 uniforms_size;
142
143
144 __u32 bo_handle_count;
145
146
147 __u16 width;
148 __u16 height;
149 __u8 min_x_tile;
150 __u8 min_y_tile;
151 __u8 max_x_tile;
152 __u8 max_y_tile;
153 struct drm_vc4_submit_rcl_surface color_read;
154 struct drm_vc4_submit_rcl_surface color_write;
155 struct drm_vc4_submit_rcl_surface zs_read;
156 struct drm_vc4_submit_rcl_surface zs_write;
157 struct drm_vc4_submit_rcl_surface msaa_color_write;
158 struct drm_vc4_submit_rcl_surface msaa_zs_write;
159 __u32 clear_color[2];
160 __u32 clear_z;
161 __u8 clear_s;
162
163 __u32 pad:24;
164
165#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
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172
173#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
174#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
175#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
176 __u32 flags;
177
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180
181 __u64 seqno;
182
183
184 __u32 perfmonid;
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189
190 __u32 pad2;
191};
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200struct drm_vc4_wait_seqno {
201 __u64 seqno;
202 __u64 timeout_ns;
203};
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213struct drm_vc4_wait_bo {
214 __u32 handle;
215 __u32 pad;
216 __u64 timeout_ns;
217};
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225struct drm_vc4_create_bo {
226 __u32 size;
227 __u32 flags;
228
229 __u32 handle;
230 __u32 pad;
231};
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243
244struct drm_vc4_mmap_bo {
245
246 __u32 handle;
247 __u32 flags;
248
249 __u64 offset;
250};
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260struct drm_vc4_create_shader_bo {
261
262 __u32 size;
263
264 __u32 flags;
265
266
267 __u64 data;
268
269
270 __u32 handle;
271
272 __u32 pad;
273};
274
275struct drm_vc4_get_hang_state_bo {
276 __u32 handle;
277 __u32 paddr;
278 __u32 size;
279 __u32 pad;
280};
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286struct drm_vc4_get_hang_state {
287
288 __u64 bo;
289
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293 __u32 bo_count;
294
295 __u32 start_bin, start_render;
296
297 __u32 ct0ca, ct0ea;
298 __u32 ct1ca, ct1ea;
299 __u32 ct0cs, ct1cs;
300 __u32 ct0ra0, ct1ra0;
301
302 __u32 bpca, bpcs;
303 __u32 bpoa, bpos;
304
305 __u32 vpmbase;
306
307 __u32 dbge;
308 __u32 fdbgo;
309 __u32 fdbgb;
310 __u32 fdbgr;
311 __u32 fdbgs;
312 __u32 errstat;
313
314
315 __u32 pad[16];
316};
317
318#define DRM_VC4_PARAM_V3D_IDENT0 0
319#define DRM_VC4_PARAM_V3D_IDENT1 1
320#define DRM_VC4_PARAM_V3D_IDENT2 2
321#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
322#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
323#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
324#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
325#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7
326#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8
327
328struct drm_vc4_get_param {
329 __u32 param;
330 __u32 pad;
331 __u64 value;
332};
333
334struct drm_vc4_get_tiling {
335 __u32 handle;
336 __u32 flags;
337 __u64 modifier;
338};
339
340struct drm_vc4_set_tiling {
341 __u32 handle;
342 __u32 flags;
343 __u64 modifier;
344};
345
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349struct drm_vc4_label_bo {
350 __u32 handle;
351 __u32 len;
352 __u64 name;
353};
354
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358
359#define VC4_MADV_WILLNEED 0
360#define VC4_MADV_DONTNEED 1
361#define __VC4_MADV_PURGED 2
362#define __VC4_MADV_NOTSUPP 3
363
364struct drm_vc4_gem_madvise {
365 __u32 handle;
366 __u32 madv;
367 __u32 retained;
368 __u32 pad;
369};
370
371enum {
372 VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
373 VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
374 VC4_PERFCNT_FEP_CLIPPED_QUADS,
375 VC4_PERFCNT_FEP_VALID_QUADS,
376 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
377 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
378 VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
379 VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
380 VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
381 VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
382 VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
383 VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
384 VC4_PERFCNT_PSE_PRIMS_REVERSED,
385 VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
386 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
387 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
388 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
389 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
390 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
391 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
392 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
393 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
394 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
395 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
396 VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
397 VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
398 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
399 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
400 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
401 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
402 VC4_PERFCNT_NUM_EVENTS,
403};
404
405#define DRM_VC4_MAX_PERF_COUNTERS 16
406
407struct drm_vc4_perfmon_create {
408 __u32 id;
409 __u32 ncounters;
410 __u8 events[DRM_VC4_MAX_PERF_COUNTERS];
411};
412
413struct drm_vc4_perfmon_destroy {
414 __u32 id;
415};
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426struct drm_vc4_perfmon_get_values {
427 __u32 id;
428 __u64 values_ptr;
429};
430
431#if defined(__cplusplus)
432}
433#endif
434
435#endif
436