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23#ifndef KFD_IOCTL_H_INCLUDED
24#define KFD_IOCTL_H_INCLUDED
25
26#include <drm/drm.h>
27#include <linux/ioctl.h>
28
29#define KFD_IOCTL_MAJOR_VERSION 1
30#define KFD_IOCTL_MINOR_VERSION 1
31
32struct kfd_ioctl_get_version_args {
33 __u32 major_version;
34 __u32 minor_version;
35};
36
37
38#define KFD_IOC_QUEUE_TYPE_COMPUTE 0
39#define KFD_IOC_QUEUE_TYPE_SDMA 1
40#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
41
42#define KFD_MAX_QUEUE_PERCENTAGE 100
43#define KFD_MAX_QUEUE_PRIORITY 15
44
45struct kfd_ioctl_create_queue_args {
46 __u64 ring_base_address;
47 __u64 write_pointer_address;
48 __u64 read_pointer_address;
49 __u64 doorbell_offset;
50
51 __u32 ring_size;
52 __u32 gpu_id;
53 __u32 queue_type;
54 __u32 queue_percentage;
55 __u32 queue_priority;
56 __u32 queue_id;
57
58 __u64 eop_buffer_address;
59 __u64 eop_buffer_size;
60 __u64 ctx_save_restore_address;
61 __u32 ctx_save_restore_size;
62 __u32 ctl_stack_size;
63};
64
65struct kfd_ioctl_destroy_queue_args {
66 __u32 queue_id;
67 __u32 pad;
68};
69
70struct kfd_ioctl_update_queue_args {
71 __u64 ring_base_address;
72
73 __u32 queue_id;
74 __u32 ring_size;
75 __u32 queue_percentage;
76 __u32 queue_priority;
77};
78
79
80#define KFD_IOC_CACHE_POLICY_COHERENT 0
81#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
82
83struct kfd_ioctl_set_memory_policy_args {
84 __u64 alternate_aperture_base;
85 __u64 alternate_aperture_size;
86
87 __u32 gpu_id;
88 __u32 default_policy;
89 __u32 alternate_policy;
90 __u32 pad;
91};
92
93
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96
97
98
99
100struct kfd_ioctl_get_clock_counters_args {
101 __u64 gpu_clock_counter;
102 __u64 cpu_clock_counter;
103 __u64 system_clock_counter;
104 __u64 system_clock_freq;
105
106 __u32 gpu_id;
107 __u32 pad;
108};
109
110struct kfd_process_device_apertures {
111 __u64 lds_base;
112 __u64 lds_limit;
113 __u64 scratch_base;
114 __u64 scratch_limit;
115 __u64 gpuvm_base;
116 __u64 gpuvm_limit;
117 __u32 gpu_id;
118 __u32 pad;
119};
120
121
122
123
124
125
126#define NUM_OF_SUPPORTED_GPUS 7
127struct kfd_ioctl_get_process_apertures_args {
128 struct kfd_process_device_apertures
129 process_apertures[NUM_OF_SUPPORTED_GPUS];
130
131
132 __u32 num_of_nodes;
133 __u32 pad;
134};
135
136struct kfd_ioctl_get_process_apertures_new_args {
137
138
139
140 __u64 kfd_process_device_apertures_ptr;
141
142
143
144
145 __u32 num_of_nodes;
146 __u32 pad;
147};
148
149#define MAX_ALLOWED_NUM_POINTS 100
150#define MAX_ALLOWED_AW_BUFF_SIZE 4096
151#define MAX_ALLOWED_WAC_BUFF_SIZE 128
152
153struct kfd_ioctl_dbg_register_args {
154 __u32 gpu_id;
155 __u32 pad;
156};
157
158struct kfd_ioctl_dbg_unregister_args {
159 __u32 gpu_id;
160 __u32 pad;
161};
162
163struct kfd_ioctl_dbg_address_watch_args {
164 __u64 content_ptr;
165 __u32 gpu_id;
166 __u32 buf_size_in_bytes;
167};
168
169struct kfd_ioctl_dbg_wave_control_args {
170 __u64 content_ptr;
171 __u32 gpu_id;
172 __u32 buf_size_in_bytes;
173};
174
175
176#define KFD_IOC_EVENT_SIGNAL 0
177#define KFD_IOC_EVENT_NODECHANGE 1
178#define KFD_IOC_EVENT_DEVICESTATECHANGE 2
179#define KFD_IOC_EVENT_HW_EXCEPTION 3
180#define KFD_IOC_EVENT_SYSTEM_EVENT 4
181#define KFD_IOC_EVENT_DEBUG_EVENT 5
182#define KFD_IOC_EVENT_PROFILE_EVENT 6
183#define KFD_IOC_EVENT_QUEUE_EVENT 7
184#define KFD_IOC_EVENT_MEMORY 8
185
186#define KFD_IOC_WAIT_RESULT_COMPLETE 0
187#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
188#define KFD_IOC_WAIT_RESULT_FAIL 2
189
190#define KFD_SIGNAL_EVENT_LIMIT 4096
191
192struct kfd_ioctl_create_event_args {
193 __u64 event_page_offset;
194 __u32 event_trigger_data;
195 __u32 event_type;
196 __u32 auto_reset;
197 __u32 node_id;
198
199 __u32 event_id;
200 __u32 event_slot_index;
201};
202
203struct kfd_ioctl_destroy_event_args {
204 __u32 event_id;
205 __u32 pad;
206};
207
208struct kfd_ioctl_set_event_args {
209 __u32 event_id;
210 __u32 pad;
211};
212
213struct kfd_ioctl_reset_event_args {
214 __u32 event_id;
215 __u32 pad;
216};
217
218struct kfd_memory_exception_failure {
219 __u32 NotPresent;
220 __u32 ReadOnly;
221 __u32 NoExecute;
222 __u32 pad;
223};
224
225
226struct kfd_hsa_memory_exception_data {
227 struct kfd_memory_exception_failure failure;
228 __u64 va;
229 __u32 gpu_id;
230 __u32 pad;
231};
232
233
234struct kfd_event_data {
235 union {
236 struct kfd_hsa_memory_exception_data memory_exception_data;
237 };
238 __u64 kfd_event_data_ext;
239
240 __u32 event_id;
241 __u32 pad;
242};
243
244struct kfd_ioctl_wait_events_args {
245 __u64 events_ptr;
246
247 __u32 num_events;
248 __u32 wait_for_all;
249 __u32 timeout;
250 __u32 wait_result;
251};
252
253struct kfd_ioctl_set_scratch_backing_va_args {
254 __u64 va_addr;
255 __u32 gpu_id;
256 __u32 pad;
257};
258
259struct kfd_ioctl_get_tile_config_args {
260
261 __u64 tile_config_ptr;
262
263 __u64 macro_tile_config_ptr;
264
265
266
267 __u32 num_tile_configs;
268
269
270
271 __u32 num_macro_tile_configs;
272
273 __u32 gpu_id;
274 __u32 gb_addr_config;
275 __u32 num_banks;
276 __u32 num_ranks;
277
278
279
280};
281
282struct kfd_ioctl_set_trap_handler_args {
283 __u64 tba_addr;
284 __u64 tma_addr;
285 __u32 gpu_id;
286 __u32 pad;
287};
288
289struct kfd_ioctl_acquire_vm_args {
290 __u32 drm_fd;
291 __u32 gpu_id;
292};
293
294
295#define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
296#define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
297#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
298#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
299
300#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
301#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
302#define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
303#define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
304#define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
305#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
306
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318
319struct kfd_ioctl_alloc_memory_of_gpu_args {
320 __u64 va_addr;
321 __u64 size;
322 __u64 handle;
323 __u64 mmap_offset;
324 __u32 gpu_id;
325 __u32 flags;
326};
327
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330
331
332struct kfd_ioctl_free_memory_of_gpu_args {
333 __u64 handle;
334};
335
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350
351struct kfd_ioctl_map_memory_to_gpu_args {
352 __u64 handle;
353 __u64 device_ids_array_ptr;
354 __u32 n_devices;
355 __u32 n_success;
356};
357
358
359
360
361
362struct kfd_ioctl_unmap_memory_from_gpu_args {
363 __u64 handle;
364 __u64 device_ids_array_ptr;
365 __u32 n_devices;
366 __u32 n_success;
367};
368
369#define AMDKFD_IOCTL_BASE 'K'
370#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
371#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
372#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
373#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
374
375#define AMDKFD_IOC_GET_VERSION \
376 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
377
378#define AMDKFD_IOC_CREATE_QUEUE \
379 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
380
381#define AMDKFD_IOC_DESTROY_QUEUE \
382 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
383
384#define AMDKFD_IOC_SET_MEMORY_POLICY \
385 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
386
387#define AMDKFD_IOC_GET_CLOCK_COUNTERS \
388 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
389
390#define AMDKFD_IOC_GET_PROCESS_APERTURES \
391 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
392
393#define AMDKFD_IOC_UPDATE_QUEUE \
394 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
395
396#define AMDKFD_IOC_CREATE_EVENT \
397 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
398
399#define AMDKFD_IOC_DESTROY_EVENT \
400 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
401
402#define AMDKFD_IOC_SET_EVENT \
403 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
404
405#define AMDKFD_IOC_RESET_EVENT \
406 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
407
408#define AMDKFD_IOC_WAIT_EVENTS \
409 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
410
411#define AMDKFD_IOC_DBG_REGISTER \
412 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
413
414#define AMDKFD_IOC_DBG_UNREGISTER \
415 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
416
417#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
418 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
419
420#define AMDKFD_IOC_DBG_WAVE_CONTROL \
421 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
422
423#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
424 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
425
426#define AMDKFD_IOC_GET_TILE_CONFIG \
427 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
428
429#define AMDKFD_IOC_SET_TRAP_HANDLER \
430 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
431
432#define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
433 AMDKFD_IOWR(0x14, \
434 struct kfd_ioctl_get_process_apertures_new_args)
435
436#define AMDKFD_IOC_ACQUIRE_VM \
437 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
438
439#define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
440 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
441
442#define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
443 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
444
445#define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
446 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
447
448#define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
449 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
450
451#define AMDKFD_COMMAND_START 0x01
452#define AMDKFD_COMMAND_END 0x1A
453
454#endif
455