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37#include <linux/delay.h>
38#include <linux/interrupt.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/dma-mapping.h>
42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
46#include <linux/mutex.h>
47#include <linux/io.h>
48#include <linux/pm_runtime.h>
49#include <linux/clocksource.h>
50#include <linux/time.h>
51#include <linux/completion.h>
52
53#ifdef CONFIG_X86
54
55#include <asm/pgtable.h>
56#include <asm/set_memory.h>
57#include <asm/cpufeature.h>
58#endif
59#include <sound/core.h>
60#include <sound/initval.h>
61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
63#include <linux/vgaarb.h>
64#include <linux/vga_switcheroo.h>
65#include <linux/firmware.h>
66#include "hda_codec.h"
67#include "hda_controller.h"
68#include "hda_intel.h"
69
70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
73
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
80 POS_FIX_SKL,
81};
82
83
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94
95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102
103#define VIA_HDAC_DEVICE_ID 0x3288
104
105
106
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
122
123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
126static char *model[SNDRV_CARDS];
127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
130static int probe_only[SNDRV_CARDS];
131static int jackpoll_ms[SNDRV_CARDS];
132static int single_cmd = -1;
133static int enable_msi = -1;
134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
137#ifdef CONFIG_SND_HDA_INPUT_BEEP
138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
141
142module_param_array(index, int, NULL, 0444);
143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
144module_param_array(id, charp, NULL, 0444);
145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
149MODULE_PARM_DESC(model, "Use the given board model.");
150module_param_array(position_fix, int, NULL, 0444);
151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
155module_param_array(probe_mask, int, NULL, 0444);
156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
157module_param_array(probe_only, int, NULL, 0444);
158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
161module_param(single_cmd, bint, 0444);
162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
164module_param(enable_msi, bint, 0444);
165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
170#ifdef CONFIG_SND_HDA_INPUT_BEEP
171module_param_array(beep_mode, bool, NULL, 0444);
172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
173 "(0=off, 1=on) (default=1).");
174#endif
175
176#ifdef CONFIG_PM
177static int param_set_xint(const char *val, const struct kernel_param *kp);
178static const struct kernel_param_ops param_ops_xint = {
179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
185module_param(power_save, xint, 0644);
186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
188
189static bool pm_blacklist = true;
190module_param(pm_blacklist, bool, 0644);
191MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
192
193
194
195
196
197static bool power_save_controller = 1;
198module_param(power_save_controller, bool, 0644);
199MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
200#else
201#define power_save 0
202#endif
203
204static int align_buffer_size = -1;
205module_param(align_buffer_size, bint, 0644);
206MODULE_PARM_DESC(align_buffer_size,
207 "Force buffer and period sizes to be multiple of 128 bytes.");
208
209#ifdef CONFIG_X86
210static int hda_snoop = -1;
211module_param_named(snoop, hda_snoop, bint, 0444);
212MODULE_PARM_DESC(snoop, "Enable/disable snooping");
213#else
214#define hda_snoop true
215#endif
216
217
218MODULE_LICENSE("GPL");
219MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
220 "{Intel, ICH6M},"
221 "{Intel, ICH7},"
222 "{Intel, ESB2},"
223 "{Intel, ICH8},"
224 "{Intel, ICH9},"
225 "{Intel, ICH10},"
226 "{Intel, PCH},"
227 "{Intel, CPT},"
228 "{Intel, PPT},"
229 "{Intel, LPT},"
230 "{Intel, LPT_LP},"
231 "{Intel, WPT_LP},"
232 "{Intel, SPT},"
233 "{Intel, SPT_LP},"
234 "{Intel, HPT},"
235 "{Intel, PBG},"
236 "{Intel, SCH},"
237 "{ATI, SB450},"
238 "{ATI, SB600},"
239 "{ATI, RS600},"
240 "{ATI, RS690},"
241 "{ATI, RS780},"
242 "{ATI, R600},"
243 "{ATI, RV630},"
244 "{ATI, RV610},"
245 "{ATI, RV670},"
246 "{ATI, RV635},"
247 "{ATI, RV620},"
248 "{ATI, RV770},"
249 "{VIA, VT8251},"
250 "{VIA, VT8237A},"
251 "{SiS, SIS966},"
252 "{ULI, M5461}}");
253MODULE_DESCRIPTION("Intel HDA driver");
254
255#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
256#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
257#define SUPPORT_VGA_SWITCHEROO
258#endif
259#endif
260
261
262
263
264
265
266enum {
267 AZX_DRIVER_ICH,
268 AZX_DRIVER_PCH,
269 AZX_DRIVER_SCH,
270 AZX_DRIVER_SKL,
271 AZX_DRIVER_HDMI,
272 AZX_DRIVER_ATI,
273 AZX_DRIVER_ATIHDMI,
274 AZX_DRIVER_ATIHDMI_NS,
275 AZX_DRIVER_VIA,
276 AZX_DRIVER_SIS,
277 AZX_DRIVER_ULI,
278 AZX_DRIVER_NVIDIA,
279 AZX_DRIVER_TERA,
280 AZX_DRIVER_CTX,
281 AZX_DRIVER_CTHDA,
282 AZX_DRIVER_CMEDIA,
283 AZX_DRIVER_GENERIC,
284 AZX_NUM_DRIVERS,
285};
286
287#define azx_get_snoop_type(chip) \
288 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
289#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
290
291
292#define AZX_DCAPS_INTEL_ICH \
293 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
294
295
296#define AZX_DCAPS_INTEL_PCH_BASE \
297 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
299
300
301#define AZX_DCAPS_INTEL_PCH_NOPM \
302 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
303
304
305
306#define AZX_DCAPS_INTEL_PCH \
307 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
308
309
310#define AZX_DCAPS_INTEL_HASWELL \
311 ( AZX_DCAPS_COUNT_LPIB_DELAY |\
312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
313 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
314
315
316#define AZX_DCAPS_INTEL_BROADWELL \
317 ( AZX_DCAPS_POSFIX_LPIB |\
318 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
319 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
320
321#define AZX_DCAPS_INTEL_BAYTRAIL \
322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
323 AZX_DCAPS_I915_POWERWELL)
324
325#define AZX_DCAPS_INTEL_BRASWELL \
326 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
327 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
328
329#define AZX_DCAPS_INTEL_SKYLAKE \
330 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
331 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
332 AZX_DCAPS_I915_POWERWELL)
333
334#define AZX_DCAPS_INTEL_BROXTON \
335 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
336 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
337 AZX_DCAPS_I915_POWERWELL)
338
339
340#define AZX_DCAPS_PRESET_ATI_SB \
341 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
342 AZX_DCAPS_SNOOP_TYPE(ATI))
343
344
345#define AZX_DCAPS_PRESET_ATI_HDMI \
346 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
347 AZX_DCAPS_NO_MSI64)
348
349
350#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
351 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
352
353
354#define AZX_DCAPS_PRESET_NVIDIA \
355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
356 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
357
358#define AZX_DCAPS_PRESET_CTHDA \
359 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
360 AZX_DCAPS_NO_64BIT |\
361 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
362
363
364
365
366#ifdef SUPPORT_VGA_SWITCHEROO
367#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
368#else
369#define use_vga_switcheroo(chip) 0
370#endif
371
372#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
373 ((pci)->device == 0x0c0c) || \
374 ((pci)->device == 0x0d0c) || \
375 ((pci)->device == 0x160c))
376
377#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
378#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
379
380static char *driver_short_names[] = {
381 [AZX_DRIVER_ICH] = "HDA Intel",
382 [AZX_DRIVER_PCH] = "HDA Intel PCH",
383 [AZX_DRIVER_SCH] = "HDA Intel MID",
384 [AZX_DRIVER_SKL] = "HDA Intel PCH",
385 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
386 [AZX_DRIVER_ATI] = "HDA ATI SB",
387 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
388 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
389 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
390 [AZX_DRIVER_SIS] = "HDA SIS966",
391 [AZX_DRIVER_ULI] = "HDA ULI M5461",
392 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
393 [AZX_DRIVER_TERA] = "HDA Teradici",
394 [AZX_DRIVER_CTX] = "HDA Creative",
395 [AZX_DRIVER_CTHDA] = "HDA Creative",
396 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
397 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
398};
399
400#ifdef CONFIG_X86
401static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
402{
403 int pages;
404
405 if (azx_snoop(chip))
406 return;
407 if (!dmab || !dmab->area || !dmab->bytes)
408 return;
409
410#ifdef CONFIG_SND_DMA_SGBUF
411 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
412 struct snd_sg_buf *sgbuf = dmab->private_data;
413 if (chip->driver_type == AZX_DRIVER_CMEDIA)
414 return;
415 if (on)
416 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
417 else
418 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
419 return;
420 }
421#endif
422
423 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
424 if (on)
425 set_memory_wc((unsigned long)dmab->area, pages);
426 else
427 set_memory_wb((unsigned long)dmab->area, pages);
428}
429
430static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
431 bool on)
432{
433 __mark_pages_wc(chip, buf, on);
434}
435static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
436 struct snd_pcm_substream *substream, bool on)
437{
438 if (azx_dev->wc_marked != on) {
439 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
440 azx_dev->wc_marked = on;
441 }
442}
443#else
444
445static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
446 bool on)
447{
448}
449static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
450 struct snd_pcm_substream *substream, bool on)
451{
452}
453#endif
454
455static int azx_acquire_irq(struct azx *chip, int do_disconnect);
456
457
458
459
460
461static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
462 unsigned char mask, unsigned char val)
463{
464 unsigned char data;
465
466 pci_read_config_byte(pci, reg, &data);
467 data &= ~mask;
468 data |= (val & mask);
469 pci_write_config_byte(pci, reg, data);
470}
471
472static void azx_init_pci(struct azx *chip)
473{
474 int snoop_type = azx_get_snoop_type(chip);
475
476
477
478
479
480
481
482 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
483 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
484 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
485 }
486
487
488
489
490 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
491 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
492 azx_snoop(chip));
493 update_pci_byte(chip->pci,
494 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
495 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
496 }
497
498
499 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
500 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
501 azx_snoop(chip));
502 update_pci_byte(chip->pci,
503 NVIDIA_HDA_TRANSREG_ADDR,
504 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
505 update_pci_byte(chip->pci,
506 NVIDIA_HDA_ISTRM_COH,
507 0x01, NVIDIA_HDA_ENABLE_COHBIT);
508 update_pci_byte(chip->pci,
509 NVIDIA_HDA_OSTRM_COH,
510 0x01, NVIDIA_HDA_ENABLE_COHBIT);
511 }
512
513
514 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
515 unsigned short snoop;
516 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
517 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
518 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
519 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
520 if (!azx_snoop(chip))
521 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
522 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
523 pci_read_config_word(chip->pci,
524 INTEL_SCH_HDA_DEVC, &snoop);
525 }
526 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
527 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
528 "Disabled" : "Enabled");
529 }
530}
531
532
533
534
535
536
537
538
539static void bxt_reduce_dma_latency(struct azx *chip)
540{
541 u32 val;
542
543 val = azx_readl(chip, VS_EM4L);
544 val &= (0x3 << 20);
545 azx_writel(chip, VS_EM4L, val);
546}
547
548
549
550
551
552
553
554
555
556
557static int intel_get_lctl_scf(struct azx *chip)
558{
559 struct hdac_bus *bus = azx_bus(chip);
560 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
561 u32 val, t;
562 int i;
563
564 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
565
566 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
567 t = preferred_bits[i];
568 if (val & (1 << t))
569 return t;
570 }
571
572 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
573 return 0;
574}
575
576static int intel_ml_lctl_set_power(struct azx *chip, int state)
577{
578 struct hdac_bus *bus = azx_bus(chip);
579 u32 val;
580 int timeout;
581
582
583
584
585
586 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
587 val &= ~AZX_MLCTL_SPA;
588 val |= state << AZX_MLCTL_SPA_SHIFT;
589 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
590
591 timeout = 50;
592 while (timeout) {
593 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
594 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
595 return 0;
596 timeout--;
597 udelay(10);
598 }
599
600 return -1;
601}
602
603static void intel_init_lctl(struct azx *chip)
604{
605 struct hdac_bus *bus = azx_bus(chip);
606 u32 val;
607 int ret;
608
609
610 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
611
612 if ((val & ML_LCTL_SCF_MASK) != 0)
613 return;
614
615
616
617
618
619 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
620 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
621 return;
622
623
624 ret = intel_ml_lctl_set_power(chip, 0);
625 udelay(100);
626 if (ret)
627 goto set_spa;
628
629
630 val &= ~ML_LCTL_SCF_MASK;
631 val |= intel_get_lctl_scf(chip);
632 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
633
634set_spa:
635
636 intel_ml_lctl_set_power(chip, 1);
637 udelay(100);
638}
639
640static void hda_intel_init_chip(struct azx *chip, bool full_reset)
641{
642 struct hdac_bus *bus = azx_bus(chip);
643 struct pci_dev *pci = chip->pci;
644 u32 val;
645
646 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
647 snd_hdac_set_codec_wakeup(bus, true);
648 if (chip->driver_type == AZX_DRIVER_SKL) {
649 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
650 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
651 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
652 }
653 azx_init_chip(chip, full_reset);
654 if (chip->driver_type == AZX_DRIVER_SKL) {
655 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
656 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
657 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
658 }
659 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
660 snd_hdac_set_codec_wakeup(bus, false);
661
662
663 if (IS_BXT(pci))
664 bxt_reduce_dma_latency(chip);
665
666 if (bus->mlcap != NULL)
667 intel_init_lctl(chip);
668}
669
670
671static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
672 unsigned int pos)
673{
674 struct snd_pcm_substream *substream = azx_dev->core.substream;
675 int stream = substream->stream;
676 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
677 int delay;
678
679 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
680 delay = pos - lpib_pos;
681 else
682 delay = lpib_pos - pos;
683 if (delay < 0) {
684 if (delay >= azx_dev->core.delay_negative_threshold)
685 delay = 0;
686 else
687 delay += azx_dev->core.bufsize;
688 }
689
690 if (delay >= azx_dev->core.period_bytes) {
691 dev_info(chip->card->dev,
692 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
693 delay, azx_dev->core.period_bytes);
694 delay = 0;
695 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
696 chip->get_delay[stream] = NULL;
697 }
698
699 return bytes_to_frames(substream->runtime, delay);
700}
701
702static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
703
704
705static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
706{
707 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
708 int ok;
709
710 ok = azx_position_ok(chip, azx_dev);
711 if (ok == 1) {
712 azx_dev->irq_pending = 0;
713 return ok;
714 } else if (ok == 0) {
715
716 azx_dev->irq_pending = 1;
717 schedule_work(&hda->irq_pending_work);
718 }
719 return 0;
720}
721
722
723static int azx_intel_link_power(struct azx *chip, bool enable)
724{
725 struct hdac_bus *bus = azx_bus(chip);
726
727 return snd_hdac_display_power(bus, enable);
728}
729
730
731
732
733
734
735
736
737
738
739static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
740{
741 struct snd_pcm_substream *substream = azx_dev->core.substream;
742 int stream = substream->stream;
743 u32 wallclk;
744 unsigned int pos;
745
746 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
747 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
748 return -1;
749
750 if (chip->get_position[stream])
751 pos = chip->get_position[stream](chip, azx_dev);
752 else {
753 pos = azx_get_pos_posbuf(chip, azx_dev);
754 if (!pos || pos == (u32)-1) {
755 dev_info(chip->card->dev,
756 "Invalid position buffer, using LPIB read method instead.\n");
757 chip->get_position[stream] = azx_get_pos_lpib;
758 if (chip->get_position[0] == azx_get_pos_lpib &&
759 chip->get_position[1] == azx_get_pos_lpib)
760 azx_bus(chip)->use_posbuf = false;
761 pos = azx_get_pos_lpib(chip, azx_dev);
762 chip->get_delay[stream] = NULL;
763 } else {
764 chip->get_position[stream] = azx_get_pos_posbuf;
765 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
766 chip->get_delay[stream] = azx_get_delay_from_lpib;
767 }
768 }
769
770 if (pos >= azx_dev->core.bufsize)
771 pos = 0;
772
773 if (WARN_ONCE(!azx_dev->core.period_bytes,
774 "hda-intel: zero azx_dev->period_bytes"))
775 return -1;
776 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
777 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
778
779 return chip->bdl_pos_adj ? 0 : -1;
780 azx_dev->core.start_wallclk += wallclk;
781 return 1;
782}
783
784
785
786
787static void azx_irq_pending_work(struct work_struct *work)
788{
789 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
790 struct azx *chip = &hda->chip;
791 struct hdac_bus *bus = azx_bus(chip);
792 struct hdac_stream *s;
793 int pending, ok;
794
795 if (!hda->irq_pending_warned) {
796 dev_info(chip->card->dev,
797 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
798 chip->card->number);
799 hda->irq_pending_warned = 1;
800 }
801
802 for (;;) {
803 pending = 0;
804 spin_lock_irq(&bus->reg_lock);
805 list_for_each_entry(s, &bus->stream_list, list) {
806 struct azx_dev *azx_dev = stream_to_azx_dev(s);
807 if (!azx_dev->irq_pending ||
808 !s->substream ||
809 !s->running)
810 continue;
811 ok = azx_position_ok(chip, azx_dev);
812 if (ok > 0) {
813 azx_dev->irq_pending = 0;
814 spin_unlock(&bus->reg_lock);
815 snd_pcm_period_elapsed(s->substream);
816 spin_lock(&bus->reg_lock);
817 } else if (ok < 0) {
818 pending = 0;
819 } else
820 pending++;
821 }
822 spin_unlock_irq(&bus->reg_lock);
823 if (!pending)
824 return;
825 msleep(1);
826 }
827}
828
829
830static void azx_clear_irq_pending(struct azx *chip)
831{
832 struct hdac_bus *bus = azx_bus(chip);
833 struct hdac_stream *s;
834
835 spin_lock_irq(&bus->reg_lock);
836 list_for_each_entry(s, &bus->stream_list, list) {
837 struct azx_dev *azx_dev = stream_to_azx_dev(s);
838 azx_dev->irq_pending = 0;
839 }
840 spin_unlock_irq(&bus->reg_lock);
841}
842
843static int azx_acquire_irq(struct azx *chip, int do_disconnect)
844{
845 struct hdac_bus *bus = azx_bus(chip);
846
847 if (request_irq(chip->pci->irq, azx_interrupt,
848 chip->msi ? 0 : IRQF_SHARED,
849 chip->card->irq_descr, chip)) {
850 dev_err(chip->card->dev,
851 "unable to grab IRQ %d, disabling device\n",
852 chip->pci->irq);
853 if (do_disconnect)
854 snd_card_disconnect(chip->card);
855 return -1;
856 }
857 bus->irq = chip->pci->irq;
858 pci_intx(chip->pci, !chip->msi);
859 return 0;
860}
861
862
863static unsigned int azx_via_get_position(struct azx *chip,
864 struct azx_dev *azx_dev)
865{
866 unsigned int link_pos, mini_pos, bound_pos;
867 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
868 unsigned int fifo_size;
869
870 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
871 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
872
873 return link_pos;
874 }
875
876
877
878
879
880 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
881 mod_dma_pos %= azx_dev->core.period_bytes;
882
883
884
885
886 fifo_size = readw(azx_bus(chip)->remap_addr +
887 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
888
889 if (azx_dev->insufficient) {
890
891 if (link_pos <= fifo_size)
892 return 0;
893
894 azx_dev->insufficient = 0;
895 }
896
897 if (link_pos <= fifo_size)
898 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
899 else
900 mini_pos = link_pos - fifo_size;
901
902
903 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
904 mod_link_pos = link_pos % azx_dev->core.period_bytes;
905 if (mod_link_pos >= fifo_size)
906 bound_pos = link_pos - mod_link_pos;
907 else if (mod_dma_pos >= mod_mini_pos)
908 bound_pos = mini_pos - mod_mini_pos;
909 else {
910 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
911 if (bound_pos >= azx_dev->core.bufsize)
912 bound_pos = 0;
913 }
914
915
916 return bound_pos + mod_dma_pos;
917}
918
919static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
920 struct azx_dev *azx_dev)
921{
922 return _snd_hdac_chip_readl(azx_bus(chip),
923 AZX_REG_VS_SDXDPIB_XBASE +
924 (AZX_REG_VS_SDXDPIB_XINTERVAL *
925 azx_dev->core.index));
926}
927
928
929static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
930{
931
932 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
933 return azx_skl_get_dpib_pos(chip, azx_dev);
934
935
936
937
938
939 udelay(20);
940 azx_skl_get_dpib_pos(chip, azx_dev);
941 return azx_get_pos_posbuf(chip, azx_dev);
942}
943
944#ifdef CONFIG_PM
945static DEFINE_MUTEX(card_list_lock);
946static LIST_HEAD(card_list);
947
948static void azx_add_card_list(struct azx *chip)
949{
950 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
951 mutex_lock(&card_list_lock);
952 list_add(&hda->list, &card_list);
953 mutex_unlock(&card_list_lock);
954}
955
956static void azx_del_card_list(struct azx *chip)
957{
958 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
959 mutex_lock(&card_list_lock);
960 list_del_init(&hda->list);
961 mutex_unlock(&card_list_lock);
962}
963
964
965static int param_set_xint(const char *val, const struct kernel_param *kp)
966{
967 struct hda_intel *hda;
968 struct azx *chip;
969 int prev = power_save;
970 int ret = param_set_int(val, kp);
971
972 if (ret || prev == power_save)
973 return ret;
974
975 mutex_lock(&card_list_lock);
976 list_for_each_entry(hda, &card_list, list) {
977 chip = &hda->chip;
978 if (!hda->probe_continued || chip->disabled)
979 continue;
980 snd_hda_set_power_save(&chip->bus, power_save * 1000);
981 }
982 mutex_unlock(&card_list_lock);
983 return 0;
984}
985#else
986#define azx_add_card_list(chip)
987#define azx_del_card_list(chip)
988#endif
989
990#ifdef CONFIG_PM_SLEEP
991
992
993
994static int azx_suspend(struct device *dev)
995{
996 struct snd_card *card = dev_get_drvdata(dev);
997 struct azx *chip;
998 struct hda_intel *hda;
999 struct hdac_bus *bus;
1000
1001 if (!card)
1002 return 0;
1003
1004 chip = card->private_data;
1005 hda = container_of(chip, struct hda_intel, chip);
1006 if (chip->disabled || hda->init_failed || !chip->running)
1007 return 0;
1008
1009 bus = azx_bus(chip);
1010 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1011 azx_clear_irq_pending(chip);
1012 azx_stop_chip(chip);
1013 azx_enter_link_reset(chip);
1014 if (bus->irq >= 0) {
1015 free_irq(bus->irq, chip);
1016 bus->irq = -1;
1017 }
1018
1019 if (chip->msi)
1020 pci_disable_msi(chip->pci);
1021 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1022 && hda->need_i915_power)
1023 snd_hdac_display_power(bus, false);
1024
1025 trace_azx_suspend(chip);
1026 return 0;
1027}
1028
1029static int azx_resume(struct device *dev)
1030{
1031 struct pci_dev *pci = to_pci_dev(dev);
1032 struct snd_card *card = dev_get_drvdata(dev);
1033 struct azx *chip;
1034 struct hda_intel *hda;
1035 struct hdac_bus *bus;
1036
1037 if (!card)
1038 return 0;
1039
1040 chip = card->private_data;
1041 hda = container_of(chip, struct hda_intel, chip);
1042 bus = azx_bus(chip);
1043 if (chip->disabled || hda->init_failed || !chip->running)
1044 return 0;
1045
1046 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1047 snd_hdac_display_power(bus, true);
1048 if (hda->need_i915_power)
1049 snd_hdac_i915_set_bclk(bus);
1050 }
1051
1052 if (chip->msi)
1053 if (pci_enable_msi(pci) < 0)
1054 chip->msi = 0;
1055 if (azx_acquire_irq(chip, 1) < 0)
1056 return -EIO;
1057 azx_init_pci(chip);
1058
1059 hda_intel_init_chip(chip, true);
1060
1061
1062 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1063 !hda->need_i915_power)
1064 snd_hdac_display_power(bus, false);
1065
1066 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1067
1068 trace_azx_resume(chip);
1069 return 0;
1070}
1071
1072
1073
1074
1075static int azx_freeze_noirq(struct device *dev)
1076{
1077 struct snd_card *card = dev_get_drvdata(dev);
1078 struct azx *chip = card->private_data;
1079 struct pci_dev *pci = to_pci_dev(dev);
1080
1081 if (chip->driver_type == AZX_DRIVER_SKL)
1082 pci_set_power_state(pci, PCI_D3hot);
1083
1084 return 0;
1085}
1086
1087static int azx_thaw_noirq(struct device *dev)
1088{
1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip = card->private_data;
1091 struct pci_dev *pci = to_pci_dev(dev);
1092
1093 if (chip->driver_type == AZX_DRIVER_SKL)
1094 pci_set_power_state(pci, PCI_D0);
1095
1096 return 0;
1097}
1098#endif
1099
1100#ifdef CONFIG_PM
1101static int azx_runtime_suspend(struct device *dev)
1102{
1103 struct snd_card *card = dev_get_drvdata(dev);
1104 struct azx *chip;
1105 struct hda_intel *hda;
1106
1107 if (!card)
1108 return 0;
1109
1110 chip = card->private_data;
1111 hda = container_of(chip, struct hda_intel, chip);
1112 if (chip->disabled || hda->init_failed)
1113 return 0;
1114
1115 if (!azx_has_pm_runtime(chip))
1116 return 0;
1117
1118
1119 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1120 STATESTS_INT_MASK);
1121
1122 azx_stop_chip(chip);
1123 azx_enter_link_reset(chip);
1124 azx_clear_irq_pending(chip);
1125 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1126 && hda->need_i915_power)
1127 snd_hdac_display_power(azx_bus(chip), false);
1128
1129 trace_azx_runtime_suspend(chip);
1130 return 0;
1131}
1132
1133static int azx_runtime_resume(struct device *dev)
1134{
1135 struct snd_card *card = dev_get_drvdata(dev);
1136 struct azx *chip;
1137 struct hda_intel *hda;
1138 struct hdac_bus *bus;
1139 struct hda_codec *codec;
1140 int status;
1141
1142 if (!card)
1143 return 0;
1144
1145 chip = card->private_data;
1146 hda = container_of(chip, struct hda_intel, chip);
1147 bus = azx_bus(chip);
1148 if (chip->disabled || hda->init_failed)
1149 return 0;
1150
1151 if (!azx_has_pm_runtime(chip))
1152 return 0;
1153
1154 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1155 snd_hdac_display_power(bus, true);
1156 if (hda->need_i915_power)
1157 snd_hdac_i915_set_bclk(bus);
1158 }
1159
1160
1161 status = azx_readw(chip, STATESTS);
1162
1163 azx_init_pci(chip);
1164 hda_intel_init_chip(chip, true);
1165
1166 if (status) {
1167 list_for_each_codec(codec, &chip->bus)
1168 if (status & (1 << codec->addr))
1169 schedule_delayed_work(&codec->jackpoll_work,
1170 codec->jackpoll_interval);
1171 }
1172
1173
1174 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1175 ~STATESTS_INT_MASK);
1176
1177
1178 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1179 !hda->need_i915_power)
1180 snd_hdac_display_power(bus, false);
1181
1182 trace_azx_runtime_resume(chip);
1183 return 0;
1184}
1185
1186static int azx_runtime_idle(struct device *dev)
1187{
1188 struct snd_card *card = dev_get_drvdata(dev);
1189 struct azx *chip;
1190 struct hda_intel *hda;
1191
1192 if (!card)
1193 return 0;
1194
1195 chip = card->private_data;
1196 hda = container_of(chip, struct hda_intel, chip);
1197 if (chip->disabled || hda->init_failed)
1198 return 0;
1199
1200 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1201 azx_bus(chip)->codec_powered || !chip->running)
1202 return -EBUSY;
1203
1204 return 0;
1205}
1206
1207static const struct dev_pm_ops azx_pm = {
1208 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1209#ifdef CONFIG_PM_SLEEP
1210 .freeze_noirq = azx_freeze_noirq,
1211 .thaw_noirq = azx_thaw_noirq,
1212#endif
1213 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1214};
1215
1216#define AZX_PM_OPS &azx_pm
1217#else
1218#define AZX_PM_OPS NULL
1219#endif
1220
1221
1222static int azx_probe_continue(struct azx *chip);
1223
1224#ifdef SUPPORT_VGA_SWITCHEROO
1225static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1226
1227static void azx_vs_set_state(struct pci_dev *pci,
1228 enum vga_switcheroo_state state)
1229{
1230 struct snd_card *card = pci_get_drvdata(pci);
1231 struct azx *chip = card->private_data;
1232 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1233 struct hda_codec *codec;
1234 bool disabled;
1235
1236 wait_for_completion(&hda->probe_wait);
1237 if (hda->init_failed)
1238 return;
1239
1240 disabled = (state == VGA_SWITCHEROO_OFF);
1241 if (chip->disabled == disabled)
1242 return;
1243
1244 if (!hda->probe_continued) {
1245 chip->disabled = disabled;
1246 if (!disabled) {
1247 dev_info(chip->card->dev,
1248 "Start delayed initialization\n");
1249 if (azx_probe_continue(chip) < 0) {
1250 dev_err(chip->card->dev, "initialization error\n");
1251 hda->init_failed = true;
1252 }
1253 }
1254 } else {
1255 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1256 disabled ? "Disabling" : "Enabling");
1257 if (disabled) {
1258 list_for_each_codec(codec, &chip->bus) {
1259 pm_runtime_suspend(hda_codec_dev(codec));
1260 pm_runtime_disable(hda_codec_dev(codec));
1261 }
1262 pm_runtime_suspend(card->dev);
1263 pm_runtime_disable(card->dev);
1264
1265
1266
1267 pci->current_state = PCI_D3cold;
1268 chip->disabled = true;
1269 if (snd_hda_lock_devices(&chip->bus))
1270 dev_warn(chip->card->dev,
1271 "Cannot lock devices!\n");
1272 } else {
1273 snd_hda_unlock_devices(&chip->bus);
1274 chip->disabled = false;
1275 pm_runtime_enable(card->dev);
1276 list_for_each_codec(codec, &chip->bus) {
1277 pm_runtime_enable(hda_codec_dev(codec));
1278 pm_runtime_resume(hda_codec_dev(codec));
1279 }
1280 }
1281 }
1282}
1283
1284static bool azx_vs_can_switch(struct pci_dev *pci)
1285{
1286 struct snd_card *card = pci_get_drvdata(pci);
1287 struct azx *chip = card->private_data;
1288 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1289
1290 wait_for_completion(&hda->probe_wait);
1291 if (hda->init_failed)
1292 return false;
1293 if (chip->disabled || !hda->probe_continued)
1294 return true;
1295 if (snd_hda_lock_devices(&chip->bus))
1296 return false;
1297 snd_hda_unlock_devices(&chip->bus);
1298 return true;
1299}
1300
1301static void init_vga_switcheroo(struct azx *chip)
1302{
1303 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1304 struct pci_dev *p = get_bound_vga(chip->pci);
1305 if (p) {
1306 dev_info(chip->card->dev,
1307 "Handle vga_switcheroo audio client\n");
1308 hda->use_vga_switcheroo = 1;
1309 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1310 pci_dev_put(p);
1311 }
1312}
1313
1314static const struct vga_switcheroo_client_ops azx_vs_ops = {
1315 .set_gpu_state = azx_vs_set_state,
1316 .can_switch = azx_vs_can_switch,
1317};
1318
1319static int register_vga_switcheroo(struct azx *chip)
1320{
1321 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1322 int err;
1323
1324 if (!hda->use_vga_switcheroo)
1325 return 0;
1326
1327
1328
1329 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1330 VGA_SWITCHEROO_DIS);
1331 if (err < 0)
1332 return err;
1333 hda->vga_switcheroo_registered = 1;
1334
1335 return 0;
1336}
1337#else
1338#define init_vga_switcheroo(chip)
1339#define register_vga_switcheroo(chip) 0
1340#define check_hdmi_disabled(pci) false
1341#endif
1342
1343
1344
1345
1346static int azx_free(struct azx *chip)
1347{
1348 struct pci_dev *pci = chip->pci;
1349 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1350 struct hdac_bus *bus = azx_bus(chip);
1351
1352 if (azx_has_pm_runtime(chip) && chip->running)
1353 pm_runtime_get_noresume(&pci->dev);
1354
1355 azx_del_card_list(chip);
1356
1357 hda->init_failed = 1;
1358 complete_all(&hda->probe_wait);
1359
1360 if (use_vga_switcheroo(hda)) {
1361 if (chip->disabled && hda->probe_continued)
1362 snd_hda_unlock_devices(&chip->bus);
1363 if (hda->vga_switcheroo_registered)
1364 vga_switcheroo_unregister_client(chip->pci);
1365 }
1366
1367 if (bus->chip_init) {
1368 azx_clear_irq_pending(chip);
1369 azx_stop_all_streams(chip);
1370 azx_stop_chip(chip);
1371 }
1372
1373 if (bus->irq >= 0)
1374 free_irq(bus->irq, (void*)chip);
1375 if (chip->msi)
1376 pci_disable_msi(chip->pci);
1377 iounmap(bus->remap_addr);
1378
1379 azx_free_stream_pages(chip);
1380 azx_free_streams(chip);
1381 snd_hdac_bus_exit(bus);
1382
1383 if (chip->region_requested)
1384 pci_release_regions(chip->pci);
1385
1386 pci_disable_device(chip->pci);
1387#ifdef CONFIG_SND_HDA_PATCH_LOADER
1388 release_firmware(chip->fw);
1389#endif
1390
1391 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1392 if (hda->need_i915_power)
1393 snd_hdac_display_power(bus, false);
1394 }
1395 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1396 snd_hdac_i915_exit(bus);
1397 kfree(hda);
1398
1399 return 0;
1400}
1401
1402static int azx_dev_disconnect(struct snd_device *device)
1403{
1404 struct azx *chip = device->device_data;
1405
1406 chip->bus.shutdown = 1;
1407 return 0;
1408}
1409
1410static int azx_dev_free(struct snd_device *device)
1411{
1412 return azx_free(device->device_data);
1413}
1414
1415#ifdef SUPPORT_VGA_SWITCHEROO
1416
1417
1418
1419static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1420{
1421 struct pci_dev *p;
1422
1423
1424 switch (pci->vendor) {
1425 case PCI_VENDOR_ID_ATI:
1426 case PCI_VENDOR_ID_AMD:
1427 case PCI_VENDOR_ID_NVIDIA:
1428 if (pci->devfn == 1) {
1429 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1430 pci->bus->number, 0);
1431 if (p) {
1432 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1433 return p;
1434 pci_dev_put(p);
1435 }
1436 }
1437 break;
1438 }
1439 return NULL;
1440}
1441
1442static bool check_hdmi_disabled(struct pci_dev *pci)
1443{
1444 bool vga_inactive = false;
1445 struct pci_dev *p = get_bound_vga(pci);
1446
1447 if (p) {
1448 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1449 vga_inactive = true;
1450 pci_dev_put(p);
1451 }
1452 return vga_inactive;
1453}
1454#endif
1455
1456
1457
1458
1459static struct snd_pci_quirk position_fix_list[] = {
1460 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1461 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1462 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1463 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1464 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1465 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1466 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1467 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1468 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1469 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1470 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1471 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1472 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1473 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1474 {}
1475};
1476
1477static int check_position_fix(struct azx *chip, int fix)
1478{
1479 const struct snd_pci_quirk *q;
1480
1481 switch (fix) {
1482 case POS_FIX_AUTO:
1483 case POS_FIX_LPIB:
1484 case POS_FIX_POSBUF:
1485 case POS_FIX_VIACOMBO:
1486 case POS_FIX_COMBO:
1487 case POS_FIX_SKL:
1488 return fix;
1489 }
1490
1491 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1492 if (q) {
1493 dev_info(chip->card->dev,
1494 "position_fix set to %d for device %04x:%04x\n",
1495 q->value, q->subvendor, q->subdevice);
1496 return q->value;
1497 }
1498
1499
1500 if (chip->driver_type == AZX_DRIVER_VIA) {
1501 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1502 return POS_FIX_VIACOMBO;
1503 }
1504 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1505 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1506 return POS_FIX_LPIB;
1507 }
1508 if (chip->driver_type == AZX_DRIVER_SKL) {
1509 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1510 return POS_FIX_SKL;
1511 }
1512 return POS_FIX_AUTO;
1513}
1514
1515static void assign_position_fix(struct azx *chip, int fix)
1516{
1517 static azx_get_pos_callback_t callbacks[] = {
1518 [POS_FIX_AUTO] = NULL,
1519 [POS_FIX_LPIB] = azx_get_pos_lpib,
1520 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1521 [POS_FIX_VIACOMBO] = azx_via_get_position,
1522 [POS_FIX_COMBO] = azx_get_pos_lpib,
1523 [POS_FIX_SKL] = azx_get_pos_skl,
1524 };
1525
1526 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1527
1528
1529 if (fix == POS_FIX_COMBO)
1530 chip->get_position[1] = NULL;
1531
1532 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1533 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1534 chip->get_delay[0] = chip->get_delay[1] =
1535 azx_get_delay_from_lpib;
1536 }
1537
1538}
1539
1540
1541
1542
1543static struct snd_pci_quirk probe_mask_list[] = {
1544
1545
1546
1547 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1548 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1549 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1550
1551 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1552
1553 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1554
1555 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1556 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1557
1558 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1559 {}
1560};
1561
1562#define AZX_FORCE_CODEC_MASK 0x100
1563
1564static void check_probe_mask(struct azx *chip, int dev)
1565{
1566 const struct snd_pci_quirk *q;
1567
1568 chip->codec_probe_mask = probe_mask[dev];
1569 if (chip->codec_probe_mask == -1) {
1570 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1571 if (q) {
1572 dev_info(chip->card->dev,
1573 "probe_mask set to 0x%x for device %04x:%04x\n",
1574 q->value, q->subvendor, q->subdevice);
1575 chip->codec_probe_mask = q->value;
1576 }
1577 }
1578
1579
1580 if (chip->codec_probe_mask != -1 &&
1581 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1582 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1583 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1584 (int)azx_bus(chip)->codec_mask);
1585 }
1586}
1587
1588
1589
1590
1591static struct snd_pci_quirk msi_black_list[] = {
1592 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0),
1593 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0),
1594 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0),
1595 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0),
1596 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0),
1597 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0),
1598 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0),
1599 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0),
1600 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0),
1601 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0),
1602 {}
1603};
1604
1605static void check_msi(struct azx *chip)
1606{
1607 const struct snd_pci_quirk *q;
1608
1609 if (enable_msi >= 0) {
1610 chip->msi = !!enable_msi;
1611 return;
1612 }
1613 chip->msi = 1;
1614 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1615 if (q) {
1616 dev_info(chip->card->dev,
1617 "msi for device %04x:%04x set to %d\n",
1618 q->subvendor, q->subdevice, q->value);
1619 chip->msi = q->value;
1620 return;
1621 }
1622
1623
1624 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1625 dev_info(chip->card->dev, "Disabling MSI\n");
1626 chip->msi = 0;
1627 }
1628}
1629
1630
1631static void azx_check_snoop_available(struct azx *chip)
1632{
1633 int snoop = hda_snoop;
1634
1635 if (snoop >= 0) {
1636 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1637 snoop ? "snoop" : "non-snoop");
1638 chip->snoop = snoop;
1639 return;
1640 }
1641
1642 snoop = true;
1643 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1644 chip->driver_type == AZX_DRIVER_VIA) {
1645
1646
1647
1648 u8 val;
1649 pci_read_config_byte(chip->pci, 0x42, &val);
1650 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1651 chip->pci->revision == 0x20))
1652 snoop = false;
1653 }
1654
1655 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1656 snoop = false;
1657
1658 chip->snoop = snoop;
1659 if (!snoop)
1660 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1661}
1662
1663static void azx_probe_work(struct work_struct *work)
1664{
1665 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1666 azx_probe_continue(&hda->chip);
1667}
1668
1669static int default_bdl_pos_adj(struct azx *chip)
1670{
1671
1672 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1673 switch (chip->pci->device) {
1674 case 0x0f04:
1675 case 0x2284:
1676 return 32;
1677 }
1678 }
1679
1680 switch (chip->driver_type) {
1681 case AZX_DRIVER_ICH:
1682 case AZX_DRIVER_PCH:
1683 return 1;
1684 default:
1685 return 32;
1686 }
1687}
1688
1689
1690
1691
1692static const struct hdac_io_ops pci_hda_io_ops;
1693static const struct hda_controller_ops pci_hda_ops;
1694
1695static int azx_create(struct snd_card *card, struct pci_dev *pci,
1696 int dev, unsigned int driver_caps,
1697 struct azx **rchip)
1698{
1699 static struct snd_device_ops ops = {
1700 .dev_disconnect = azx_dev_disconnect,
1701 .dev_free = azx_dev_free,
1702 };
1703 struct hda_intel *hda;
1704 struct azx *chip;
1705 int err;
1706
1707 *rchip = NULL;
1708
1709 err = pci_enable_device(pci);
1710 if (err < 0)
1711 return err;
1712
1713 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1714 if (!hda) {
1715 pci_disable_device(pci);
1716 return -ENOMEM;
1717 }
1718
1719 chip = &hda->chip;
1720 mutex_init(&chip->open_mutex);
1721 chip->card = card;
1722 chip->pci = pci;
1723 chip->ops = &pci_hda_ops;
1724 chip->driver_caps = driver_caps;
1725 chip->driver_type = driver_caps & 0xff;
1726 check_msi(chip);
1727 chip->dev_index = dev;
1728 chip->jackpoll_ms = jackpoll_ms;
1729 INIT_LIST_HEAD(&chip->pcm_list);
1730 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1731 INIT_LIST_HEAD(&hda->list);
1732 init_vga_switcheroo(chip);
1733 init_completion(&hda->probe_wait);
1734
1735 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1736
1737 check_probe_mask(chip, dev);
1738
1739 if (single_cmd < 0)
1740 chip->fallback_to_single_cmd = 1;
1741 else
1742 chip->single_cmd = single_cmd;
1743
1744 azx_check_snoop_available(chip);
1745
1746 if (bdl_pos_adj[dev] < 0)
1747 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1748 else
1749 chip->bdl_pos_adj = bdl_pos_adj[dev];
1750
1751
1752 if (IS_CFL(pci))
1753 chip->polling_mode = 1;
1754
1755 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1756 if (err < 0) {
1757 kfree(hda);
1758 pci_disable_device(pci);
1759 return err;
1760 }
1761
1762 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1763 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1764 chip->bus.needs_damn_long_delay = 1;
1765 }
1766
1767 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1768 if (err < 0) {
1769 dev_err(card->dev, "Error creating device [card]!\n");
1770 azx_free(chip);
1771 return err;
1772 }
1773
1774
1775 INIT_WORK(&hda->probe_work, azx_probe_work);
1776
1777 *rchip = chip;
1778
1779 return 0;
1780}
1781
1782static int azx_first_init(struct azx *chip)
1783{
1784 int dev = chip->dev_index;
1785 struct pci_dev *pci = chip->pci;
1786 struct snd_card *card = chip->card;
1787 struct hdac_bus *bus = azx_bus(chip);
1788 int err;
1789 unsigned short gcap;
1790 unsigned int dma_bits = 64;
1791
1792#if BITS_PER_LONG != 64
1793
1794 if (chip->driver_type == AZX_DRIVER_ULI) {
1795 u16 tmp3;
1796 pci_read_config_word(pci, 0x40, &tmp3);
1797 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1798 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1799 }
1800#endif
1801
1802 err = pci_request_regions(pci, "ICH HD audio");
1803 if (err < 0)
1804 return err;
1805 chip->region_requested = 1;
1806
1807 bus->addr = pci_resource_start(pci, 0);
1808 bus->remap_addr = pci_ioremap_bar(pci, 0);
1809 if (bus->remap_addr == NULL) {
1810 dev_err(card->dev, "ioremap error\n");
1811 return -ENXIO;
1812 }
1813
1814 if (chip->driver_type == AZX_DRIVER_SKL)
1815 snd_hdac_bus_parse_capabilities(bus);
1816
1817
1818
1819
1820
1821
1822
1823 chip->gts_present = false;
1824
1825#ifdef CONFIG_X86
1826 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1827 chip->gts_present = true;
1828#endif
1829
1830 if (chip->msi) {
1831 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1832 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1833 pci->no_64bit_msi = true;
1834 }
1835 if (pci_enable_msi(pci) < 0)
1836 chip->msi = 0;
1837 }
1838
1839 if (azx_acquire_irq(chip, 0) < 0)
1840 return -EBUSY;
1841
1842 pci_set_master(pci);
1843 synchronize_irq(bus->irq);
1844
1845 gcap = azx_readw(chip, GCAP);
1846 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1847
1848
1849 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1850 dma_bits = 40;
1851
1852
1853 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1854 struct pci_dev *p_smbus;
1855 dma_bits = 40;
1856 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1857 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1858 NULL);
1859 if (p_smbus) {
1860 if (p_smbus->revision < 0x30)
1861 gcap &= ~AZX_GCAP_64OK;
1862 pci_dev_put(p_smbus);
1863 }
1864 }
1865
1866
1867 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1868 dma_bits = 40;
1869
1870
1871 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1872 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1873 gcap &= ~AZX_GCAP_64OK;
1874 }
1875
1876
1877 if (align_buffer_size >= 0)
1878 chip->align_buffer_size = !!align_buffer_size;
1879 else {
1880 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1881 chip->align_buffer_size = 0;
1882 else
1883 chip->align_buffer_size = 1;
1884 }
1885
1886
1887 if (!(gcap & AZX_GCAP_64OK))
1888 dma_bits = 32;
1889 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1890 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1891 } else {
1892 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1893 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1894 }
1895
1896
1897
1898
1899 chip->capture_streams = (gcap >> 8) & 0x0f;
1900 chip->playback_streams = (gcap >> 12) & 0x0f;
1901 if (!chip->playback_streams && !chip->capture_streams) {
1902
1903
1904 switch (chip->driver_type) {
1905 case AZX_DRIVER_ULI:
1906 chip->playback_streams = ULI_NUM_PLAYBACK;
1907 chip->capture_streams = ULI_NUM_CAPTURE;
1908 break;
1909 case AZX_DRIVER_ATIHDMI:
1910 case AZX_DRIVER_ATIHDMI_NS:
1911 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1912 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1913 break;
1914 case AZX_DRIVER_GENERIC:
1915 default:
1916 chip->playback_streams = ICH6_NUM_PLAYBACK;
1917 chip->capture_streams = ICH6_NUM_CAPTURE;
1918 break;
1919 }
1920 }
1921 chip->capture_index_offset = 0;
1922 chip->playback_index_offset = chip->capture_streams;
1923 chip->num_streams = chip->playback_streams + chip->capture_streams;
1924
1925
1926 if (chip->num_streams > 15 &&
1927 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1928 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1929 "forcing separate stream tags", chip->num_streams);
1930 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1931 }
1932
1933
1934 err = azx_init_streams(chip);
1935 if (err < 0)
1936 return err;
1937
1938 err = azx_alloc_stream_pages(chip);
1939 if (err < 0)
1940 return err;
1941
1942
1943 azx_init_pci(chip);
1944
1945 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1946 snd_hdac_i915_set_bclk(bus);
1947
1948 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1949
1950
1951 if (!azx_bus(chip)->codec_mask) {
1952 dev_err(card->dev, "no codecs found!\n");
1953 return -ENODEV;
1954 }
1955
1956 strcpy(card->driver, "HDA-Intel");
1957 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1958 sizeof(card->shortname));
1959 snprintf(card->longname, sizeof(card->longname),
1960 "%s at 0x%lx irq %i",
1961 card->shortname, bus->addr, bus->irq);
1962
1963 return 0;
1964}
1965
1966#ifdef CONFIG_SND_HDA_PATCH_LOADER
1967
1968static void azx_firmware_cb(const struct firmware *fw, void *context)
1969{
1970 struct snd_card *card = context;
1971 struct azx *chip = card->private_data;
1972 struct pci_dev *pci = chip->pci;
1973
1974 if (!fw) {
1975 dev_err(card->dev, "Cannot load firmware, aborting\n");
1976 goto error;
1977 }
1978
1979 chip->fw = fw;
1980 if (!chip->disabled) {
1981
1982 if (azx_probe_continue(chip))
1983 goto error;
1984 }
1985 return;
1986
1987 error:
1988 snd_card_free(card);
1989 pci_set_drvdata(pci, NULL);
1990}
1991#endif
1992
1993
1994
1995
1996
1997
1998static void pci_azx_writel(u32 value, u32 __iomem *addr)
1999{
2000 writel(value, addr);
2001}
2002
2003static u32 pci_azx_readl(u32 __iomem *addr)
2004{
2005 return readl(addr);
2006}
2007
2008static void pci_azx_writew(u16 value, u16 __iomem *addr)
2009{
2010 writew(value, addr);
2011}
2012
2013static u16 pci_azx_readw(u16 __iomem *addr)
2014{
2015 return readw(addr);
2016}
2017
2018static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2019{
2020 writeb(value, addr);
2021}
2022
2023static u8 pci_azx_readb(u8 __iomem *addr)
2024{
2025 return readb(addr);
2026}
2027
2028static int disable_msi_reset_irq(struct azx *chip)
2029{
2030 struct hdac_bus *bus = azx_bus(chip);
2031 int err;
2032
2033 free_irq(bus->irq, chip);
2034 bus->irq = -1;
2035 pci_disable_msi(chip->pci);
2036 chip->msi = 0;
2037 err = azx_acquire_irq(chip, 1);
2038 if (err < 0)
2039 return err;
2040
2041 return 0;
2042}
2043
2044
2045static int dma_alloc_pages(struct hdac_bus *bus,
2046 int type,
2047 size_t size,
2048 struct snd_dma_buffer *buf)
2049{
2050 struct azx *chip = bus_to_azx(bus);
2051 int err;
2052
2053 err = snd_dma_alloc_pages(type,
2054 bus->dev,
2055 size, buf);
2056 if (err < 0)
2057 return err;
2058 mark_pages_wc(chip, buf, true);
2059 return 0;
2060}
2061
2062static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2063{
2064 struct azx *chip = bus_to_azx(bus);
2065
2066 mark_pages_wc(chip, buf, false);
2067 snd_dma_free_pages(buf);
2068}
2069
2070static int substream_alloc_pages(struct azx *chip,
2071 struct snd_pcm_substream *substream,
2072 size_t size)
2073{
2074 struct azx_dev *azx_dev = get_azx_dev(substream);
2075 int ret;
2076
2077 mark_runtime_wc(chip, azx_dev, substream, false);
2078 ret = snd_pcm_lib_malloc_pages(substream, size);
2079 if (ret < 0)
2080 return ret;
2081 mark_runtime_wc(chip, azx_dev, substream, true);
2082 return 0;
2083}
2084
2085static int substream_free_pages(struct azx *chip,
2086 struct snd_pcm_substream *substream)
2087{
2088 struct azx_dev *azx_dev = get_azx_dev(substream);
2089 mark_runtime_wc(chip, azx_dev, substream, false);
2090 return snd_pcm_lib_free_pages(substream);
2091}
2092
2093static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2094 struct vm_area_struct *area)
2095{
2096#ifdef CONFIG_X86
2097 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2098 struct azx *chip = apcm->chip;
2099 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
2100 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2101#endif
2102}
2103
2104static const struct hdac_io_ops pci_hda_io_ops = {
2105 .reg_writel = pci_azx_writel,
2106 .reg_readl = pci_azx_readl,
2107 .reg_writew = pci_azx_writew,
2108 .reg_readw = pci_azx_readw,
2109 .reg_writeb = pci_azx_writeb,
2110 .reg_readb = pci_azx_readb,
2111 .dma_alloc_pages = dma_alloc_pages,
2112 .dma_free_pages = dma_free_pages,
2113};
2114
2115static const struct hda_controller_ops pci_hda_ops = {
2116 .disable_msi_reset_irq = disable_msi_reset_irq,
2117 .substream_alloc_pages = substream_alloc_pages,
2118 .substream_free_pages = substream_free_pages,
2119 .pcm_mmap_prepare = pcm_mmap_prepare,
2120 .position_check = azx_position_check,
2121 .link_power = azx_intel_link_power,
2122};
2123
2124static int azx_probe(struct pci_dev *pci,
2125 const struct pci_device_id *pci_id)
2126{
2127 static int dev;
2128 struct snd_card *card;
2129 struct hda_intel *hda;
2130 struct azx *chip;
2131 bool schedule_probe;
2132 int err;
2133
2134 if (dev >= SNDRV_CARDS)
2135 return -ENODEV;
2136 if (!enable[dev]) {
2137 dev++;
2138 return -ENOENT;
2139 }
2140
2141 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2142 0, &card);
2143 if (err < 0) {
2144 dev_err(&pci->dev, "Error creating card!\n");
2145 return err;
2146 }
2147
2148 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2149 if (err < 0)
2150 goto out_free;
2151 card->private_data = chip;
2152 hda = container_of(chip, struct hda_intel, chip);
2153
2154 pci_set_drvdata(pci, card);
2155
2156 err = register_vga_switcheroo(chip);
2157 if (err < 0) {
2158 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2159 goto out_free;
2160 }
2161
2162 if (check_hdmi_disabled(pci)) {
2163 dev_info(card->dev, "VGA controller is disabled\n");
2164 dev_info(card->dev, "Delaying initialization\n");
2165 chip->disabled = true;
2166 }
2167
2168 schedule_probe = !chip->disabled;
2169
2170#ifdef CONFIG_SND_HDA_PATCH_LOADER
2171 if (patch[dev] && *patch[dev]) {
2172 dev_info(card->dev, "Applying patch firmware '%s'\n",
2173 patch[dev]);
2174 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2175 &pci->dev, GFP_KERNEL, card,
2176 azx_firmware_cb);
2177 if (err < 0)
2178 goto out_free;
2179 schedule_probe = false;
2180 }
2181#endif
2182
2183#ifndef CONFIG_SND_HDA_I915
2184 if (CONTROLLER_IN_GPU(pci))
2185 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2186#endif
2187
2188 if (schedule_probe)
2189 schedule_work(&hda->probe_work);
2190
2191 dev++;
2192 if (chip->disabled)
2193 complete_all(&hda->probe_wait);
2194 return 0;
2195
2196out_free:
2197 snd_card_free(card);
2198 return err;
2199}
2200
2201#ifdef CONFIG_PM
2202
2203
2204
2205
2206
2207
2208static struct snd_pci_quirk power_save_blacklist[] = {
2209
2210 SND_PCI_QUIRK(0x1849, 0x0c0c, "Asrock B85M-ITX", 0),
2211
2212 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2213
2214 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2215
2216 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2217 {}
2218};
2219#endif
2220
2221
2222static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2223 [AZX_DRIVER_NVIDIA] = 8,
2224 [AZX_DRIVER_TERA] = 1,
2225};
2226
2227static int azx_probe_continue(struct azx *chip)
2228{
2229 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2230 struct hdac_bus *bus = azx_bus(chip);
2231 struct pci_dev *pci = chip->pci;
2232 struct hda_codec *codec;
2233 int dev = chip->dev_index;
2234 int val;
2235 int err;
2236
2237 hda->probe_continued = 1;
2238
2239
2240 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2241 err = snd_hdac_i915_init(bus);
2242 if (err < 0) {
2243
2244
2245
2246
2247
2248 if (CONTROLLER_IN_GPU(pci)) {
2249 dev_err(chip->card->dev,
2250 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2251 goto out_free;
2252 } else {
2253
2254 chip->driver_caps &=
2255 ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
2256 }
2257 }
2258 }
2259
2260
2261
2262
2263
2264
2265 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2266
2267 if (CONTROLLER_IN_GPU(pci))
2268 hda->need_i915_power = 1;
2269
2270 err = snd_hdac_display_power(bus, true);
2271 if (err < 0) {
2272 dev_err(chip->card->dev,
2273 "Cannot turn on display power on i915\n");
2274 goto i915_power_fail;
2275 }
2276 }
2277
2278 err = azx_first_init(chip);
2279 if (err < 0)
2280 goto out_free;
2281
2282#ifdef CONFIG_SND_HDA_INPUT_BEEP
2283 chip->beep_mode = beep_mode[dev];
2284#endif
2285
2286
2287 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2288 if (err < 0)
2289 goto out_free;
2290
2291#ifdef CONFIG_SND_HDA_PATCH_LOADER
2292 if (chip->fw) {
2293 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2294 chip->fw->data);
2295 if (err < 0)
2296 goto out_free;
2297#ifndef CONFIG_PM
2298 release_firmware(chip->fw);
2299 chip->fw = NULL;
2300#endif
2301 }
2302#endif
2303 if ((probe_only[dev] & 1) == 0) {
2304 err = azx_codec_configure(chip);
2305 if (err < 0)
2306 goto out_free;
2307 }
2308
2309 err = snd_card_register(chip->card);
2310 if (err < 0)
2311 goto out_free;
2312
2313 chip->running = 1;
2314 azx_add_card_list(chip);
2315
2316 val = power_save;
2317#ifdef CONFIG_PM
2318 if (pm_blacklist) {
2319 const struct snd_pci_quirk *q;
2320
2321 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2322 if (q && val) {
2323 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2324 q->subvendor, q->subdevice);
2325 val = 0;
2326 }
2327 }
2328#endif
2329
2330
2331
2332
2333 if (use_vga_switcheroo(hda))
2334 list_for_each_codec(codec, &chip->bus)
2335 codec->auto_runtime_pm = 1;
2336
2337 snd_hda_set_power_save(&chip->bus, val * 1000);
2338 if (azx_has_pm_runtime(chip))
2339 pm_runtime_put_autosuspend(&pci->dev);
2340
2341out_free:
2342 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2343 && !hda->need_i915_power)
2344 snd_hdac_display_power(bus, false);
2345
2346i915_power_fail:
2347 if (err < 0)
2348 hda->init_failed = 1;
2349 complete_all(&hda->probe_wait);
2350 return err;
2351}
2352
2353static void azx_remove(struct pci_dev *pci)
2354{
2355 struct snd_card *card = pci_get_drvdata(pci);
2356 struct azx *chip;
2357 struct hda_intel *hda;
2358
2359 if (card) {
2360
2361 chip = card->private_data;
2362 hda = container_of(chip, struct hda_intel, chip);
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374 device_unlock(&pci->dev);
2375 cancel_work_sync(&hda->probe_work);
2376 device_lock(&pci->dev);
2377
2378 snd_card_free(card);
2379 }
2380}
2381
2382static void azx_shutdown(struct pci_dev *pci)
2383{
2384 struct snd_card *card = pci_get_drvdata(pci);
2385 struct azx *chip;
2386
2387 if (!card)
2388 return;
2389 chip = card->private_data;
2390 if (chip && chip->running)
2391 azx_stop_chip(chip);
2392}
2393
2394
2395static const struct pci_device_id azx_ids[] = {
2396
2397 { PCI_DEVICE(0x8086, 0x1c20),
2398 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2399
2400 { PCI_DEVICE(0x8086, 0x1d20),
2401 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2402
2403 { PCI_DEVICE(0x8086, 0x1e20),
2404 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2405
2406 { PCI_DEVICE(0x8086, 0x8c20),
2407 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2408
2409 { PCI_DEVICE(0x8086, 0x8ca0),
2410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2411
2412 { PCI_DEVICE(0x8086, 0x8d20),
2413 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2414 { PCI_DEVICE(0x8086, 0x8d21),
2415 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2416
2417 { PCI_DEVICE(0x8086, 0xa1f0),
2418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2419 { PCI_DEVICE(0x8086, 0xa270),
2420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2421
2422 { PCI_DEVICE(0x8086, 0x9c20),
2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2424
2425 { PCI_DEVICE(0x8086, 0x9c21),
2426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2427
2428 { PCI_DEVICE(0x8086, 0x9ca0),
2429 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2430
2431 { PCI_DEVICE(0x8086, 0xa170),
2432 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2433
2434 { PCI_DEVICE(0x8086, 0x9d70),
2435 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2436
2437 { PCI_DEVICE(0x8086, 0xa171),
2438 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2439
2440 { PCI_DEVICE(0x8086, 0x9d71),
2441 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2442
2443 { PCI_DEVICE(0x8086, 0xa2f0),
2444 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2445
2446 { PCI_DEVICE(0x8086, 0xa348),
2447 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2448
2449 { PCI_DEVICE(0x8086, 0x9dc8),
2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2451
2452 { PCI_DEVICE(0x8086, 0x34c8),
2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2454
2455 { PCI_DEVICE(0x8086, 0x5a98),
2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2457
2458 { PCI_DEVICE(0x8086, 0x1a98),
2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2460
2461 { PCI_DEVICE(0x8086, 0x3198),
2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2463
2464 { PCI_DEVICE(0x8086, 0x0a0c),
2465 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2466 { PCI_DEVICE(0x8086, 0x0c0c),
2467 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2468 { PCI_DEVICE(0x8086, 0x0d0c),
2469 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2470
2471 { PCI_DEVICE(0x8086, 0x160c),
2472 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2473
2474 { PCI_DEVICE(0x8086, 0x3b56),
2475 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2476
2477 { PCI_DEVICE(0x8086, 0x811b),
2478 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2479
2480 { PCI_DEVICE(0x8086, 0x080a),
2481 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2482
2483 { PCI_DEVICE(0x8086, 0x0f04),
2484 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2485
2486 { PCI_DEVICE(0x8086, 0x2284),
2487 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2488
2489 { PCI_DEVICE(0x8086, 0x2668),
2490 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2491
2492 { PCI_DEVICE(0x8086, 0x27d8),
2493 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2494
2495 { PCI_DEVICE(0x8086, 0x269a),
2496 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2497
2498 { PCI_DEVICE(0x8086, 0x284b),
2499 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2500
2501 { PCI_DEVICE(0x8086, 0x293e),
2502 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2503
2504 { PCI_DEVICE(0x8086, 0x293f),
2505 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2506
2507 { PCI_DEVICE(0x8086, 0x3a3e),
2508 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2509
2510 { PCI_DEVICE(0x8086, 0x3a6e),
2511 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2512
2513 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2514 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2515 .class_mask = 0xffffff,
2516 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2517
2518 { PCI_DEVICE(0x1002, 0x437b),
2519 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2520 { PCI_DEVICE(0x1002, 0x4383),
2521 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2522
2523 { PCI_DEVICE(0x1022, 0x780d),
2524 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2525
2526 { PCI_DEVICE(0x1022, 0x15e3),
2527 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2528
2529 { PCI_DEVICE(0x1002, 0x0002),
2530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2531 { PCI_DEVICE(0x1002, 0x1308),
2532 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2533 { PCI_DEVICE(0x1002, 0x157a),
2534 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2535 { PCI_DEVICE(0x1002, 0x15b3),
2536 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2537 { PCI_DEVICE(0x1002, 0x793b),
2538 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2539 { PCI_DEVICE(0x1002, 0x7919),
2540 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2541 { PCI_DEVICE(0x1002, 0x960f),
2542 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2543 { PCI_DEVICE(0x1002, 0x970f),
2544 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2545 { PCI_DEVICE(0x1002, 0x9840),
2546 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2547 { PCI_DEVICE(0x1002, 0xaa00),
2548 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2549 { PCI_DEVICE(0x1002, 0xaa08),
2550 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2551 { PCI_DEVICE(0x1002, 0xaa10),
2552 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2553 { PCI_DEVICE(0x1002, 0xaa18),
2554 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2555 { PCI_DEVICE(0x1002, 0xaa20),
2556 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2557 { PCI_DEVICE(0x1002, 0xaa28),
2558 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2559 { PCI_DEVICE(0x1002, 0xaa30),
2560 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2561 { PCI_DEVICE(0x1002, 0xaa38),
2562 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2563 { PCI_DEVICE(0x1002, 0xaa40),
2564 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2565 { PCI_DEVICE(0x1002, 0xaa48),
2566 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2567 { PCI_DEVICE(0x1002, 0xaa50),
2568 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2569 { PCI_DEVICE(0x1002, 0xaa58),
2570 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2571 { PCI_DEVICE(0x1002, 0xaa60),
2572 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2573 { PCI_DEVICE(0x1002, 0xaa68),
2574 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2575 { PCI_DEVICE(0x1002, 0xaa80),
2576 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2577 { PCI_DEVICE(0x1002, 0xaa88),
2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2579 { PCI_DEVICE(0x1002, 0xaa90),
2580 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2581 { PCI_DEVICE(0x1002, 0xaa98),
2582 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2583 { PCI_DEVICE(0x1002, 0x9902),
2584 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2585 { PCI_DEVICE(0x1002, 0xaaa0),
2586 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2587 { PCI_DEVICE(0x1002, 0xaaa8),
2588 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2589 { PCI_DEVICE(0x1002, 0xaab0),
2590 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2591 { PCI_DEVICE(0x1002, 0xaac0),
2592 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2593 { PCI_DEVICE(0x1002, 0xaac8),
2594 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2595 { PCI_DEVICE(0x1002, 0xaad8),
2596 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2597 { PCI_DEVICE(0x1002, 0xaae8),
2598 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2599 { PCI_DEVICE(0x1002, 0xaae0),
2600 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2601 { PCI_DEVICE(0x1002, 0xaaf0),
2602 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2603
2604 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2605
2606 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2607
2608 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2609
2610 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2611
2612 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2613
2614 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2615 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2616 .class_mask = 0xffffff,
2617 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2618
2619 { PCI_DEVICE(0x6549, 0x1200),
2620 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2621 { PCI_DEVICE(0x6549, 0x2200),
2622 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2623
2624
2625 { PCI_DEVICE(0x1102, 0x0010),
2626 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2627 { PCI_DEVICE(0x1102, 0x0012),
2628 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2629#if !IS_ENABLED(CONFIG_SND_CTXFI)
2630
2631
2632
2633
2634 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2635 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2636 .class_mask = 0xffffff,
2637 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2638 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2639#else
2640
2641 { PCI_DEVICE(0x1102, 0x0009),
2642 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2643 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2644#endif
2645
2646 { PCI_DEVICE(0x13f6, 0x5011),
2647 .driver_data = AZX_DRIVER_CMEDIA |
2648 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2649
2650 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2651
2652 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2653
2654 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2655 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2656 .class_mask = 0xffffff,
2657 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2658 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2659 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2660 .class_mask = 0xffffff,
2661 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2662 { 0, }
2663};
2664MODULE_DEVICE_TABLE(pci, azx_ids);
2665
2666
2667static struct pci_driver azx_driver = {
2668 .name = KBUILD_MODNAME,
2669 .id_table = azx_ids,
2670 .probe = azx_probe,
2671 .remove = azx_remove,
2672 .shutdown = azx_shutdown,
2673 .driver = {
2674 .pm = AZX_PM_OPS,
2675 },
2676};
2677
2678module_pci_driver(azx_driver);
2679