linux/sound/pci/hda/patch_hdmi.c
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   1/*
   2 *
   3 *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
   4 *
   5 *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
   6 *  Copyright (c) 2006 ATI Technologies Inc.
   7 *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
   8 *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
   9 *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10 *
  11 *  Authors:
  12 *                      Wu Fengguang <wfg@linux.intel.com>
  13 *
  14 *  Maintained by:
  15 *                      Wu Fengguang <wfg@linux.intel.com>
  16 *
  17 *  This program is free software; you can redistribute it and/or modify it
  18 *  under the terms of the GNU General Public License as published by the Free
  19 *  Software Foundation; either version 2 of the License, or (at your option)
  20 *  any later version.
  21 *
  22 *  This program is distributed in the hope that it will be useful, but
  23 *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24 *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  25 *  for more details.
  26 *
  27 *  You should have received a copy of the GNU General Public License
  28 *  along with this program; if not, write to the Free Software Foundation,
  29 *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  30 */
  31
  32#include <linux/init.h>
  33#include <linux/delay.h>
  34#include <linux/slab.h>
  35#include <linux/module.h>
  36#include <sound/core.h>
  37#include <sound/jack.h>
  38#include <sound/asoundef.h>
  39#include <sound/tlv.h>
  40#include <sound/hdaudio.h>
  41#include <sound/hda_i915.h>
  42#include <sound/hda_chmap.h>
  43#include "hda_codec.h"
  44#include "hda_local.h"
  45#include "hda_jack.h"
  46
  47static bool static_hdmi_pcm;
  48module_param(static_hdmi_pcm, bool, 0644);
  49MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  50
  51#define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
  52#define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
  53#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  54#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
  55#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
  56#define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
  57                                ((codec)->core.vendor_id == 0x80862800))
  58#define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
  59#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  60                                || is_skylake(codec) || is_broxton(codec) \
  61                                || is_kabylake(codec)) || is_geminilake(codec) \
  62                                || is_cannonlake(codec)
  63#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  64#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  65#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  66
  67struct hdmi_spec_per_cvt {
  68        hda_nid_t cvt_nid;
  69        int assigned;
  70        unsigned int channels_min;
  71        unsigned int channels_max;
  72        u32 rates;
  73        u64 formats;
  74        unsigned int maxbps;
  75};
  76
  77/* max. connections to a widget */
  78#define HDA_MAX_CONNECTIONS     32
  79
  80struct hdmi_spec_per_pin {
  81        hda_nid_t pin_nid;
  82        int dev_id;
  83        /* pin idx, different device entries on the same pin use the same idx */
  84        int pin_nid_idx;
  85        int num_mux_nids;
  86        hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  87        int mux_idx;
  88        hda_nid_t cvt_nid;
  89
  90        struct hda_codec *codec;
  91        struct hdmi_eld sink_eld;
  92        struct mutex lock;
  93        struct delayed_work work;
  94        struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
  95        int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
  96        int repoll_count;
  97        bool setup; /* the stream has been set up by prepare callback */
  98        int channels; /* current number of channels */
  99        bool non_pcm;
 100        bool chmap_set;         /* channel-map override by ALSA API? */
 101        unsigned char chmap[8]; /* ALSA API channel-map */
 102#ifdef CONFIG_SND_PROC_FS
 103        struct snd_info_entry *proc_entry;
 104#endif
 105};
 106
 107/* operations used by generic code that can be overridden by patches */
 108struct hdmi_ops {
 109        int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
 110                           unsigned char *buf, int *eld_size);
 111
 112        void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
 113                                    int ca, int active_channels, int conn_type);
 114
 115        /* enable/disable HBR (HD passthrough) */
 116        int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
 117
 118        int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
 119                            hda_nid_t pin_nid, u32 stream_tag, int format);
 120
 121        void (*pin_cvt_fixup)(struct hda_codec *codec,
 122                              struct hdmi_spec_per_pin *per_pin,
 123                              hda_nid_t cvt_nid);
 124};
 125
 126struct hdmi_pcm {
 127        struct hda_pcm *pcm;
 128        struct snd_jack *jack;
 129        struct snd_kcontrol *eld_ctl;
 130};
 131
 132struct hdmi_spec {
 133        int num_cvts;
 134        struct snd_array cvts; /* struct hdmi_spec_per_cvt */
 135        hda_nid_t cvt_nids[4]; /* only for haswell fix */
 136
 137        /*
 138         * num_pins is the number of virtual pins
 139         * for example, there are 3 pins, and each pin
 140         * has 4 device entries, then the num_pins is 12
 141         */
 142        int num_pins;
 143        /*
 144         * num_nids is the number of real pins
 145         * In the above example, num_nids is 3
 146         */
 147        int num_nids;
 148        /*
 149         * dev_num is the number of device entries
 150         * on each pin.
 151         * In the above example, dev_num is 4
 152         */
 153        int dev_num;
 154        struct snd_array pins; /* struct hdmi_spec_per_pin */
 155        struct hdmi_pcm pcm_rec[16];
 156        struct mutex pcm_lock;
 157        /* pcm_bitmap means which pcms have been assigned to pins*/
 158        unsigned long pcm_bitmap;
 159        int pcm_used;   /* counter of pcm_rec[] */
 160        /* bitmap shows whether the pcm is opened in user space
 161         * bit 0 means the first playback PCM (PCM3);
 162         * bit 1 means the second playback PCM, and so on.
 163         */
 164        unsigned long pcm_in_use;
 165
 166        struct hdmi_eld temp_eld;
 167        struct hdmi_ops ops;
 168
 169        bool dyn_pin_out;
 170        bool dyn_pcm_assign;
 171        /*
 172         * Non-generic VIA/NVIDIA specific
 173         */
 174        struct hda_multi_out multiout;
 175        struct hda_pcm_stream pcm_playback;
 176
 177        /* i915/powerwell (Haswell+/Valleyview+) specific */
 178        bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
 179        struct i915_audio_component_audio_ops i915_audio_ops;
 180
 181        struct hdac_chmap chmap;
 182        hda_nid_t vendor_nid;
 183};
 184
 185#ifdef CONFIG_SND_HDA_I915
 186static inline bool codec_has_acomp(struct hda_codec *codec)
 187{
 188        struct hdmi_spec *spec = codec->spec;
 189        return spec->use_acomp_notifier;
 190}
 191#else
 192#define codec_has_acomp(codec)  false
 193#endif
 194
 195struct hdmi_audio_infoframe {
 196        u8 type; /* 0x84 */
 197        u8 ver;  /* 0x01 */
 198        u8 len;  /* 0x0a */
 199
 200        u8 checksum;
 201
 202        u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
 203        u8 SS01_SF24;
 204        u8 CXT04;
 205        u8 CA;
 206        u8 LFEPBL01_LSV36_DM_INH7;
 207};
 208
 209struct dp_audio_infoframe {
 210        u8 type; /* 0x84 */
 211        u8 len;  /* 0x1b */
 212        u8 ver;  /* 0x11 << 2 */
 213
 214        u8 CC02_CT47;   /* match with HDMI infoframe from this on */
 215        u8 SS01_SF24;
 216        u8 CXT04;
 217        u8 CA;
 218        u8 LFEPBL01_LSV36_DM_INH7;
 219};
 220
 221union audio_infoframe {
 222        struct hdmi_audio_infoframe hdmi;
 223        struct dp_audio_infoframe dp;
 224        u8 bytes[0];
 225};
 226
 227/*
 228 * HDMI routines
 229 */
 230
 231#define get_pin(spec, idx) \
 232        ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
 233#define get_cvt(spec, idx) \
 234        ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
 235/* obtain hdmi_pcm object assigned to idx */
 236#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
 237/* obtain hda_pcm object assigned to idx */
 238#define get_pcm_rec(spec, idx)  (get_hdmi_pcm(spec, idx)->pcm)
 239
 240static int pin_id_to_pin_index(struct hda_codec *codec,
 241                               hda_nid_t pin_nid, int dev_id)
 242{
 243        struct hdmi_spec *spec = codec->spec;
 244        int pin_idx;
 245        struct hdmi_spec_per_pin *per_pin;
 246
 247        /*
 248         * (dev_id == -1) means it is NON-MST pin
 249         * return the first virtual pin on this port
 250         */
 251        if (dev_id == -1)
 252                dev_id = 0;
 253
 254        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
 255                per_pin = get_pin(spec, pin_idx);
 256                if ((per_pin->pin_nid == pin_nid) &&
 257                        (per_pin->dev_id == dev_id))
 258                        return pin_idx;
 259        }
 260
 261        codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
 262        return -EINVAL;
 263}
 264
 265static int hinfo_to_pcm_index(struct hda_codec *codec,
 266                        struct hda_pcm_stream *hinfo)
 267{
 268        struct hdmi_spec *spec = codec->spec;
 269        int pcm_idx;
 270
 271        for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
 272                if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
 273                        return pcm_idx;
 274
 275        codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
 276        return -EINVAL;
 277}
 278
 279static int hinfo_to_pin_index(struct hda_codec *codec,
 280                              struct hda_pcm_stream *hinfo)
 281{
 282        struct hdmi_spec *spec = codec->spec;
 283        struct hdmi_spec_per_pin *per_pin;
 284        int pin_idx;
 285
 286        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
 287                per_pin = get_pin(spec, pin_idx);
 288                if (per_pin->pcm &&
 289                        per_pin->pcm->pcm->stream == hinfo)
 290                        return pin_idx;
 291        }
 292
 293        codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
 294        return -EINVAL;
 295}
 296
 297static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
 298                                                int pcm_idx)
 299{
 300        int i;
 301        struct hdmi_spec_per_pin *per_pin;
 302
 303        for (i = 0; i < spec->num_pins; i++) {
 304                per_pin = get_pin(spec, i);
 305                if (per_pin->pcm_idx == pcm_idx)
 306                        return per_pin;
 307        }
 308        return NULL;
 309}
 310
 311static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
 312{
 313        struct hdmi_spec *spec = codec->spec;
 314        int cvt_idx;
 315
 316        for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
 317                if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
 318                        return cvt_idx;
 319
 320        codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
 321        return -EINVAL;
 322}
 323
 324static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
 325                        struct snd_ctl_elem_info *uinfo)
 326{
 327        struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 328        struct hdmi_spec *spec = codec->spec;
 329        struct hdmi_spec_per_pin *per_pin;
 330        struct hdmi_eld *eld;
 331        int pcm_idx;
 332
 333        uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 334
 335        pcm_idx = kcontrol->private_value;
 336        mutex_lock(&spec->pcm_lock);
 337        per_pin = pcm_idx_to_pin(spec, pcm_idx);
 338        if (!per_pin) {
 339                /* no pin is bound to the pcm */
 340                uinfo->count = 0;
 341                mutex_unlock(&spec->pcm_lock);
 342                return 0;
 343        }
 344        eld = &per_pin->sink_eld;
 345        uinfo->count = eld->eld_valid ? eld->eld_size : 0;
 346        mutex_unlock(&spec->pcm_lock);
 347
 348        return 0;
 349}
 350
 351static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
 352                        struct snd_ctl_elem_value *ucontrol)
 353{
 354        struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 355        struct hdmi_spec *spec = codec->spec;
 356        struct hdmi_spec_per_pin *per_pin;
 357        struct hdmi_eld *eld;
 358        int pcm_idx;
 359
 360        pcm_idx = kcontrol->private_value;
 361        mutex_lock(&spec->pcm_lock);
 362        per_pin = pcm_idx_to_pin(spec, pcm_idx);
 363        if (!per_pin) {
 364                /* no pin is bound to the pcm */
 365                memset(ucontrol->value.bytes.data, 0,
 366                       ARRAY_SIZE(ucontrol->value.bytes.data));
 367                mutex_unlock(&spec->pcm_lock);
 368                return 0;
 369        }
 370        eld = &per_pin->sink_eld;
 371
 372        if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
 373            eld->eld_size > ELD_MAX_SIZE) {
 374                mutex_unlock(&spec->pcm_lock);
 375                snd_BUG();
 376                return -EINVAL;
 377        }
 378
 379        memset(ucontrol->value.bytes.data, 0,
 380               ARRAY_SIZE(ucontrol->value.bytes.data));
 381        if (eld->eld_valid)
 382                memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
 383                       eld->eld_size);
 384        mutex_unlock(&spec->pcm_lock);
 385
 386        return 0;
 387}
 388
 389static const struct snd_kcontrol_new eld_bytes_ctl = {
 390        .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 391        .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 392        .name = "ELD",
 393        .info = hdmi_eld_ctl_info,
 394        .get = hdmi_eld_ctl_get,
 395};
 396
 397static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
 398                        int device)
 399{
 400        struct snd_kcontrol *kctl;
 401        struct hdmi_spec *spec = codec->spec;
 402        int err;
 403
 404        kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
 405        if (!kctl)
 406                return -ENOMEM;
 407        kctl->private_value = pcm_idx;
 408        kctl->id.device = device;
 409
 410        /* no pin nid is associated with the kctl now
 411         * tbd: associate pin nid to eld ctl later
 412         */
 413        err = snd_hda_ctl_add(codec, 0, kctl);
 414        if (err < 0)
 415                return err;
 416
 417        get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
 418        return 0;
 419}
 420
 421#ifdef BE_PARANOID
 422static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 423                                int *packet_index, int *byte_index)
 424{
 425        int val;
 426
 427        val = snd_hda_codec_read(codec, pin_nid, 0,
 428                                 AC_VERB_GET_HDMI_DIP_INDEX, 0);
 429
 430        *packet_index = val >> 5;
 431        *byte_index = val & 0x1f;
 432}
 433#endif
 434
 435static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 436                                int packet_index, int byte_index)
 437{
 438        int val;
 439
 440        val = (packet_index << 5) | (byte_index & 0x1f);
 441
 442        snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
 443}
 444
 445static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
 446                                unsigned char val)
 447{
 448        snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
 449}
 450
 451static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
 452{
 453        struct hdmi_spec *spec = codec->spec;
 454        int pin_out;
 455
 456        /* Unmute */
 457        if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 458                snd_hda_codec_write(codec, pin_nid, 0,
 459                                AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
 460
 461        if (spec->dyn_pin_out)
 462                /* Disable pin out until stream is active */
 463                pin_out = 0;
 464        else
 465                /* Enable pin out: some machines with GM965 gets broken output
 466                 * when the pin is disabled or changed while using with HDMI
 467                 */
 468                pin_out = PIN_OUT;
 469
 470        snd_hda_codec_write(codec, pin_nid, 0,
 471                            AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
 472}
 473
 474/*
 475 * ELD proc files
 476 */
 477
 478#ifdef CONFIG_SND_PROC_FS
 479static void print_eld_info(struct snd_info_entry *entry,
 480                           struct snd_info_buffer *buffer)
 481{
 482        struct hdmi_spec_per_pin *per_pin = entry->private_data;
 483
 484        mutex_lock(&per_pin->lock);
 485        snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
 486        mutex_unlock(&per_pin->lock);
 487}
 488
 489static void write_eld_info(struct snd_info_entry *entry,
 490                           struct snd_info_buffer *buffer)
 491{
 492        struct hdmi_spec_per_pin *per_pin = entry->private_data;
 493
 494        mutex_lock(&per_pin->lock);
 495        snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
 496        mutex_unlock(&per_pin->lock);
 497}
 498
 499static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
 500{
 501        char name[32];
 502        struct hda_codec *codec = per_pin->codec;
 503        struct snd_info_entry *entry;
 504        int err;
 505
 506        snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
 507        err = snd_card_proc_new(codec->card, name, &entry);
 508        if (err < 0)
 509                return err;
 510
 511        snd_info_set_text_ops(entry, per_pin, print_eld_info);
 512        entry->c.text.write = write_eld_info;
 513        entry->mode |= S_IWUSR;
 514        per_pin->proc_entry = entry;
 515
 516        return 0;
 517}
 518
 519static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 520{
 521        if (!per_pin->codec->bus->shutdown) {
 522                snd_info_free_entry(per_pin->proc_entry);
 523                per_pin->proc_entry = NULL;
 524        }
 525}
 526#else
 527static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
 528                               int index)
 529{
 530        return 0;
 531}
 532static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 533{
 534}
 535#endif
 536
 537/*
 538 * Audio InfoFrame routines
 539 */
 540
 541/*
 542 * Enable Audio InfoFrame Transmission
 543 */
 544static void hdmi_start_infoframe_trans(struct hda_codec *codec,
 545                                       hda_nid_t pin_nid)
 546{
 547        hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 548        snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 549                                                AC_DIPXMIT_BEST);
 550}
 551
 552/*
 553 * Disable Audio InfoFrame Transmission
 554 */
 555static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
 556                                      hda_nid_t pin_nid)
 557{
 558        hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 559        snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 560                                                AC_DIPXMIT_DISABLE);
 561}
 562
 563static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
 564{
 565#ifdef CONFIG_SND_DEBUG_VERBOSE
 566        int i;
 567        int size;
 568
 569        size = snd_hdmi_get_eld_size(codec, pin_nid);
 570        codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
 571
 572        for (i = 0; i < 8; i++) {
 573                size = snd_hda_codec_read(codec, pin_nid, 0,
 574                                                AC_VERB_GET_HDMI_DIP_SIZE, i);
 575                codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
 576        }
 577#endif
 578}
 579
 580static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
 581{
 582#ifdef BE_PARANOID
 583        int i, j;
 584        int size;
 585        int pi, bi;
 586        for (i = 0; i < 8; i++) {
 587                size = snd_hda_codec_read(codec, pin_nid, 0,
 588                                                AC_VERB_GET_HDMI_DIP_SIZE, i);
 589                if (size == 0)
 590                        continue;
 591
 592                hdmi_set_dip_index(codec, pin_nid, i, 0x0);
 593                for (j = 1; j < 1000; j++) {
 594                        hdmi_write_dip_byte(codec, pin_nid, 0x0);
 595                        hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
 596                        if (pi != i)
 597                                codec_dbg(codec, "dip index %d: %d != %d\n",
 598                                                bi, pi, i);
 599                        if (bi == 0) /* byte index wrapped around */
 600                                break;
 601                }
 602                codec_dbg(codec,
 603                        "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
 604                        i, size, j);
 605        }
 606#endif
 607}
 608
 609static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
 610{
 611        u8 *bytes = (u8 *)hdmi_ai;
 612        u8 sum = 0;
 613        int i;
 614
 615        hdmi_ai->checksum = 0;
 616
 617        for (i = 0; i < sizeof(*hdmi_ai); i++)
 618                sum += bytes[i];
 619
 620        hdmi_ai->checksum = -sum;
 621}
 622
 623static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
 624                                      hda_nid_t pin_nid,
 625                                      u8 *dip, int size)
 626{
 627        int i;
 628
 629        hdmi_debug_dip_size(codec, pin_nid);
 630        hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
 631
 632        hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 633        for (i = 0; i < size; i++)
 634                hdmi_write_dip_byte(codec, pin_nid, dip[i]);
 635}
 636
 637static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
 638                                    u8 *dip, int size)
 639{
 640        u8 val;
 641        int i;
 642
 643        if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
 644                                                            != AC_DIPXMIT_BEST)
 645                return false;
 646
 647        hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 648        for (i = 0; i < size; i++) {
 649                val = snd_hda_codec_read(codec, pin_nid, 0,
 650                                         AC_VERB_GET_HDMI_DIP_DATA, 0);
 651                if (val != dip[i])
 652                        return false;
 653        }
 654
 655        return true;
 656}
 657
 658static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
 659                                     hda_nid_t pin_nid,
 660                                     int ca, int active_channels,
 661                                     int conn_type)
 662{
 663        union audio_infoframe ai;
 664
 665        memset(&ai, 0, sizeof(ai));
 666        if (conn_type == 0) { /* HDMI */
 667                struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
 668
 669                hdmi_ai->type           = 0x84;
 670                hdmi_ai->ver            = 0x01;
 671                hdmi_ai->len            = 0x0a;
 672                hdmi_ai->CC02_CT47      = active_channels - 1;
 673                hdmi_ai->CA             = ca;
 674                hdmi_checksum_audio_infoframe(hdmi_ai);
 675        } else if (conn_type == 1) { /* DisplayPort */
 676                struct dp_audio_infoframe *dp_ai = &ai.dp;
 677
 678                dp_ai->type             = 0x84;
 679                dp_ai->len              = 0x1b;
 680                dp_ai->ver              = 0x11 << 2;
 681                dp_ai->CC02_CT47        = active_channels - 1;
 682                dp_ai->CA               = ca;
 683        } else {
 684                codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
 685                            pin_nid);
 686                return;
 687        }
 688
 689        /*
 690         * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
 691         * sizeof(*dp_ai) to avoid partial match/update problems when
 692         * the user switches between HDMI/DP monitors.
 693         */
 694        if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
 695                                        sizeof(ai))) {
 696                codec_dbg(codec,
 697                          "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
 698                            pin_nid,
 699                            active_channels, ca);
 700                hdmi_stop_infoframe_trans(codec, pin_nid);
 701                hdmi_fill_audio_infoframe(codec, pin_nid,
 702                                            ai.bytes, sizeof(ai));
 703                hdmi_start_infoframe_trans(codec, pin_nid);
 704        }
 705}
 706
 707static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
 708                                       struct hdmi_spec_per_pin *per_pin,
 709                                       bool non_pcm)
 710{
 711        struct hdmi_spec *spec = codec->spec;
 712        struct hdac_chmap *chmap = &spec->chmap;
 713        hda_nid_t pin_nid = per_pin->pin_nid;
 714        int channels = per_pin->channels;
 715        int active_channels;
 716        struct hdmi_eld *eld;
 717        int ca;
 718
 719        if (!channels)
 720                return;
 721
 722        /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
 723        if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 724                snd_hda_codec_write(codec, pin_nid, 0,
 725                                            AC_VERB_SET_AMP_GAIN_MUTE,
 726                                            AMP_OUT_UNMUTE);
 727
 728        eld = &per_pin->sink_eld;
 729
 730        ca = snd_hdac_channel_allocation(&codec->core,
 731                        eld->info.spk_alloc, channels,
 732                        per_pin->chmap_set, non_pcm, per_pin->chmap);
 733
 734        active_channels = snd_hdac_get_active_channels(ca);
 735
 736        chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
 737                                                active_channels);
 738
 739        /*
 740         * always configure channel mapping, it may have been changed by the
 741         * user in the meantime
 742         */
 743        snd_hdac_setup_channel_mapping(&spec->chmap,
 744                                pin_nid, non_pcm, ca, channels,
 745                                per_pin->chmap, per_pin->chmap_set);
 746
 747        spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
 748                                      eld->info.conn_type);
 749
 750        per_pin->non_pcm = non_pcm;
 751}
 752
 753/*
 754 * Unsolicited events
 755 */
 756
 757static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
 758
 759static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
 760                                      int dev_id)
 761{
 762        struct hdmi_spec *spec = codec->spec;
 763        int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
 764
 765        if (pin_idx < 0)
 766                return;
 767        if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
 768                snd_hda_jack_report_sync(codec);
 769}
 770
 771static void jack_callback(struct hda_codec *codec,
 772                          struct hda_jack_callback *jack)
 773{
 774        /* hda_jack don't support DP MST */
 775        check_presence_and_report(codec, jack->nid, 0);
 776}
 777
 778static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
 779{
 780        int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 781        struct hda_jack_tbl *jack;
 782        int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
 783
 784        /*
 785         * assume DP MST uses dyn_pcm_assign and acomp and
 786         * never comes here
 787         * if DP MST supports unsol event, below code need
 788         * consider dev_entry
 789         */
 790        jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
 791        if (!jack)
 792                return;
 793        jack->jack_dirty = 1;
 794
 795        codec_dbg(codec,
 796                "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
 797                codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
 798                !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
 799
 800        /* hda_jack don't support DP MST */
 801        check_presence_and_report(codec, jack->nid, 0);
 802}
 803
 804static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
 805{
 806        int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 807        int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
 808        int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
 809        int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
 810
 811        codec_info(codec,
 812                "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
 813                codec->addr,
 814                tag,
 815                subtag,
 816                cp_state,
 817                cp_ready);
 818
 819        /* TODO */
 820        if (cp_state)
 821                ;
 822        if (cp_ready)
 823                ;
 824}
 825
 826
 827static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
 828{
 829        int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 830        int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
 831
 832        if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
 833                codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
 834                return;
 835        }
 836
 837        if (subtag == 0)
 838                hdmi_intrinsic_event(codec, res);
 839        else
 840                hdmi_non_intrinsic_event(codec, res);
 841}
 842
 843static void haswell_verify_D0(struct hda_codec *codec,
 844                hda_nid_t cvt_nid, hda_nid_t nid)
 845{
 846        int pwr;
 847
 848        /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
 849         * thus pins could only choose converter 0 for use. Make sure the
 850         * converters are in correct power state */
 851        if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
 852                snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
 853
 854        if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
 855                snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
 856                                    AC_PWRST_D0);
 857                msleep(40);
 858                pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
 859                pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
 860                codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
 861        }
 862}
 863
 864/*
 865 * Callbacks
 866 */
 867
 868/* HBR should be Non-PCM, 8 channels */
 869#define is_hbr_format(format) \
 870        ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
 871
 872static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
 873                              bool hbr)
 874{
 875        int pinctl, new_pinctl;
 876
 877        if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
 878                pinctl = snd_hda_codec_read(codec, pin_nid, 0,
 879                                            AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
 880
 881                if (pinctl < 0)
 882                        return hbr ? -EINVAL : 0;
 883
 884                new_pinctl = pinctl & ~AC_PINCTL_EPT;
 885                if (hbr)
 886                        new_pinctl |= AC_PINCTL_EPT_HBR;
 887                else
 888                        new_pinctl |= AC_PINCTL_EPT_NATIVE;
 889
 890                codec_dbg(codec,
 891                          "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
 892                            pin_nid,
 893                            pinctl == new_pinctl ? "" : "new-",
 894                            new_pinctl);
 895
 896                if (pinctl != new_pinctl)
 897                        snd_hda_codec_write(codec, pin_nid, 0,
 898                                            AC_VERB_SET_PIN_WIDGET_CONTROL,
 899                                            new_pinctl);
 900        } else if (hbr)
 901                return -EINVAL;
 902
 903        return 0;
 904}
 905
 906static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
 907                              hda_nid_t pin_nid, u32 stream_tag, int format)
 908{
 909        struct hdmi_spec *spec = codec->spec;
 910        unsigned int param;
 911        int err;
 912
 913        err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
 914
 915        if (err) {
 916                codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
 917                return err;
 918        }
 919
 920        if (is_haswell_plus(codec)) {
 921
 922                /*
 923                 * on recent platforms IEC Coding Type is required for HBR
 924                 * support, read current Digital Converter settings and set
 925                 * ICT bitfield if needed.
 926                 */
 927                param = snd_hda_codec_read(codec, cvt_nid, 0,
 928                                           AC_VERB_GET_DIGI_CONVERT_1, 0);
 929
 930                param = (param >> 16) & ~(AC_DIG3_ICT);
 931
 932                /* on recent platforms ICT mode is required for HBR support */
 933                if (is_hbr_format(format))
 934                        param |= 0x1;
 935
 936                snd_hda_codec_write(codec, cvt_nid, 0,
 937                                    AC_VERB_SET_DIGI_CONVERT_3, param);
 938        }
 939
 940        snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
 941        return 0;
 942}
 943
 944/* Try to find an available converter
 945 * If pin_idx is less then zero, just try to find an available converter.
 946 * Otherwise, try to find an available converter and get the cvt mux index
 947 * of the pin.
 948 */
 949static int hdmi_choose_cvt(struct hda_codec *codec,
 950                           int pin_idx, int *cvt_id)
 951{
 952        struct hdmi_spec *spec = codec->spec;
 953        struct hdmi_spec_per_pin *per_pin;
 954        struct hdmi_spec_per_cvt *per_cvt = NULL;
 955        int cvt_idx, mux_idx = 0;
 956
 957        /* pin_idx < 0 means no pin will be bound to the converter */
 958        if (pin_idx < 0)
 959                per_pin = NULL;
 960        else
 961                per_pin = get_pin(spec, pin_idx);
 962
 963        /* Dynamically assign converter to stream */
 964        for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
 965                per_cvt = get_cvt(spec, cvt_idx);
 966
 967                /* Must not already be assigned */
 968                if (per_cvt->assigned)
 969                        continue;
 970                if (per_pin == NULL)
 971                        break;
 972                /* Must be in pin's mux's list of converters */
 973                for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
 974                        if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
 975                                break;
 976                /* Not in mux list */
 977                if (mux_idx == per_pin->num_mux_nids)
 978                        continue;
 979                break;
 980        }
 981
 982        /* No free converters */
 983        if (cvt_idx == spec->num_cvts)
 984                return -EBUSY;
 985
 986        if (per_pin != NULL)
 987                per_pin->mux_idx = mux_idx;
 988
 989        if (cvt_id)
 990                *cvt_id = cvt_idx;
 991
 992        return 0;
 993}
 994
 995/* Assure the pin select the right convetor */
 996static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
 997                        struct hdmi_spec_per_pin *per_pin)
 998{
 999        hda_nid_t pin_nid = per_pin->pin_nid;
1000        int mux_idx, curr;
1001
1002        mux_idx = per_pin->mux_idx;
1003        curr = snd_hda_codec_read(codec, pin_nid, 0,
1004                                          AC_VERB_GET_CONNECT_SEL, 0);
1005        if (curr != mux_idx)
1006                snd_hda_codec_write_cache(codec, pin_nid, 0,
1007                                            AC_VERB_SET_CONNECT_SEL,
1008                                            mux_idx);
1009}
1010
1011/* get the mux index for the converter of the pins
1012 * converter's mux index is the same for all pins on Intel platform
1013 */
1014static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1015                        hda_nid_t cvt_nid)
1016{
1017        int i;
1018
1019        for (i = 0; i < spec->num_cvts; i++)
1020                if (spec->cvt_nids[i] == cvt_nid)
1021                        return i;
1022        return -EINVAL;
1023}
1024
1025/* Intel HDMI workaround to fix audio routing issue:
1026 * For some Intel display codecs, pins share the same connection list.
1027 * So a conveter can be selected by multiple pins and playback on any of these
1028 * pins will generate sound on the external display, because audio flows from
1029 * the same converter to the display pipeline. Also muting one pin may make
1030 * other pins have no sound output.
1031 * So this function assures that an assigned converter for a pin is not selected
1032 * by any other pins.
1033 */
1034static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1035                                         hda_nid_t pin_nid,
1036                                         int dev_id, int mux_idx)
1037{
1038        struct hdmi_spec *spec = codec->spec;
1039        hda_nid_t nid;
1040        int cvt_idx, curr;
1041        struct hdmi_spec_per_cvt *per_cvt;
1042        struct hdmi_spec_per_pin *per_pin;
1043        int pin_idx;
1044
1045        /* configure the pins connections */
1046        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1047                int dev_id_saved;
1048                int dev_num;
1049
1050                per_pin = get_pin(spec, pin_idx);
1051                /*
1052                 * pin not connected to monitor
1053                 * no need to operate on it
1054                 */
1055                if (!per_pin->pcm)
1056                        continue;
1057
1058                if ((per_pin->pin_nid == pin_nid) &&
1059                        (per_pin->dev_id == dev_id))
1060                        continue;
1061
1062                /*
1063                 * if per_pin->dev_id >= dev_num,
1064                 * snd_hda_get_dev_select() will fail,
1065                 * and the following operation is unpredictable.
1066                 * So skip this situation.
1067                 */
1068                dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1069                if (per_pin->dev_id >= dev_num)
1070                        continue;
1071
1072                nid = per_pin->pin_nid;
1073
1074                /*
1075                 * Calling this function should not impact
1076                 * on the device entry selection
1077                 * So let's save the dev id for each pin,
1078                 * and restore it when return
1079                 */
1080                dev_id_saved = snd_hda_get_dev_select(codec, nid);
1081                snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1082                curr = snd_hda_codec_read(codec, nid, 0,
1083                                          AC_VERB_GET_CONNECT_SEL, 0);
1084                if (curr != mux_idx) {
1085                        snd_hda_set_dev_select(codec, nid, dev_id_saved);
1086                        continue;
1087                }
1088
1089
1090                /* choose an unassigned converter. The conveters in the
1091                 * connection list are in the same order as in the codec.
1092                 */
1093                for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1094                        per_cvt = get_cvt(spec, cvt_idx);
1095                        if (!per_cvt->assigned) {
1096                                codec_dbg(codec,
1097                                          "choose cvt %d for pin nid %d\n",
1098                                        cvt_idx, nid);
1099                                snd_hda_codec_write_cache(codec, nid, 0,
1100                                            AC_VERB_SET_CONNECT_SEL,
1101                                            cvt_idx);
1102                                break;
1103                        }
1104                }
1105                snd_hda_set_dev_select(codec, nid, dev_id_saved);
1106        }
1107}
1108
1109/* A wrapper of intel_not_share_asigned_cvt() */
1110static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1111                        hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1112{
1113        int mux_idx;
1114        struct hdmi_spec *spec = codec->spec;
1115
1116        /* On Intel platform, the mapping of converter nid to
1117         * mux index of the pins are always the same.
1118         * The pin nid may be 0, this means all pins will not
1119         * share the converter.
1120         */
1121        mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1122        if (mux_idx >= 0)
1123                intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1124}
1125
1126/* skeleton caller of pin_cvt_fixup ops */
1127static void pin_cvt_fixup(struct hda_codec *codec,
1128                          struct hdmi_spec_per_pin *per_pin,
1129                          hda_nid_t cvt_nid)
1130{
1131        struct hdmi_spec *spec = codec->spec;
1132
1133        if (spec->ops.pin_cvt_fixup)
1134                spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1135}
1136
1137/* called in hdmi_pcm_open when no pin is assigned to the PCM
1138 * in dyn_pcm_assign mode.
1139 */
1140static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1141                         struct hda_codec *codec,
1142                         struct snd_pcm_substream *substream)
1143{
1144        struct hdmi_spec *spec = codec->spec;
1145        struct snd_pcm_runtime *runtime = substream->runtime;
1146        int cvt_idx, pcm_idx;
1147        struct hdmi_spec_per_cvt *per_cvt = NULL;
1148        int err;
1149
1150        pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1151        if (pcm_idx < 0)
1152                return -EINVAL;
1153
1154        err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1155        if (err)
1156                return err;
1157
1158        per_cvt = get_cvt(spec, cvt_idx);
1159        per_cvt->assigned = 1;
1160        hinfo->nid = per_cvt->cvt_nid;
1161
1162        pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1163
1164        set_bit(pcm_idx, &spec->pcm_in_use);
1165        /* todo: setup spdif ctls assign */
1166
1167        /* Initially set the converter's capabilities */
1168        hinfo->channels_min = per_cvt->channels_min;
1169        hinfo->channels_max = per_cvt->channels_max;
1170        hinfo->rates = per_cvt->rates;
1171        hinfo->formats = per_cvt->formats;
1172        hinfo->maxbps = per_cvt->maxbps;
1173
1174        /* Store the updated parameters */
1175        runtime->hw.channels_min = hinfo->channels_min;
1176        runtime->hw.channels_max = hinfo->channels_max;
1177        runtime->hw.formats = hinfo->formats;
1178        runtime->hw.rates = hinfo->rates;
1179
1180        snd_pcm_hw_constraint_step(substream->runtime, 0,
1181                                   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1182        return 0;
1183}
1184
1185/*
1186 * HDA PCM callbacks
1187 */
1188static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1189                         struct hda_codec *codec,
1190                         struct snd_pcm_substream *substream)
1191{
1192        struct hdmi_spec *spec = codec->spec;
1193        struct snd_pcm_runtime *runtime = substream->runtime;
1194        int pin_idx, cvt_idx, pcm_idx;
1195        struct hdmi_spec_per_pin *per_pin;
1196        struct hdmi_eld *eld;
1197        struct hdmi_spec_per_cvt *per_cvt = NULL;
1198        int err;
1199
1200        /* Validate hinfo */
1201        pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1202        if (pcm_idx < 0)
1203                return -EINVAL;
1204
1205        mutex_lock(&spec->pcm_lock);
1206        pin_idx = hinfo_to_pin_index(codec, hinfo);
1207        if (!spec->dyn_pcm_assign) {
1208                if (snd_BUG_ON(pin_idx < 0)) {
1209                        mutex_unlock(&spec->pcm_lock);
1210                        return -EINVAL;
1211                }
1212        } else {
1213                /* no pin is assigned to the PCM
1214                 * PA need pcm open successfully when probe
1215                 */
1216                if (pin_idx < 0) {
1217                        err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1218                        mutex_unlock(&spec->pcm_lock);
1219                        return err;
1220                }
1221        }
1222
1223        err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1224        if (err < 0) {
1225                mutex_unlock(&spec->pcm_lock);
1226                return err;
1227        }
1228
1229        per_cvt = get_cvt(spec, cvt_idx);
1230        /* Claim converter */
1231        per_cvt->assigned = 1;
1232
1233        set_bit(pcm_idx, &spec->pcm_in_use);
1234        per_pin = get_pin(spec, pin_idx);
1235        per_pin->cvt_nid = per_cvt->cvt_nid;
1236        hinfo->nid = per_cvt->cvt_nid;
1237
1238        snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1239        snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1240                            AC_VERB_SET_CONNECT_SEL,
1241                            per_pin->mux_idx);
1242
1243        /* configure unused pins to choose other converters */
1244        pin_cvt_fixup(codec, per_pin, 0);
1245
1246        snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1247
1248        /* Initially set the converter's capabilities */
1249        hinfo->channels_min = per_cvt->channels_min;
1250        hinfo->channels_max = per_cvt->channels_max;
1251        hinfo->rates = per_cvt->rates;
1252        hinfo->formats = per_cvt->formats;
1253        hinfo->maxbps = per_cvt->maxbps;
1254
1255        eld = &per_pin->sink_eld;
1256        /* Restrict capabilities by ELD if this isn't disabled */
1257        if (!static_hdmi_pcm && eld->eld_valid) {
1258                snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1259                if (hinfo->channels_min > hinfo->channels_max ||
1260                    !hinfo->rates || !hinfo->formats) {
1261                        per_cvt->assigned = 0;
1262                        hinfo->nid = 0;
1263                        snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1264                        mutex_unlock(&spec->pcm_lock);
1265                        return -ENODEV;
1266                }
1267        }
1268
1269        mutex_unlock(&spec->pcm_lock);
1270        /* Store the updated parameters */
1271        runtime->hw.channels_min = hinfo->channels_min;
1272        runtime->hw.channels_max = hinfo->channels_max;
1273        runtime->hw.formats = hinfo->formats;
1274        runtime->hw.rates = hinfo->rates;
1275
1276        snd_pcm_hw_constraint_step(substream->runtime, 0,
1277                                   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1278        return 0;
1279}
1280
1281/*
1282 * HDA/HDMI auto parsing
1283 */
1284static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1285{
1286        struct hdmi_spec *spec = codec->spec;
1287        struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1288        hda_nid_t pin_nid = per_pin->pin_nid;
1289
1290        if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1291                codec_warn(codec,
1292                           "HDMI: pin %d wcaps %#x does not support connection list\n",
1293                           pin_nid, get_wcaps(codec, pin_nid));
1294                return -EINVAL;
1295        }
1296
1297        /* all the device entries on the same pin have the same conn list */
1298        per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1299                                                        per_pin->mux_nids,
1300                                                        HDA_MAX_CONNECTIONS);
1301
1302        return 0;
1303}
1304
1305static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1306                                struct hdmi_spec_per_pin *per_pin)
1307{
1308        int i;
1309
1310        /* try the prefer PCM */
1311        if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1312                return per_pin->pin_nid_idx;
1313
1314        /* have a second try; check the "reserved area" over num_pins */
1315        for (i = spec->num_nids; i < spec->pcm_used; i++) {
1316                if (!test_bit(i, &spec->pcm_bitmap))
1317                        return i;
1318        }
1319
1320        /* the last try; check the empty slots in pins */
1321        for (i = 0; i < spec->num_nids; i++) {
1322                if (!test_bit(i, &spec->pcm_bitmap))
1323                        return i;
1324        }
1325        return -EBUSY;
1326}
1327
1328static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1329                                struct hdmi_spec_per_pin *per_pin)
1330{
1331        int idx;
1332
1333        /* pcm already be attached to the pin */
1334        if (per_pin->pcm)
1335                return;
1336        idx = hdmi_find_pcm_slot(spec, per_pin);
1337        if (idx == -EBUSY)
1338                return;
1339        per_pin->pcm_idx = idx;
1340        per_pin->pcm = get_hdmi_pcm(spec, idx);
1341        set_bit(idx, &spec->pcm_bitmap);
1342}
1343
1344static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1345                                struct hdmi_spec_per_pin *per_pin)
1346{
1347        int idx;
1348
1349        /* pcm already be detached from the pin */
1350        if (!per_pin->pcm)
1351                return;
1352        idx = per_pin->pcm_idx;
1353        per_pin->pcm_idx = -1;
1354        per_pin->pcm = NULL;
1355        if (idx >= 0 && idx < spec->pcm_used)
1356                clear_bit(idx, &spec->pcm_bitmap);
1357}
1358
1359static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1360                struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1361{
1362        int mux_idx;
1363
1364        for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1365                if (per_pin->mux_nids[mux_idx] == cvt_nid)
1366                        break;
1367        return mux_idx;
1368}
1369
1370static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1371
1372static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1373                           struct hdmi_spec_per_pin *per_pin)
1374{
1375        struct hda_codec *codec = per_pin->codec;
1376        struct hda_pcm *pcm;
1377        struct hda_pcm_stream *hinfo;
1378        struct snd_pcm_substream *substream;
1379        int mux_idx;
1380        bool non_pcm;
1381
1382        if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1383                pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1384        else
1385                return;
1386        if (!pcm->pcm)
1387                return;
1388        if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1389                return;
1390
1391        /* hdmi audio only uses playback and one substream */
1392        hinfo = pcm->stream;
1393        substream = pcm->pcm->streams[0].substream;
1394
1395        per_pin->cvt_nid = hinfo->nid;
1396
1397        mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1398        if (mux_idx < per_pin->num_mux_nids) {
1399                snd_hda_set_dev_select(codec, per_pin->pin_nid,
1400                                   per_pin->dev_id);
1401                snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1402                                AC_VERB_SET_CONNECT_SEL,
1403                                mux_idx);
1404        }
1405        snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1406
1407        non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1408        if (substream->runtime)
1409                per_pin->channels = substream->runtime->channels;
1410        per_pin->setup = true;
1411        per_pin->mux_idx = mux_idx;
1412
1413        hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1414}
1415
1416static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1417                           struct hdmi_spec_per_pin *per_pin)
1418{
1419        if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1420                snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1421
1422        per_pin->chmap_set = false;
1423        memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1424
1425        per_pin->setup = false;
1426        per_pin->channels = 0;
1427}
1428
1429/* update per_pin ELD from the given new ELD;
1430 * setup info frame and notification accordingly
1431 */
1432static void update_eld(struct hda_codec *codec,
1433                       struct hdmi_spec_per_pin *per_pin,
1434                       struct hdmi_eld *eld)
1435{
1436        struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1437        struct hdmi_spec *spec = codec->spec;
1438        bool old_eld_valid = pin_eld->eld_valid;
1439        bool eld_changed;
1440        int pcm_idx = -1;
1441
1442        /* for monitor disconnection, save pcm_idx firstly */
1443        pcm_idx = per_pin->pcm_idx;
1444        if (spec->dyn_pcm_assign) {
1445                if (eld->eld_valid) {
1446                        hdmi_attach_hda_pcm(spec, per_pin);
1447                        hdmi_pcm_setup_pin(spec, per_pin);
1448                } else {
1449                        hdmi_pcm_reset_pin(spec, per_pin);
1450                        hdmi_detach_hda_pcm(spec, per_pin);
1451                }
1452        }
1453        /* if pcm_idx == -1, it means this is in monitor connection event
1454         * we can get the correct pcm_idx now.
1455         */
1456        if (pcm_idx == -1)
1457                pcm_idx = per_pin->pcm_idx;
1458
1459        if (eld->eld_valid)
1460                snd_hdmi_show_eld(codec, &eld->info);
1461
1462        eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1463        if (eld->eld_valid && pin_eld->eld_valid)
1464                if (pin_eld->eld_size != eld->eld_size ||
1465                    memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1466                           eld->eld_size) != 0)
1467                        eld_changed = true;
1468
1469        pin_eld->monitor_present = eld->monitor_present;
1470        pin_eld->eld_valid = eld->eld_valid;
1471        pin_eld->eld_size = eld->eld_size;
1472        if (eld->eld_valid)
1473                memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1474        pin_eld->info = eld->info;
1475
1476        /*
1477         * Re-setup pin and infoframe. This is needed e.g. when
1478         * - sink is first plugged-in
1479         * - transcoder can change during stream playback on Haswell
1480         *   and this can make HW reset converter selection on a pin.
1481         */
1482        if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1483                pin_cvt_fixup(codec, per_pin, 0);
1484                hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1485        }
1486
1487        if (eld_changed && pcm_idx >= 0)
1488                snd_ctl_notify(codec->card,
1489                               SNDRV_CTL_EVENT_MASK_VALUE |
1490                               SNDRV_CTL_EVENT_MASK_INFO,
1491                               &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1492}
1493
1494/* update ELD and jack state via HD-audio verbs */
1495static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1496                                         int repoll)
1497{
1498        struct hda_jack_tbl *jack;
1499        struct hda_codec *codec = per_pin->codec;
1500        struct hdmi_spec *spec = codec->spec;
1501        struct hdmi_eld *eld = &spec->temp_eld;
1502        hda_nid_t pin_nid = per_pin->pin_nid;
1503        /*
1504         * Always execute a GetPinSense verb here, even when called from
1505         * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1506         * response's PD bit is not the real PD value, but indicates that
1507         * the real PD value changed. An older version of the HD-audio
1508         * specification worked this way. Hence, we just ignore the data in
1509         * the unsolicited response to avoid custom WARs.
1510         */
1511        int present;
1512        bool ret;
1513        bool do_repoll = false;
1514
1515        present = snd_hda_pin_sense(codec, pin_nid);
1516
1517        mutex_lock(&per_pin->lock);
1518        eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1519        if (eld->monitor_present)
1520                eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1521        else
1522                eld->eld_valid = false;
1523
1524        codec_dbg(codec,
1525                "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1526                codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1527
1528        if (eld->eld_valid) {
1529                if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1530                                                     &eld->eld_size) < 0)
1531                        eld->eld_valid = false;
1532                else {
1533                        if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1534                                                    eld->eld_size) < 0)
1535                                eld->eld_valid = false;
1536                }
1537                if (!eld->eld_valid && repoll)
1538                        do_repoll = true;
1539        }
1540
1541        if (do_repoll)
1542                schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1543        else
1544                update_eld(codec, per_pin, eld);
1545
1546        ret = !repoll || !eld->monitor_present || eld->eld_valid;
1547
1548        jack = snd_hda_jack_tbl_get(codec, pin_nid);
1549        if (jack)
1550                jack->block_report = !ret;
1551
1552        mutex_unlock(&per_pin->lock);
1553        return ret;
1554}
1555
1556static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1557                                 struct hdmi_spec_per_pin *per_pin)
1558{
1559        struct hdmi_spec *spec = codec->spec;
1560        struct snd_jack *jack = NULL;
1561        struct hda_jack_tbl *jack_tbl;
1562
1563        /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1564         * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1565         * NULL even after snd_hda_jack_tbl_clear() is called to
1566         * free snd_jack. This may cause access invalid memory
1567         * when calling snd_jack_report
1568         */
1569        if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1570                jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1571        else if (!spec->dyn_pcm_assign) {
1572                /*
1573                 * jack tbl doesn't support DP MST
1574                 * DP MST will use dyn_pcm_assign,
1575                 * so DP MST will never come here
1576                 */
1577                jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1578                if (jack_tbl)
1579                        jack = jack_tbl->jack;
1580        }
1581        return jack;
1582}
1583
1584/* update ELD and jack state via audio component */
1585static void sync_eld_via_acomp(struct hda_codec *codec,
1586                               struct hdmi_spec_per_pin *per_pin)
1587{
1588        struct hdmi_spec *spec = codec->spec;
1589        struct hdmi_eld *eld = &spec->temp_eld;
1590        struct snd_jack *jack = NULL;
1591        int size;
1592
1593        mutex_lock(&per_pin->lock);
1594        eld->monitor_present = false;
1595        size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1596                                      per_pin->dev_id, &eld->monitor_present,
1597                                      eld->eld_buffer, ELD_MAX_SIZE);
1598        if (size > 0) {
1599                size = min(size, ELD_MAX_SIZE);
1600                if (snd_hdmi_parse_eld(codec, &eld->info,
1601                                       eld->eld_buffer, size) < 0)
1602                        size = -EINVAL;
1603        }
1604
1605        if (size > 0) {
1606                eld->eld_valid = true;
1607                eld->eld_size = size;
1608        } else {
1609                eld->eld_valid = false;
1610                eld->eld_size = 0;
1611        }
1612
1613        /* pcm_idx >=0 before update_eld() means it is in monitor
1614         * disconnected event. Jack must be fetched before update_eld()
1615         */
1616        jack = pin_idx_to_jack(codec, per_pin);
1617        update_eld(codec, per_pin, eld);
1618        if (jack == NULL)
1619                jack = pin_idx_to_jack(codec, per_pin);
1620        if (jack == NULL)
1621                goto unlock;
1622        snd_jack_report(jack,
1623                        eld->monitor_present ? SND_JACK_AVOUT : 0);
1624 unlock:
1625        mutex_unlock(&per_pin->lock);
1626}
1627
1628static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1629{
1630        struct hda_codec *codec = per_pin->codec;
1631        struct hdmi_spec *spec = codec->spec;
1632        int ret;
1633
1634        /* no temporary power up/down needed for component notifier */
1635        if (!codec_has_acomp(codec))
1636                snd_hda_power_up_pm(codec);
1637
1638        mutex_lock(&spec->pcm_lock);
1639        if (codec_has_acomp(codec)) {
1640                sync_eld_via_acomp(codec, per_pin);
1641                ret = false; /* don't call snd_hda_jack_report_sync() */
1642        } else {
1643                ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1644        }
1645        mutex_unlock(&spec->pcm_lock);
1646
1647        if (!codec_has_acomp(codec))
1648                snd_hda_power_down_pm(codec);
1649
1650        return ret;
1651}
1652
1653static void hdmi_repoll_eld(struct work_struct *work)
1654{
1655        struct hdmi_spec_per_pin *per_pin =
1656        container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1657
1658        if (per_pin->repoll_count++ > 6)
1659                per_pin->repoll_count = 0;
1660
1661        if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1662                snd_hda_jack_report_sync(per_pin->codec);
1663}
1664
1665static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1666                                             hda_nid_t nid);
1667
1668static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1669{
1670        struct hdmi_spec *spec = codec->spec;
1671        unsigned int caps, config;
1672        int pin_idx;
1673        struct hdmi_spec_per_pin *per_pin;
1674        int err;
1675        int dev_num, i;
1676
1677        caps = snd_hda_query_pin_caps(codec, pin_nid);
1678        if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1679                return 0;
1680
1681        /*
1682         * For DP MST audio, Configuration Default is the same for
1683         * all device entries on the same pin
1684         */
1685        config = snd_hda_codec_get_pincfg(codec, pin_nid);
1686        if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1687                return 0;
1688
1689        /*
1690         * To simplify the implementation, malloc all
1691         * the virtual pins in the initialization statically
1692         */
1693        if (is_haswell_plus(codec)) {
1694                /*
1695                 * On Intel platforms, device entries number is
1696                 * changed dynamically. If there is a DP MST
1697                 * hub connected, the device entries number is 3.
1698                 * Otherwise, it is 1.
1699                 * Here we manually set dev_num to 3, so that
1700                 * we can initialize all the device entries when
1701                 * bootup statically.
1702                 */
1703                dev_num = 3;
1704                spec->dev_num = 3;
1705        } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1706                dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1707                /*
1708                 * spec->dev_num is the maxinum number of device entries
1709                 * among all the pins
1710                 */
1711                spec->dev_num = (spec->dev_num > dev_num) ?
1712                        spec->dev_num : dev_num;
1713        } else {
1714                /*
1715                 * If the platform doesn't support DP MST,
1716                 * manually set dev_num to 1. This means
1717                 * the pin has only one device entry.
1718                 */
1719                dev_num = 1;
1720                spec->dev_num = 1;
1721        }
1722
1723        for (i = 0; i < dev_num; i++) {
1724                pin_idx = spec->num_pins;
1725                per_pin = snd_array_new(&spec->pins);
1726
1727                if (!per_pin)
1728                        return -ENOMEM;
1729
1730                if (spec->dyn_pcm_assign) {
1731                        per_pin->pcm = NULL;
1732                        per_pin->pcm_idx = -1;
1733                } else {
1734                        per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1735                        per_pin->pcm_idx = pin_idx;
1736                }
1737                per_pin->pin_nid = pin_nid;
1738                per_pin->pin_nid_idx = spec->num_nids;
1739                per_pin->dev_id = i;
1740                per_pin->non_pcm = false;
1741                snd_hda_set_dev_select(codec, pin_nid, i);
1742                if (is_haswell_plus(codec))
1743                        intel_haswell_fixup_connect_list(codec, pin_nid);
1744                err = hdmi_read_pin_conn(codec, pin_idx);
1745                if (err < 0)
1746                        return err;
1747                spec->num_pins++;
1748        }
1749        spec->num_nids++;
1750
1751        return 0;
1752}
1753
1754static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1755{
1756        struct hdmi_spec *spec = codec->spec;
1757        struct hdmi_spec_per_cvt *per_cvt;
1758        unsigned int chans;
1759        int err;
1760
1761        chans = get_wcaps(codec, cvt_nid);
1762        chans = get_wcaps_channels(chans);
1763
1764        per_cvt = snd_array_new(&spec->cvts);
1765        if (!per_cvt)
1766                return -ENOMEM;
1767
1768        per_cvt->cvt_nid = cvt_nid;
1769        per_cvt->channels_min = 2;
1770        if (chans <= 16) {
1771                per_cvt->channels_max = chans;
1772                if (chans > spec->chmap.channels_max)
1773                        spec->chmap.channels_max = chans;
1774        }
1775
1776        err = snd_hda_query_supported_pcm(codec, cvt_nid,
1777                                          &per_cvt->rates,
1778                                          &per_cvt->formats,
1779                                          &per_cvt->maxbps);
1780        if (err < 0)
1781                return err;
1782
1783        if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1784                spec->cvt_nids[spec->num_cvts] = cvt_nid;
1785        spec->num_cvts++;
1786
1787        return 0;
1788}
1789
1790static int hdmi_parse_codec(struct hda_codec *codec)
1791{
1792        hda_nid_t nid;
1793        int i, nodes;
1794
1795        nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1796        if (!nid || nodes < 0) {
1797                codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1798                return -EINVAL;
1799        }
1800
1801        for (i = 0; i < nodes; i++, nid++) {
1802                unsigned int caps;
1803                unsigned int type;
1804
1805                caps = get_wcaps(codec, nid);
1806                type = get_wcaps_type(caps);
1807
1808                if (!(caps & AC_WCAP_DIGITAL))
1809                        continue;
1810
1811                switch (type) {
1812                case AC_WID_AUD_OUT:
1813                        hdmi_add_cvt(codec, nid);
1814                        break;
1815                case AC_WID_PIN:
1816                        hdmi_add_pin(codec, nid);
1817                        break;
1818                }
1819        }
1820
1821        return 0;
1822}
1823
1824/*
1825 */
1826static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1827{
1828        struct hda_spdif_out *spdif;
1829        bool non_pcm;
1830
1831        mutex_lock(&codec->spdif_mutex);
1832        spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1833        /* Add sanity check to pass klockwork check.
1834         * This should never happen.
1835         */
1836        if (WARN_ON(spdif == NULL))
1837                return true;
1838        non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1839        mutex_unlock(&codec->spdif_mutex);
1840        return non_pcm;
1841}
1842
1843/*
1844 * HDMI callbacks
1845 */
1846
1847static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1848                                           struct hda_codec *codec,
1849                                           unsigned int stream_tag,
1850                                           unsigned int format,
1851                                           struct snd_pcm_substream *substream)
1852{
1853        hda_nid_t cvt_nid = hinfo->nid;
1854        struct hdmi_spec *spec = codec->spec;
1855        int pin_idx;
1856        struct hdmi_spec_per_pin *per_pin;
1857        hda_nid_t pin_nid;
1858        struct snd_pcm_runtime *runtime = substream->runtime;
1859        bool non_pcm;
1860        int pinctl;
1861        int err;
1862
1863        mutex_lock(&spec->pcm_lock);
1864        pin_idx = hinfo_to_pin_index(codec, hinfo);
1865        if (spec->dyn_pcm_assign && pin_idx < 0) {
1866                /* when dyn_pcm_assign and pcm is not bound to a pin
1867                 * skip pin setup and return 0 to make audio playback
1868                 * be ongoing
1869                 */
1870                pin_cvt_fixup(codec, NULL, cvt_nid);
1871                snd_hda_codec_setup_stream(codec, cvt_nid,
1872                                        stream_tag, 0, format);
1873                mutex_unlock(&spec->pcm_lock);
1874                return 0;
1875        }
1876
1877        if (snd_BUG_ON(pin_idx < 0)) {
1878                mutex_unlock(&spec->pcm_lock);
1879                return -EINVAL;
1880        }
1881        per_pin = get_pin(spec, pin_idx);
1882        pin_nid = per_pin->pin_nid;
1883
1884        /* Verify pin:cvt selections to avoid silent audio after S3.
1885         * After S3, the audio driver restores pin:cvt selections
1886         * but this can happen before gfx is ready and such selection
1887         * is overlooked by HW. Thus multiple pins can share a same
1888         * default convertor and mute control will affect each other,
1889         * which can cause a resumed audio playback become silent
1890         * after S3.
1891         */
1892        pin_cvt_fixup(codec, per_pin, 0);
1893
1894        /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1895        /* Todo: add DP1.2 MST audio support later */
1896        if (codec_has_acomp(codec))
1897                snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1898                                         runtime->rate);
1899
1900        non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1901        mutex_lock(&per_pin->lock);
1902        per_pin->channels = substream->runtime->channels;
1903        per_pin->setup = true;
1904
1905        hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1906        mutex_unlock(&per_pin->lock);
1907        if (spec->dyn_pin_out) {
1908                pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1909                                            AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1910                snd_hda_codec_write(codec, pin_nid, 0,
1911                                    AC_VERB_SET_PIN_WIDGET_CONTROL,
1912                                    pinctl | PIN_OUT);
1913        }
1914
1915        /* snd_hda_set_dev_select() has been called before */
1916        err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1917                                 stream_tag, format);
1918        mutex_unlock(&spec->pcm_lock);
1919        return err;
1920}
1921
1922static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1923                                             struct hda_codec *codec,
1924                                             struct snd_pcm_substream *substream)
1925{
1926        snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1927        return 0;
1928}
1929
1930static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1931                          struct hda_codec *codec,
1932                          struct snd_pcm_substream *substream)
1933{
1934        struct hdmi_spec *spec = codec->spec;
1935        int cvt_idx, pin_idx, pcm_idx;
1936        struct hdmi_spec_per_cvt *per_cvt;
1937        struct hdmi_spec_per_pin *per_pin;
1938        int pinctl;
1939
1940        if (hinfo->nid) {
1941                pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1942                if (snd_BUG_ON(pcm_idx < 0))
1943                        return -EINVAL;
1944                cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1945                if (snd_BUG_ON(cvt_idx < 0))
1946                        return -EINVAL;
1947                per_cvt = get_cvt(spec, cvt_idx);
1948
1949                snd_BUG_ON(!per_cvt->assigned);
1950                per_cvt->assigned = 0;
1951                hinfo->nid = 0;
1952
1953                mutex_lock(&spec->pcm_lock);
1954                snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1955                clear_bit(pcm_idx, &spec->pcm_in_use);
1956                pin_idx = hinfo_to_pin_index(codec, hinfo);
1957                if (spec->dyn_pcm_assign && pin_idx < 0) {
1958                        mutex_unlock(&spec->pcm_lock);
1959                        return 0;
1960                }
1961
1962                if (snd_BUG_ON(pin_idx < 0)) {
1963                        mutex_unlock(&spec->pcm_lock);
1964                        return -EINVAL;
1965                }
1966                per_pin = get_pin(spec, pin_idx);
1967
1968                if (spec->dyn_pin_out) {
1969                        pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1970                                        AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1971                        snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1972                                            AC_VERB_SET_PIN_WIDGET_CONTROL,
1973                                            pinctl & ~PIN_OUT);
1974                }
1975
1976                mutex_lock(&per_pin->lock);
1977                per_pin->chmap_set = false;
1978                memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1979
1980                per_pin->setup = false;
1981                per_pin->channels = 0;
1982                mutex_unlock(&per_pin->lock);
1983                mutex_unlock(&spec->pcm_lock);
1984        }
1985
1986        return 0;
1987}
1988
1989static const struct hda_pcm_ops generic_ops = {
1990        .open = hdmi_pcm_open,
1991        .close = hdmi_pcm_close,
1992        .prepare = generic_hdmi_playback_pcm_prepare,
1993        .cleanup = generic_hdmi_playback_pcm_cleanup,
1994};
1995
1996static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1997{
1998        struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1999        struct hdmi_spec *spec = codec->spec;
2000        struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2001
2002        if (!per_pin)
2003                return 0;
2004
2005        return per_pin->sink_eld.info.spk_alloc;
2006}
2007
2008static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2009                                        unsigned char *chmap)
2010{
2011        struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2012        struct hdmi_spec *spec = codec->spec;
2013        struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2014
2015        /* chmap is already set to 0 in caller */
2016        if (!per_pin)
2017                return;
2018
2019        memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2020}
2021
2022static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2023                                unsigned char *chmap, int prepared)
2024{
2025        struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2026        struct hdmi_spec *spec = codec->spec;
2027        struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2028
2029        if (!per_pin)
2030                return;
2031        mutex_lock(&per_pin->lock);
2032        per_pin->chmap_set = true;
2033        memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2034        if (prepared)
2035                hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2036        mutex_unlock(&per_pin->lock);
2037}
2038
2039static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2040{
2041        struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2042        struct hdmi_spec *spec = codec->spec;
2043        struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2044
2045        return per_pin ? true:false;
2046}
2047
2048static int generic_hdmi_build_pcms(struct hda_codec *codec)
2049{
2050        struct hdmi_spec *spec = codec->spec;
2051        int idx;
2052
2053        /*
2054         * for non-mst mode, pcm number is the same as before
2055         * for DP MST mode, pcm number is (nid number + dev_num - 1)
2056         *  dev_num is the device entry number in a pin
2057         *
2058         */
2059        for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2060                struct hda_pcm *info;
2061                struct hda_pcm_stream *pstr;
2062
2063                info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2064                if (!info)
2065                        return -ENOMEM;
2066
2067                spec->pcm_rec[idx].pcm = info;
2068                spec->pcm_used++;
2069                info->pcm_type = HDA_PCM_TYPE_HDMI;
2070                info->own_chmap = true;
2071
2072                pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2073                pstr->substreams = 1;
2074                pstr->ops = generic_ops;
2075                /* pcm number is less than 16 */
2076                if (spec->pcm_used >= 16)
2077                        break;
2078                /* other pstr fields are set in open */
2079        }
2080
2081        return 0;
2082}
2083
2084static void free_hdmi_jack_priv(struct snd_jack *jack)
2085{
2086        struct hdmi_pcm *pcm = jack->private_data;
2087
2088        pcm->jack = NULL;
2089}
2090
2091static int add_hdmi_jack_kctl(struct hda_codec *codec,
2092                               struct hdmi_spec *spec,
2093                               int pcm_idx,
2094                               const char *name)
2095{
2096        struct snd_jack *jack;
2097        int err;
2098
2099        err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2100                           true, false);
2101        if (err < 0)
2102                return err;
2103
2104        spec->pcm_rec[pcm_idx].jack = jack;
2105        jack->private_data = &spec->pcm_rec[pcm_idx];
2106        jack->private_free = free_hdmi_jack_priv;
2107        return 0;
2108}
2109
2110static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2111{
2112        char hdmi_str[32] = "HDMI/DP";
2113        struct hdmi_spec *spec = codec->spec;
2114        struct hdmi_spec_per_pin *per_pin;
2115        struct hda_jack_tbl *jack;
2116        int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2117        bool phantom_jack;
2118        int ret;
2119
2120        if (pcmdev > 0)
2121                sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2122
2123        if (spec->dyn_pcm_assign)
2124                return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2125
2126        /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2127        /* if !dyn_pcm_assign, it must be non-MST mode.
2128         * This means pcms and pins are statically mapped.
2129         * And pcm_idx is pin_idx.
2130         */
2131        per_pin = get_pin(spec, pcm_idx);
2132        phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2133        if (phantom_jack)
2134                strncat(hdmi_str, " Phantom",
2135                        sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2136        ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2137                                    phantom_jack);
2138        if (ret < 0)
2139                return ret;
2140        jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2141        if (jack == NULL)
2142                return 0;
2143        /* assign jack->jack to pcm_rec[].jack to
2144         * align with dyn_pcm_assign mode
2145         */
2146        spec->pcm_rec[pcm_idx].jack = jack->jack;
2147        return 0;
2148}
2149
2150static int generic_hdmi_build_controls(struct hda_codec *codec)
2151{
2152        struct hdmi_spec *spec = codec->spec;
2153        int dev, err;
2154        int pin_idx, pcm_idx;
2155
2156        for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2157                if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2158                        /* no PCM: mark this for skipping permanently */
2159                        set_bit(pcm_idx, &spec->pcm_bitmap);
2160                        continue;
2161                }
2162
2163                err = generic_hdmi_build_jack(codec, pcm_idx);
2164                if (err < 0)
2165                        return err;
2166
2167                /* create the spdif for each pcm
2168                 * pin will be bound when monitor is connected
2169                 */
2170                if (spec->dyn_pcm_assign)
2171                        err = snd_hda_create_dig_out_ctls(codec,
2172                                          0, spec->cvt_nids[0],
2173                                          HDA_PCM_TYPE_HDMI);
2174                else {
2175                        struct hdmi_spec_per_pin *per_pin =
2176                                get_pin(spec, pcm_idx);
2177                        err = snd_hda_create_dig_out_ctls(codec,
2178                                                  per_pin->pin_nid,
2179                                                  per_pin->mux_nids[0],
2180                                                  HDA_PCM_TYPE_HDMI);
2181                }
2182                if (err < 0)
2183                        return err;
2184                snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2185
2186                dev = get_pcm_rec(spec, pcm_idx)->device;
2187                if (dev != SNDRV_PCM_INVALID_DEVICE) {
2188                        /* add control for ELD Bytes */
2189                        err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2190                        if (err < 0)
2191                                return err;
2192                }
2193        }
2194
2195        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2196                struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2197
2198                hdmi_present_sense(per_pin, 0);
2199        }
2200
2201        /* add channel maps */
2202        for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2203                struct hda_pcm *pcm;
2204
2205                pcm = get_pcm_rec(spec, pcm_idx);
2206                if (!pcm || !pcm->pcm)
2207                        break;
2208                err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2209                if (err < 0)
2210                        return err;
2211        }
2212
2213        return 0;
2214}
2215
2216static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2217{
2218        struct hdmi_spec *spec = codec->spec;
2219        int pin_idx;
2220
2221        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2222                struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2223
2224                per_pin->codec = codec;
2225                mutex_init(&per_pin->lock);
2226                INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2227                eld_proc_new(per_pin, pin_idx);
2228        }
2229        return 0;
2230}
2231
2232static int generic_hdmi_init(struct hda_codec *codec)
2233{
2234        struct hdmi_spec *spec = codec->spec;
2235        int pin_idx;
2236
2237        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2238                struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2239                hda_nid_t pin_nid = per_pin->pin_nid;
2240                int dev_id = per_pin->dev_id;
2241
2242                snd_hda_set_dev_select(codec, pin_nid, dev_id);
2243                hdmi_init_pin(codec, pin_nid);
2244                if (!codec_has_acomp(codec))
2245                        snd_hda_jack_detect_enable_callback(codec, pin_nid,
2246                                codec->jackpoll_interval > 0 ?
2247                                jack_callback : NULL);
2248        }
2249        return 0;
2250}
2251
2252static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2253{
2254        snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2255        snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2256}
2257
2258static void hdmi_array_free(struct hdmi_spec *spec)
2259{
2260        snd_array_free(&spec->pins);
2261        snd_array_free(&spec->cvts);
2262}
2263
2264static void generic_spec_free(struct hda_codec *codec)
2265{
2266        struct hdmi_spec *spec = codec->spec;
2267
2268        if (spec) {
2269                hdmi_array_free(spec);
2270                kfree(spec);
2271                codec->spec = NULL;
2272        }
2273        codec->dp_mst = false;
2274}
2275
2276static void generic_hdmi_free(struct hda_codec *codec)
2277{
2278        struct hdmi_spec *spec = codec->spec;
2279        int pin_idx, pcm_idx;
2280
2281        if (codec_has_acomp(codec))
2282                snd_hdac_i915_register_notifier(NULL);
2283
2284        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2285                struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2286                cancel_delayed_work_sync(&per_pin->work);
2287                eld_proc_free(per_pin);
2288        }
2289
2290        for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2291                if (spec->pcm_rec[pcm_idx].jack == NULL)
2292                        continue;
2293                if (spec->dyn_pcm_assign)
2294                        snd_device_free(codec->card,
2295                                        spec->pcm_rec[pcm_idx].jack);
2296                else
2297                        spec->pcm_rec[pcm_idx].jack = NULL;
2298        }
2299
2300        generic_spec_free(codec);
2301}
2302
2303#ifdef CONFIG_PM
2304static int generic_hdmi_resume(struct hda_codec *codec)
2305{
2306        struct hdmi_spec *spec = codec->spec;
2307        int pin_idx;
2308
2309        codec->patch_ops.init(codec);
2310        regcache_sync(codec->core.regmap);
2311
2312        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2313                struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2314                hdmi_present_sense(per_pin, 1);
2315        }
2316        return 0;
2317}
2318#endif
2319
2320static const struct hda_codec_ops generic_hdmi_patch_ops = {
2321        .init                   = generic_hdmi_init,
2322        .free                   = generic_hdmi_free,
2323        .build_pcms             = generic_hdmi_build_pcms,
2324        .build_controls         = generic_hdmi_build_controls,
2325        .unsol_event            = hdmi_unsol_event,
2326#ifdef CONFIG_PM
2327        .resume                 = generic_hdmi_resume,
2328#endif
2329};
2330
2331static const struct hdmi_ops generic_standard_hdmi_ops = {
2332        .pin_get_eld                            = snd_hdmi_get_eld,
2333        .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2334        .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2335        .setup_stream                           = hdmi_setup_stream,
2336};
2337
2338/* allocate codec->spec and assign/initialize generic parser ops */
2339static int alloc_generic_hdmi(struct hda_codec *codec)
2340{
2341        struct hdmi_spec *spec;
2342
2343        spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2344        if (!spec)
2345                return -ENOMEM;
2346
2347        spec->ops = generic_standard_hdmi_ops;
2348        spec->dev_num = 1;      /* initialize to 1 */
2349        mutex_init(&spec->pcm_lock);
2350        snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2351
2352        spec->chmap.ops.get_chmap = hdmi_get_chmap;
2353        spec->chmap.ops.set_chmap = hdmi_set_chmap;
2354        spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2355        spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2356
2357        codec->spec = spec;
2358        hdmi_array_init(spec, 4);
2359
2360        codec->patch_ops = generic_hdmi_patch_ops;
2361
2362        return 0;
2363}
2364
2365/* generic HDMI parser */
2366static int patch_generic_hdmi(struct hda_codec *codec)
2367{
2368        int err;
2369
2370        err = alloc_generic_hdmi(codec);
2371        if (err < 0)
2372                return err;
2373
2374        err = hdmi_parse_codec(codec);
2375        if (err < 0) {
2376                generic_spec_free(codec);
2377                return err;
2378        }
2379
2380        generic_hdmi_init_per_pins(codec);
2381        return 0;
2382}
2383
2384/*
2385 * Intel codec parsers and helpers
2386 */
2387
2388static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2389                                             hda_nid_t nid)
2390{
2391        struct hdmi_spec *spec = codec->spec;
2392        hda_nid_t conns[4];
2393        int nconns;
2394
2395        nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2396        if (nconns == spec->num_cvts &&
2397            !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2398                return;
2399
2400        /* override pins connection list */
2401        codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2402        snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2403}
2404
2405#define INTEL_VENDOR_NID 0x08
2406#define INTEL_GLK_VENDOR_NID 0x0B
2407#define INTEL_GET_VENDOR_VERB 0xf81
2408#define INTEL_SET_VENDOR_VERB 0x781
2409#define INTEL_EN_DP12                   0x02 /* enable DP 1.2 features */
2410#define INTEL_EN_ALL_PIN_CVTS   0x01 /* enable 2nd & 3rd pins and convertors */
2411
2412static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2413                                          bool update_tree)
2414{
2415        unsigned int vendor_param;
2416        struct hdmi_spec *spec = codec->spec;
2417
2418        vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2419                                INTEL_GET_VENDOR_VERB, 0);
2420        if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2421                return;
2422
2423        vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2424        vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2425                                INTEL_SET_VENDOR_VERB, vendor_param);
2426        if (vendor_param == -1)
2427                return;
2428
2429        if (update_tree)
2430                snd_hda_codec_update_widgets(codec);
2431}
2432
2433static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2434{
2435        unsigned int vendor_param;
2436        struct hdmi_spec *spec = codec->spec;
2437
2438        vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2439                                INTEL_GET_VENDOR_VERB, 0);
2440        if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2441                return;
2442
2443        /* enable DP1.2 mode */
2444        vendor_param |= INTEL_EN_DP12;
2445        snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2446        snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2447                                INTEL_SET_VENDOR_VERB, vendor_param);
2448}
2449
2450/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2451 * Otherwise you may get severe h/w communication errors.
2452 */
2453static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2454                                unsigned int power_state)
2455{
2456        if (power_state == AC_PWRST_D0) {
2457                intel_haswell_enable_all_pins(codec, false);
2458                intel_haswell_fixup_enable_dp12(codec);
2459        }
2460
2461        snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2462        snd_hda_codec_set_power_to_all(codec, fg, power_state);
2463}
2464
2465static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2466{
2467        struct hda_codec *codec = audio_ptr;
2468        int pin_nid;
2469        int dev_id = pipe;
2470
2471        /* we assume only from port-B to port-D */
2472        if (port < 1 || port > 3)
2473                return;
2474
2475        switch (codec->core.vendor_id) {
2476        case 0x80860054: /* ILK */
2477        case 0x80862804: /* ILK */
2478        case 0x80862882: /* VLV */
2479                pin_nid = port + 0x03;
2480                break;
2481        default:
2482                pin_nid = port + 0x04;
2483                break;
2484        }
2485
2486        /* skip notification during system suspend (but not in runtime PM);
2487         * the state will be updated at resume
2488         */
2489        if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2490                return;
2491        /* ditto during suspend/resume process itself */
2492        if (atomic_read(&(codec)->core.in_pm))
2493                return;
2494
2495        snd_hdac_i915_set_bclk(&codec->bus->core);
2496        check_presence_and_report(codec, pin_nid, dev_id);
2497}
2498
2499/* register i915 component pin_eld_notify callback */
2500static void register_i915_notifier(struct hda_codec *codec)
2501{
2502        struct hdmi_spec *spec = codec->spec;
2503
2504        spec->use_acomp_notifier = true;
2505        spec->i915_audio_ops.audio_ptr = codec;
2506        /* intel_audio_codec_enable() or intel_audio_codec_disable()
2507         * will call pin_eld_notify with using audio_ptr pointer
2508         * We need make sure audio_ptr is really setup
2509         */
2510        wmb();
2511        spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2512        snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2513}
2514
2515/* setup_stream ops override for HSW+ */
2516static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2517                                 hda_nid_t pin_nid, u32 stream_tag, int format)
2518{
2519        haswell_verify_D0(codec, cvt_nid, pin_nid);
2520        return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2521}
2522
2523/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2524static void i915_pin_cvt_fixup(struct hda_codec *codec,
2525                               struct hdmi_spec_per_pin *per_pin,
2526                               hda_nid_t cvt_nid)
2527{
2528        if (per_pin) {
2529                snd_hda_set_dev_select(codec, per_pin->pin_nid,
2530                               per_pin->dev_id);
2531                intel_verify_pin_cvt_connect(codec, per_pin);
2532                intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2533                                     per_pin->dev_id, per_pin->mux_idx);
2534        } else {
2535                intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2536        }
2537}
2538
2539/* precondition and allocation for Intel codecs */
2540static int alloc_intel_hdmi(struct hda_codec *codec)
2541{
2542        /* requires i915 binding */
2543        if (!codec->bus->core.audio_component) {
2544                codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2545                return -ENODEV;
2546        }
2547
2548        return alloc_generic_hdmi(codec);
2549}
2550
2551/* parse and post-process for Intel codecs */
2552static int parse_intel_hdmi(struct hda_codec *codec)
2553{
2554        int err;
2555
2556        err = hdmi_parse_codec(codec);
2557        if (err < 0) {
2558                generic_spec_free(codec);
2559                return err;
2560        }
2561
2562        generic_hdmi_init_per_pins(codec);
2563        register_i915_notifier(codec);
2564        return 0;
2565}
2566
2567/* Intel Haswell and onwards; audio component with eld notifier */
2568static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2569{
2570        struct hdmi_spec *spec;
2571        int err;
2572
2573        err = alloc_intel_hdmi(codec);
2574        if (err < 0)
2575                return err;
2576        spec = codec->spec;
2577        codec->dp_mst = true;
2578        spec->dyn_pcm_assign = true;
2579        spec->vendor_nid = vendor_nid;
2580
2581        intel_haswell_enable_all_pins(codec, true);
2582        intel_haswell_fixup_enable_dp12(codec);
2583
2584        /* For Haswell/Broadwell, the controller is also in the power well and
2585         * can cover the codec power request, and so need not set this flag.
2586         */
2587        if (!is_haswell(codec) && !is_broadwell(codec))
2588                codec->core.link_power_control = 1;
2589
2590        codec->patch_ops.set_power_state = haswell_set_power_state;
2591        codec->depop_delay = 0;
2592        codec->auto_runtime_pm = 1;
2593
2594        spec->ops.setup_stream = i915_hsw_setup_stream;
2595        spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2596
2597        return parse_intel_hdmi(codec);
2598}
2599
2600static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2601{
2602        return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2603}
2604
2605static int patch_i915_glk_hdmi(struct hda_codec *codec)
2606{
2607        return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2608}
2609
2610/* Intel Baytrail and Braswell; with eld notifier */
2611static int patch_i915_byt_hdmi(struct hda_codec *codec)
2612{
2613        struct hdmi_spec *spec;
2614        int err;
2615
2616        err = alloc_intel_hdmi(codec);
2617        if (err < 0)
2618                return err;
2619        spec = codec->spec;
2620
2621        /* For Valleyview/Cherryview, only the display codec is in the display
2622         * power well and can use link_power ops to request/release the power.
2623         */
2624        codec->core.link_power_control = 1;
2625
2626        codec->depop_delay = 0;
2627        codec->auto_runtime_pm = 1;
2628
2629        spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2630
2631        return parse_intel_hdmi(codec);
2632}
2633
2634/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2635static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2636{
2637        int err;
2638
2639        err = alloc_intel_hdmi(codec);
2640        if (err < 0)
2641                return err;
2642        return parse_intel_hdmi(codec);
2643}
2644
2645/*
2646 * Shared non-generic implementations
2647 */
2648
2649static int simple_playback_build_pcms(struct hda_codec *codec)
2650{
2651        struct hdmi_spec *spec = codec->spec;
2652        struct hda_pcm *info;
2653        unsigned int chans;
2654        struct hda_pcm_stream *pstr;
2655        struct hdmi_spec_per_cvt *per_cvt;
2656
2657        per_cvt = get_cvt(spec, 0);
2658        chans = get_wcaps(codec, per_cvt->cvt_nid);
2659        chans = get_wcaps_channels(chans);
2660
2661        info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2662        if (!info)
2663                return -ENOMEM;
2664        spec->pcm_rec[0].pcm = info;
2665        info->pcm_type = HDA_PCM_TYPE_HDMI;
2666        pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2667        *pstr = spec->pcm_playback;
2668        pstr->nid = per_cvt->cvt_nid;
2669        if (pstr->channels_max <= 2 && chans && chans <= 16)
2670                pstr->channels_max = chans;
2671
2672        return 0;
2673}
2674
2675/* unsolicited event for jack sensing */
2676static void simple_hdmi_unsol_event(struct hda_codec *codec,
2677                                    unsigned int res)
2678{
2679        snd_hda_jack_set_dirty_all(codec);
2680        snd_hda_jack_report_sync(codec);
2681}
2682
2683/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2684 * as long as spec->pins[] is set correctly
2685 */
2686#define simple_hdmi_build_jack  generic_hdmi_build_jack
2687
2688static int simple_playback_build_controls(struct hda_codec *codec)
2689{
2690        struct hdmi_spec *spec = codec->spec;
2691        struct hdmi_spec_per_cvt *per_cvt;
2692        int err;
2693
2694        per_cvt = get_cvt(spec, 0);
2695        err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2696                                          per_cvt->cvt_nid,
2697                                          HDA_PCM_TYPE_HDMI);
2698        if (err < 0)
2699                return err;
2700        return simple_hdmi_build_jack(codec, 0);
2701}
2702
2703static int simple_playback_init(struct hda_codec *codec)
2704{
2705        struct hdmi_spec *spec = codec->spec;
2706        struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2707        hda_nid_t pin = per_pin->pin_nid;
2708
2709        snd_hda_codec_write(codec, pin, 0,
2710                            AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2711        /* some codecs require to unmute the pin */
2712        if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2713                snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2714                                    AMP_OUT_UNMUTE);
2715        snd_hda_jack_detect_enable(codec, pin);
2716        return 0;
2717}
2718
2719static void simple_playback_free(struct hda_codec *codec)
2720{
2721        struct hdmi_spec *spec = codec->spec;
2722
2723        hdmi_array_free(spec);
2724        kfree(spec);
2725}
2726
2727/*
2728 * Nvidia specific implementations
2729 */
2730
2731#define Nv_VERB_SET_Channel_Allocation          0xF79
2732#define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2733#define Nv_VERB_SET_Audio_Protection_On         0xF98
2734#define Nv_VERB_SET_Audio_Protection_Off        0xF99
2735
2736#define nvhdmi_master_con_nid_7x        0x04
2737#define nvhdmi_master_pin_nid_7x        0x05
2738
2739static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2740        /*front, rear, clfe, rear_surr */
2741        0x6, 0x8, 0xa, 0xc,
2742};
2743
2744static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2745        /* set audio protect on */
2746        { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2747        /* enable digital output on pin widget */
2748        { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2749        {} /* terminator */
2750};
2751
2752static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2753        /* set audio protect on */
2754        { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2755        /* enable digital output on pin widget */
2756        { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2757        { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2758        { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2759        { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2760        { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2761        {} /* terminator */
2762};
2763
2764#ifdef LIMITED_RATE_FMT_SUPPORT
2765/* support only the safe format and rate */
2766#define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
2767#define SUPPORTED_MAXBPS        16
2768#define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
2769#else
2770/* support all rates and formats */
2771#define SUPPORTED_RATES \
2772        (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2773        SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2774         SNDRV_PCM_RATE_192000)
2775#define SUPPORTED_MAXBPS        24
2776#define SUPPORTED_FORMATS \
2777        (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2778#endif
2779
2780static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2781{
2782        snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2783        return 0;
2784}
2785
2786static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2787{
2788        snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2789        return 0;
2790}
2791
2792static const unsigned int channels_2_6_8[] = {
2793        2, 6, 8
2794};
2795
2796static const unsigned int channels_2_8[] = {
2797        2, 8
2798};
2799
2800static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2801        .count = ARRAY_SIZE(channels_2_6_8),
2802        .list = channels_2_6_8,
2803        .mask = 0,
2804};
2805
2806static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2807        .count = ARRAY_SIZE(channels_2_8),
2808        .list = channels_2_8,
2809        .mask = 0,
2810};
2811
2812static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2813                                    struct hda_codec *codec,
2814                                    struct snd_pcm_substream *substream)
2815{
2816        struct hdmi_spec *spec = codec->spec;
2817        const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2818
2819        switch (codec->preset->vendor_id) {
2820        case 0x10de0002:
2821        case 0x10de0003:
2822        case 0x10de0005:
2823        case 0x10de0006:
2824                hw_constraints_channels = &hw_constraints_2_8_channels;
2825                break;
2826        case 0x10de0007:
2827                hw_constraints_channels = &hw_constraints_2_6_8_channels;
2828                break;
2829        default:
2830                break;
2831        }
2832
2833        if (hw_constraints_channels != NULL) {
2834                snd_pcm_hw_constraint_list(substream->runtime, 0,
2835                                SNDRV_PCM_HW_PARAM_CHANNELS,
2836                                hw_constraints_channels);
2837        } else {
2838                snd_pcm_hw_constraint_step(substream->runtime, 0,
2839                                           SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2840        }
2841
2842        return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2843}
2844
2845static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2846                                     struct hda_codec *codec,
2847                                     struct snd_pcm_substream *substream)
2848{
2849        struct hdmi_spec *spec = codec->spec;
2850        return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2851}
2852
2853static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2854                                       struct hda_codec *codec,
2855                                       unsigned int stream_tag,
2856                                       unsigned int format,
2857                                       struct snd_pcm_substream *substream)
2858{
2859        struct hdmi_spec *spec = codec->spec;
2860        return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2861                                             stream_tag, format, substream);
2862}
2863
2864static const struct hda_pcm_stream simple_pcm_playback = {
2865        .substreams = 1,
2866        .channels_min = 2,
2867        .channels_max = 2,
2868        .ops = {
2869                .open = simple_playback_pcm_open,
2870                .close = simple_playback_pcm_close,
2871                .prepare = simple_playback_pcm_prepare
2872        },
2873};
2874
2875static const struct hda_codec_ops simple_hdmi_patch_ops = {
2876        .build_controls = simple_playback_build_controls,
2877        .build_pcms = simple_playback_build_pcms,
2878        .init = simple_playback_init,
2879        .free = simple_playback_free,
2880        .unsol_event = simple_hdmi_unsol_event,
2881};
2882
2883static int patch_simple_hdmi(struct hda_codec *codec,
2884                             hda_nid_t cvt_nid, hda_nid_t pin_nid)
2885{
2886        struct hdmi_spec *spec;
2887        struct hdmi_spec_per_cvt *per_cvt;
2888        struct hdmi_spec_per_pin *per_pin;
2889
2890        spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2891        if (!spec)
2892                return -ENOMEM;
2893
2894        codec->spec = spec;
2895        hdmi_array_init(spec, 1);
2896
2897        spec->multiout.num_dacs = 0;  /* no analog */
2898        spec->multiout.max_channels = 2;
2899        spec->multiout.dig_out_nid = cvt_nid;
2900        spec->num_cvts = 1;
2901        spec->num_pins = 1;
2902        per_pin = snd_array_new(&spec->pins);
2903        per_cvt = snd_array_new(&spec->cvts);
2904        if (!per_pin || !per_cvt) {
2905                simple_playback_free(codec);
2906                return -ENOMEM;
2907        }
2908        per_cvt->cvt_nid = cvt_nid;
2909        per_pin->pin_nid = pin_nid;
2910        spec->pcm_playback = simple_pcm_playback;
2911
2912        codec->patch_ops = simple_hdmi_patch_ops;
2913
2914        return 0;
2915}
2916
2917static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2918                                                    int channels)
2919{
2920        unsigned int chanmask;
2921        int chan = channels ? (channels - 1) : 1;
2922
2923        switch (channels) {
2924        default:
2925        case 0:
2926        case 2:
2927                chanmask = 0x00;
2928                break;
2929        case 4:
2930                chanmask = 0x08;
2931                break;
2932        case 6:
2933                chanmask = 0x0b;
2934                break;
2935        case 8:
2936                chanmask = 0x13;
2937                break;
2938        }
2939
2940        /* Set the audio infoframe channel allocation and checksum fields.  The
2941         * channel count is computed implicitly by the hardware. */
2942        snd_hda_codec_write(codec, 0x1, 0,
2943                        Nv_VERB_SET_Channel_Allocation, chanmask);
2944
2945        snd_hda_codec_write(codec, 0x1, 0,
2946                        Nv_VERB_SET_Info_Frame_Checksum,
2947                        (0x71 - chan - chanmask));
2948}
2949
2950static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2951                                   struct hda_codec *codec,
2952                                   struct snd_pcm_substream *substream)
2953{
2954        struct hdmi_spec *spec = codec->spec;
2955        int i;
2956
2957        snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2958                        0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2959        for (i = 0; i < 4; i++) {
2960                /* set the stream id */
2961                snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2962                                AC_VERB_SET_CHANNEL_STREAMID, 0);
2963                /* set the stream format */
2964                snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2965                                AC_VERB_SET_STREAM_FORMAT, 0);
2966        }
2967
2968        /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2969         * streams are disabled. */
2970        nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2971
2972        return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2973}
2974
2975static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2976                                     struct hda_codec *codec,
2977                                     unsigned int stream_tag,
2978                                     unsigned int format,
2979                                     struct snd_pcm_substream *substream)
2980{
2981        int chs;
2982        unsigned int dataDCC2, channel_id;
2983        int i;
2984        struct hdmi_spec *spec = codec->spec;
2985        struct hda_spdif_out *spdif;
2986        struct hdmi_spec_per_cvt *per_cvt;
2987
2988        mutex_lock(&codec->spdif_mutex);
2989        per_cvt = get_cvt(spec, 0);
2990        spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2991
2992        chs = substream->runtime->channels;
2993
2994        dataDCC2 = 0x2;
2995
2996        /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2997        if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2998                snd_hda_codec_write(codec,
2999                                nvhdmi_master_con_nid_7x,
3000                                0,
3001                                AC_VERB_SET_DIGI_CONVERT_1,
3002                                spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3003
3004        /* set the stream id */
3005        snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3006                        AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3007
3008        /* set the stream format */
3009        snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3010                        AC_VERB_SET_STREAM_FORMAT, format);
3011
3012        /* turn on again (if needed) */
3013        /* enable and set the channel status audio/data flag */
3014        if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3015                snd_hda_codec_write(codec,
3016                                nvhdmi_master_con_nid_7x,
3017                                0,
3018                                AC_VERB_SET_DIGI_CONVERT_1,
3019                                spdif->ctls & 0xff);
3020                snd_hda_codec_write(codec,
3021                                nvhdmi_master_con_nid_7x,
3022                                0,
3023                                AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3024        }
3025
3026        for (i = 0; i < 4; i++) {
3027                if (chs == 2)
3028                        channel_id = 0;
3029                else
3030                        channel_id = i * 2;
3031
3032                /* turn off SPDIF once;
3033                 *otherwise the IEC958 bits won't be updated
3034                 */
3035                if (codec->spdif_status_reset &&
3036                (spdif->ctls & AC_DIG1_ENABLE))
3037                        snd_hda_codec_write(codec,
3038                                nvhdmi_con_nids_7x[i],
3039                                0,
3040                                AC_VERB_SET_DIGI_CONVERT_1,
3041                                spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3042                /* set the stream id */
3043                snd_hda_codec_write(codec,
3044                                nvhdmi_con_nids_7x[i],
3045                                0,
3046                                AC_VERB_SET_CHANNEL_STREAMID,
3047                                (stream_tag << 4) | channel_id);
3048                /* set the stream format */
3049                snd_hda_codec_write(codec,
3050                                nvhdmi_con_nids_7x[i],
3051                                0,
3052                                AC_VERB_SET_STREAM_FORMAT,
3053                                format);
3054                /* turn on again (if needed) */
3055                /* enable and set the channel status audio/data flag */
3056                if (codec->spdif_status_reset &&
3057                (spdif->ctls & AC_DIG1_ENABLE)) {
3058                        snd_hda_codec_write(codec,
3059                                        nvhdmi_con_nids_7x[i],
3060                                        0,
3061                                        AC_VERB_SET_DIGI_CONVERT_1,
3062                                        spdif->ctls & 0xff);
3063                        snd_hda_codec_write(codec,
3064                                        nvhdmi_con_nids_7x[i],
3065                                        0,
3066                                        AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3067                }
3068        }
3069
3070        nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3071
3072        mutex_unlock(&codec->spdif_mutex);
3073        return 0;
3074}
3075
3076static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3077        .substreams = 1,
3078        .channels_min = 2,
3079        .channels_max = 8,
3080        .nid = nvhdmi_master_con_nid_7x,
3081        .rates = SUPPORTED_RATES,
3082        .maxbps = SUPPORTED_MAXBPS,
3083        .formats = SUPPORTED_FORMATS,
3084        .ops = {
3085                .open = simple_playback_pcm_open,
3086                .close = nvhdmi_8ch_7x_pcm_close,
3087                .prepare = nvhdmi_8ch_7x_pcm_prepare
3088        },
3089};
3090
3091static int patch_nvhdmi_2ch(struct hda_codec *codec)
3092{
3093        struct hdmi_spec *spec;
3094        int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3095                                    nvhdmi_master_pin_nid_7x);
3096        if (err < 0)
3097                return err;
3098
3099        codec->patch_ops.init = nvhdmi_7x_init_2ch;
3100        /* override the PCM rates, etc, as the codec doesn't give full list */
3101        spec = codec->spec;
3102        spec->pcm_playback.rates = SUPPORTED_RATES;
3103        spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3104        spec->pcm_playback.formats = SUPPORTED_FORMATS;
3105        return 0;
3106}
3107
3108static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3109{
3110        struct hdmi_spec *spec = codec->spec;
3111        int err = simple_playback_build_pcms(codec);
3112        if (!err) {
3113                struct hda_pcm *info = get_pcm_rec(spec, 0);
3114                info->own_chmap = true;
3115        }
3116        return err;
3117}
3118
3119static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3120{
3121        struct hdmi_spec *spec = codec->spec;
3122        struct hda_pcm *info;
3123        struct snd_pcm_chmap *chmap;
3124        int err;
3125
3126        err = simple_playback_build_controls(codec);
3127        if (err < 0)
3128                return err;
3129
3130        /* add channel maps */
3131        info = get_pcm_rec(spec, 0);
3132        err = snd_pcm_add_chmap_ctls(info->pcm,
3133                                     SNDRV_PCM_STREAM_PLAYBACK,
3134                                     snd_pcm_alt_chmaps, 8, 0, &chmap);
3135        if (err < 0)
3136                return err;
3137        switch (codec->preset->vendor_id) {
3138        case 0x10de0002:
3139        case 0x10de0003:
3140        case 0x10de0005:
3141        case 0x10de0006:
3142                chmap->channel_mask = (1U << 2) | (1U << 8);
3143                break;
3144        case 0x10de0007:
3145                chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3146        }
3147        return 0;
3148}
3149
3150static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3151{
3152        struct hdmi_spec *spec;
3153        int err = patch_nvhdmi_2ch(codec);
3154        if (err < 0)
3155                return err;
3156        spec = codec->spec;
3157        spec->multiout.max_channels = 8;
3158        spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3159        codec->patch_ops.init = nvhdmi_7x_init_8ch;
3160        codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3161        codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3162
3163        /* Initialize the audio infoframe channel mask and checksum to something
3164         * valid */
3165        nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3166
3167        return 0;
3168}
3169
3170/*
3171 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3172 * - 0x10de0015
3173 * - 0x10de0040
3174 */
3175static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3176                struct hdac_cea_channel_speaker_allocation *cap, int channels)
3177{
3178        if (cap->ca_index == 0x00 && channels == 2)
3179                return SNDRV_CTL_TLVT_CHMAP_FIXED;
3180
3181        /* If the speaker allocation matches the channel count, it is OK. */
3182        if (cap->channels != channels)
3183                return -1;
3184
3185        /* all channels are remappable freely */
3186        return SNDRV_CTL_TLVT_CHMAP_VAR;
3187}
3188
3189static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3190                int ca, int chs, unsigned char *map)
3191{
3192        if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3193                return -EINVAL;
3194
3195        return 0;
3196}
3197
3198static int patch_nvhdmi(struct hda_codec *codec)
3199{
3200        struct hdmi_spec *spec;
3201        int err;
3202
3203        err = patch_generic_hdmi(codec);
3204        if (err)
3205                return err;
3206
3207        spec = codec->spec;
3208        spec->dyn_pin_out = true;
3209
3210        spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3211                nvhdmi_chmap_cea_alloc_validate_get_type;
3212        spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3213
3214        return 0;
3215}
3216
3217/*
3218 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3219 * accessed using vendor-defined verbs. These registers can be used for
3220 * interoperability between the HDA and HDMI drivers.
3221 */
3222
3223/* Audio Function Group node */
3224#define NVIDIA_AFG_NID 0x01
3225
3226/*
3227 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3228 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3229 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3230 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3231 * additional bit (at position 30) to signal the validity of the format.
3232 *
3233 * | 31      | 30    | 29  16 | 15   0 |
3234 * +---------+-------+--------+--------+
3235 * | TRIGGER | VALID | UNUSED | FORMAT |
3236 * +-----------------------------------|
3237 *
3238 * Note that for the trigger bit to take effect it needs to change value
3239 * (i.e. it needs to be toggled).
3240 */
3241#define NVIDIA_GET_SCRATCH0             0xfa6
3242#define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
3243#define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
3244#define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
3245#define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
3246#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3247#define NVIDIA_SCRATCH_VALID   (1 << 6)
3248
3249#define NVIDIA_GET_SCRATCH1             0xfab
3250#define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
3251#define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
3252#define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
3253#define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
3254
3255/*
3256 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3257 * the format is invalidated so that the HDMI codec can be disabled.
3258 */
3259static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3260{
3261        unsigned int value;
3262
3263        /* bits [31:30] contain the trigger and valid bits */
3264        value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3265                                   NVIDIA_GET_SCRATCH0, 0);
3266        value = (value >> 24) & 0xff;
3267
3268        /* bits [15:0] are used to store the HDA format */
3269        snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3270                            NVIDIA_SET_SCRATCH0_BYTE0,
3271                            (format >> 0) & 0xff);
3272        snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3273                            NVIDIA_SET_SCRATCH0_BYTE1,
3274                            (format >> 8) & 0xff);
3275
3276        /* bits [16:24] are unused */
3277        snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3278                            NVIDIA_SET_SCRATCH0_BYTE2, 0);
3279
3280        /*
3281         * Bit 30 signals that the data is valid and hence that HDMI audio can
3282         * be enabled.
3283         */
3284        if (format == 0)
3285                value &= ~NVIDIA_SCRATCH_VALID;
3286        else
3287                value |= NVIDIA_SCRATCH_VALID;
3288
3289        /*
3290         * Whenever the trigger bit is toggled, an interrupt is raised in the
3291         * HDMI codec. The HDMI driver will use that as trigger to update its
3292         * configuration.
3293         */
3294        value ^= NVIDIA_SCRATCH_TRIGGER;
3295
3296        snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3297                            NVIDIA_SET_SCRATCH0_BYTE3, value);
3298}
3299
3300static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3301                                  struct hda_codec *codec,
3302                                  unsigned int stream_tag,
3303                                  unsigned int format,
3304                                  struct snd_pcm_substream *substream)
3305{
3306        int err;
3307
3308        err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3309                                                format, substream);
3310        if (err < 0)
3311                return err;
3312
3313        /* notify the HDMI codec of the format change */
3314        tegra_hdmi_set_format(codec, format);
3315
3316        return 0;
3317}
3318
3319static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3320                                  struct hda_codec *codec,
3321                                  struct snd_pcm_substream *substream)
3322{
3323        /* invalidate the format in the HDMI codec */
3324        tegra_hdmi_set_format(codec, 0);
3325
3326        return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3327}
3328
3329static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3330{
3331        struct hdmi_spec *spec = codec->spec;
3332        unsigned int i;
3333
3334        for (i = 0; i < spec->num_pins; i++) {
3335                struct hda_pcm *pcm = get_pcm_rec(spec, i);
3336
3337                if (pcm->pcm_type == type)
3338                        return pcm;
3339        }
3340
3341        return NULL;
3342}
3343
3344static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3345{
3346        struct hda_pcm_stream *stream;
3347        struct hda_pcm *pcm;
3348        int err;
3349
3350        err = generic_hdmi_build_pcms(codec);
3351        if (err < 0)
3352                return err;
3353
3354        pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3355        if (!pcm)
3356                return -ENODEV;
3357
3358        /*
3359         * Override ->prepare() and ->cleanup() operations to notify the HDMI
3360         * codec about format changes.
3361         */
3362        stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3363        stream->ops.prepare = tegra_hdmi_pcm_prepare;
3364        stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3365
3366        return 0;
3367}
3368
3369static int patch_tegra_hdmi(struct hda_codec *codec)
3370{
3371        int err;
3372
3373        err = patch_generic_hdmi(codec);
3374        if (err)
3375                return err;
3376
3377        codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3378
3379        return 0;
3380}
3381
3382/*
3383 * ATI/AMD-specific implementations
3384 */
3385
3386#define is_amdhdmi_rev3_or_later(codec) \
3387        ((codec)->core.vendor_id == 0x1002aa01 && \
3388         ((codec)->core.revision_id & 0xff00) >= 0x0300)
3389#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3390
3391/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3392#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3393#define ATI_VERB_SET_DOWNMIX_INFO       0x772
3394#define ATI_VERB_SET_MULTICHANNEL_01    0x777
3395#define ATI_VERB_SET_MULTICHANNEL_23    0x778
3396#define ATI_VERB_SET_MULTICHANNEL_45    0x779
3397#define ATI_VERB_SET_MULTICHANNEL_67    0x77a
3398#define ATI_VERB_SET_HBR_CONTROL        0x77c
3399#define ATI_VERB_SET_MULTICHANNEL_1     0x785
3400#define ATI_VERB_SET_MULTICHANNEL_3     0x786
3401#define ATI_VERB_SET_MULTICHANNEL_5     0x787
3402#define ATI_VERB_SET_MULTICHANNEL_7     0x788
3403#define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
3404#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3405#define ATI_VERB_GET_DOWNMIX_INFO       0xf72
3406#define ATI_VERB_GET_MULTICHANNEL_01    0xf77
3407#define ATI_VERB_GET_MULTICHANNEL_23    0xf78
3408#define ATI_VERB_GET_MULTICHANNEL_45    0xf79
3409#define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
3410#define ATI_VERB_GET_HBR_CONTROL        0xf7c
3411#define ATI_VERB_GET_MULTICHANNEL_1     0xf85
3412#define ATI_VERB_GET_MULTICHANNEL_3     0xf86
3413#define ATI_VERB_GET_MULTICHANNEL_5     0xf87
3414#define ATI_VERB_GET_MULTICHANNEL_7     0xf88
3415#define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
3416
3417/* AMD specific HDA cvt verbs */
3418#define ATI_VERB_SET_RAMP_RATE          0x770
3419#define ATI_VERB_GET_RAMP_RATE          0xf70
3420
3421#define ATI_OUT_ENABLE 0x1
3422
3423#define ATI_MULTICHANNEL_MODE_PAIRED    0
3424#define ATI_MULTICHANNEL_MODE_SINGLE    1
3425
3426#define ATI_HBR_CAPABLE 0x01
3427#define ATI_HBR_ENABLE 0x10
3428
3429static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3430                           unsigned char *buf, int *eld_size)
3431{
3432        /* call hda_eld.c ATI/AMD-specific function */
3433        return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3434                                    is_amdhdmi_rev3_or_later(codec));
3435}
3436
3437static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3438                                        int active_channels, int conn_type)
3439{
3440        snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3441}
3442
3443static int atihdmi_paired_swap_fc_lfe(int pos)
3444{
3445        /*
3446         * ATI/AMD have automatic FC/LFE swap built-in
3447         * when in pairwise mapping mode.
3448         */
3449
3450        switch (pos) {
3451                /* see channel_allocations[].speakers[] */
3452                case 2: return 3;
3453                case 3: return 2;
3454                default: break;
3455        }
3456
3457        return pos;
3458}
3459
3460static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3461                        int ca, int chs, unsigned char *map)
3462{
3463        struct hdac_cea_channel_speaker_allocation *cap;
3464        int i, j;
3465
3466        /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3467
3468        cap = snd_hdac_get_ch_alloc_from_ca(ca);
3469        for (i = 0; i < chs; ++i) {
3470                int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3471                bool ok = false;
3472                bool companion_ok = false;
3473
3474                if (!mask)
3475                        continue;
3476
3477                for (j = 0 + i % 2; j < 8; j += 2) {
3478                        int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3479                        if (cap->speakers[chan_idx] == mask) {
3480                                /* channel is in a supported position */
3481                                ok = true;
3482
3483                                if (i % 2 == 0 && i + 1 < chs) {
3484                                        /* even channel, check the odd companion */
3485                                        int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3486                                        int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3487                                        int comp_mask_act = cap->speakers[comp_chan_idx];
3488
3489                                        if (comp_mask_req == comp_mask_act)
3490                                                companion_ok = true;
3491                                        else
3492                                                return -EINVAL;
3493                                }
3494                                break;
3495                        }
3496                }
3497
3498                if (!ok)
3499                        return -EINVAL;
3500
3501                if (companion_ok)
3502                        i++; /* companion channel already checked */
3503        }
3504
3505        return 0;
3506}
3507
3508static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3509                hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3510{
3511        struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3512        int verb;
3513        int ati_channel_setup = 0;
3514
3515        if (hdmi_slot > 7)
3516                return -EINVAL;
3517
3518        if (!has_amd_full_remap_support(codec)) {
3519                hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3520
3521                /* In case this is an odd slot but without stream channel, do not
3522                 * disable the slot since the corresponding even slot could have a
3523                 * channel. In case neither have a channel, the slot pair will be
3524                 * disabled when this function is called for the even slot. */
3525                if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3526                        return 0;
3527
3528                hdmi_slot -= hdmi_slot % 2;
3529
3530                if (stream_channel != 0xf)
3531                        stream_channel -= stream_channel % 2;
3532        }
3533
3534        verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3535
3536        /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3537
3538        if (stream_channel != 0xf)
3539                ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3540
3541        return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3542}
3543
3544static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3545                                hda_nid_t pin_nid, int asp_slot)
3546{
3547        struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3548        bool was_odd = false;
3549        int ati_asp_slot = asp_slot;
3550        int verb;
3551        int ati_channel_setup;
3552
3553        if (asp_slot > 7)
3554                return -EINVAL;
3555
3556        if (!has_amd_full_remap_support(codec)) {
3557                ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3558                if (ati_asp_slot % 2 != 0) {
3559                        ati_asp_slot -= 1;
3560                        was_odd = true;
3561                }
3562        }
3563
3564        verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3565
3566        ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3567
3568        if (!(ati_channel_setup & ATI_OUT_ENABLE))
3569                return 0xf;
3570
3571        return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3572}
3573
3574static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3575                struct hdac_chmap *chmap,
3576                struct hdac_cea_channel_speaker_allocation *cap,
3577                int channels)
3578{
3579        int c;
3580
3581        /*
3582         * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3583         * we need to take that into account (a single channel may take 2
3584         * channel slots if we need to carry a silent channel next to it).
3585         * On Rev3+ AMD codecs this function is not used.
3586         */
3587        int chanpairs = 0;
3588
3589        /* We only produce even-numbered channel count TLVs */
3590        if ((channels % 2) != 0)
3591                return -1;
3592
3593        for (c = 0; c < 7; c += 2) {
3594                if (cap->speakers[c] || cap->speakers[c+1])
3595                        chanpairs++;
3596        }
3597
3598        if (chanpairs * 2 != channels)
3599                return -1;
3600
3601        return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3602}
3603
3604static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3605                struct hdac_cea_channel_speaker_allocation *cap,
3606                unsigned int *chmap, int channels)
3607{
3608        /* produce paired maps for pre-rev3 ATI/AMD codecs */
3609        int count = 0;
3610        int c;
3611
3612        for (c = 7; c >= 0; c--) {
3613                int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3614                int spk = cap->speakers[chan];
3615                if (!spk) {
3616                        /* add N/A channel if the companion channel is occupied */
3617                        if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3618                                chmap[count++] = SNDRV_CHMAP_NA;
3619
3620                        continue;
3621                }
3622
3623                chmap[count++] = snd_hdac_spk_to_chmap(spk);
3624        }
3625
3626        WARN_ON(count != channels);
3627}
3628
3629static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3630                                 bool hbr)
3631{
3632        int hbr_ctl, hbr_ctl_new;
3633
3634        hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3635        if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3636                if (hbr)
3637                        hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3638                else
3639                        hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3640
3641                codec_dbg(codec,
3642                          "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3643                                pin_nid,
3644                                hbr_ctl == hbr_ctl_new ? "" : "new-",
3645                                hbr_ctl_new);
3646
3647                if (hbr_ctl != hbr_ctl_new)
3648                        snd_hda_codec_write(codec, pin_nid, 0,
3649                                                ATI_VERB_SET_HBR_CONTROL,
3650                                                hbr_ctl_new);
3651
3652        } else if (hbr)
3653                return -EINVAL;
3654
3655        return 0;
3656}
3657
3658static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3659                                hda_nid_t pin_nid, u32 stream_tag, int format)
3660{
3661
3662        if (is_amdhdmi_rev3_or_later(codec)) {
3663                int ramp_rate = 180; /* default as per AMD spec */
3664                /* disable ramp-up/down for non-pcm as per AMD spec */
3665                if (format & AC_FMT_TYPE_NON_PCM)
3666                        ramp_rate = 0;
3667
3668                snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3669        }
3670
3671        return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3672}
3673
3674
3675static int atihdmi_init(struct hda_codec *codec)
3676{
3677        struct hdmi_spec *spec = codec->spec;
3678        int pin_idx, err;
3679
3680        err = generic_hdmi_init(codec);
3681
3682        if (err)
3683                return err;
3684
3685        for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3686                struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3687
3688                /* make sure downmix information in infoframe is zero */
3689                snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3690
3691                /* enable channel-wise remap mode if supported */
3692                if (has_amd_full_remap_support(codec))
3693                        snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3694                                            ATI_VERB_SET_MULTICHANNEL_MODE,
3695                                            ATI_MULTICHANNEL_MODE_SINGLE);
3696        }
3697
3698        return 0;
3699}
3700
3701static int patch_atihdmi(struct hda_codec *codec)
3702{
3703        struct hdmi_spec *spec;
3704        struct hdmi_spec_per_cvt *per_cvt;
3705        int err, cvt_idx;
3706
3707        err = patch_generic_hdmi(codec);
3708
3709        if (err)
3710                return err;
3711
3712        codec->patch_ops.init = atihdmi_init;
3713
3714        spec = codec->spec;
3715
3716        spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3717        spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3718        spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3719        spec->ops.setup_stream = atihdmi_setup_stream;
3720
3721        spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3722        spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3723
3724        if (!has_amd_full_remap_support(codec)) {
3725                /* override to ATI/AMD-specific versions with pairwise mapping */
3726                spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3727                        atihdmi_paired_chmap_cea_alloc_validate_get_type;
3728                spec->chmap.ops.cea_alloc_to_tlv_chmap =
3729                                atihdmi_paired_cea_alloc_to_tlv_chmap;
3730                spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3731        }
3732
3733        /* ATI/AMD converters do not advertise all of their capabilities */
3734        for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3735                per_cvt = get_cvt(spec, cvt_idx);
3736                per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3737                per_cvt->rates |= SUPPORTED_RATES;
3738                per_cvt->formats |= SUPPORTED_FORMATS;
3739                per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3740        }
3741
3742        spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3743
3744        return 0;
3745}
3746
3747/* VIA HDMI Implementation */
3748#define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
3749#define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
3750
3751static int patch_via_hdmi(struct hda_codec *codec)
3752{
3753        return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3754}
3755
3756/*
3757 * patch entries
3758 */
3759static const struct hda_device_id snd_hda_id_hdmi[] = {
3760HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",       patch_atihdmi),
3761HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",       patch_atihdmi),
3762HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",   patch_atihdmi),
3763HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",        patch_atihdmi),
3764HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",     patch_generic_hdmi),
3765HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",     patch_generic_hdmi),
3766HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",    patch_generic_hdmi),
3767HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3768HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3769HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3770HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI",      patch_nvhdmi_8ch_7x),
3771HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3772HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3773HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",    patch_nvhdmi_8ch_7x),
3774HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP",   patch_nvhdmi),
3775HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP",   patch_nvhdmi),
3776HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",   patch_nvhdmi),
3777HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",   patch_nvhdmi),
3778HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",       patch_nvhdmi),
3779HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",   patch_nvhdmi),
3780HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",   patch_nvhdmi),
3781HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",   patch_nvhdmi),
3782HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",   patch_nvhdmi),
3783HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",   patch_nvhdmi),
3784HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",   patch_nvhdmi),
3785HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",   patch_nvhdmi),
3786HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",   patch_nvhdmi),
3787/* 17 is known to be absent */
3788HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",   patch_nvhdmi),
3789HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",   patch_nvhdmi),
3790HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",   patch_nvhdmi),
3791HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",   patch_nvhdmi),
3792HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",   patch_nvhdmi),
3793HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",     patch_tegra_hdmi),
3794HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",    patch_tegra_hdmi),
3795HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",    patch_tegra_hdmi),
3796HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3797HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",   patch_nvhdmi),
3798HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",   patch_nvhdmi),
3799HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",   patch_nvhdmi),
3800HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",   patch_nvhdmi),
3801HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",   patch_nvhdmi),
3802HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP",   patch_nvhdmi),
3803HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP",   patch_nvhdmi),
3804HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",   patch_nvhdmi),
3805HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP",   patch_nvhdmi),
3806HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",   patch_nvhdmi),
3807HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP",   patch_nvhdmi),
3808HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP",   patch_nvhdmi),
3809HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",       patch_nvhdmi_2ch),
3810HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",   patch_nvhdmi),
3811HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",   patch_nvhdmi),
3812HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",   patch_nvhdmi),
3813HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP",   patch_nvhdmi),
3814HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP",   patch_nvhdmi),
3815HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP",   patch_nvhdmi),
3816HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP",   patch_nvhdmi),
3817HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP",   patch_nvhdmi),
3818HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",   patch_nvhdmi),
3819HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP",   patch_nvhdmi),
3820HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP",   patch_nvhdmi),
3821HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP",   patch_nvhdmi),
3822HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP",   patch_nvhdmi),
3823HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP",   patch_nvhdmi),
3824HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP",   patch_nvhdmi),
3825HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP",   patch_nvhdmi),
3826HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP",   patch_nvhdmi),
3827HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP",   patch_nvhdmi),
3828HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP",   patch_nvhdmi),
3829HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP",   patch_nvhdmi),
3830HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP",   patch_nvhdmi),
3831HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP",   patch_nvhdmi),
3832HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP",   patch_nvhdmi),
3833HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP",   patch_nvhdmi),
3834HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3835HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI",    patch_nvhdmi_2ch),
3836HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",    patch_via_hdmi),
3837HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",    patch_via_hdmi),
3838HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",     patch_generic_hdmi),
3839HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",     patch_generic_hdmi),
3840HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
3841HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",    patch_generic_hdmi),
3842HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",     patch_generic_hdmi),
3843HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",   patch_generic_hdmi),
3844HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
3845HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3846HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3847HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",     patch_i915_hsw_hdmi),
3848HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",   patch_i915_hsw_hdmi),
3849HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",     patch_i915_hsw_hdmi),
3850HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",     patch_i915_hsw_hdmi),
3851HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",    patch_i915_hsw_hdmi),
3852HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI",  patch_i915_glk_hdmi),
3853HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI",  patch_i915_glk_hdmi),
3854HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI",  patch_i915_glk_hdmi),
3855HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",  patch_generic_hdmi),
3856HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3857HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",    patch_i915_byt_hdmi),
3858HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",   patch_generic_hdmi),
3859/* special ID for generic HDMI */
3860HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3861{} /* terminator */
3862};
3863MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3864
3865MODULE_LICENSE("GPL");
3866MODULE_DESCRIPTION("HDMI HD-audio codec");
3867MODULE_ALIAS("snd-hda-codec-intelhdmi");
3868MODULE_ALIAS("snd-hda-codec-nvhdmi");
3869MODULE_ALIAS("snd-hda-codec-atihdmi");
3870
3871static struct hda_codec_driver hdmi_driver = {
3872        .id = snd_hda_id_hdmi,
3873};
3874
3875module_hda_codec_driver(hdmi_driver);
3876