LXR linux/sound/soc/codecs/cs43130.h

   1/*
   2 * ALSA SoC CS43130 codec driver
   3 *
   4 * Copyright 2017 Cirrus Logic, Inc.
   5 *
   6 * Author: Li Xu <li.xu@cirrus.com>
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License
  10 * version 2 as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope that it will be useful, but
  13 * WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 */
  18
  19#ifndef __CS43130_H__
  20#define __CS43130_H__
  21
  22/* CS43130 registers addresses */
  23/* all reg address is shifted by a byte for control byte to be LSB */
  24#define CS43130_FIRSTREG        0x010000
  25#define CS43130_LASTREG         0x190000
  26#define CS43130_CHIP_ID         0x00043130
  27#define CS4399_CHIP_ID          0x00043990
  28#define CS43131_CHIP_ID         0x00043131
  29#define CS43198_CHIP_ID         0x00043198
  30#define CS43130_DEVID_AB        0x010000        /* Device ID A & B [RO] */
  31#define CS43130_DEVID_CD        0x010001        /* Device ID C & D [RO] */
  32#define CS43130_DEVID_E         0x010002        /* Device ID E [RO] */
  33#define CS43130_FAB_ID          0x010003        /* Fab ID [RO] */
  34#define CS43130_REV_ID          0x010004        /* Revision ID [RO] */
  35#define CS43130_SUBREV_ID       0x010005        /* Subrevision ID */
  36#define CS43130_SYS_CLK_CTL_1   0x010006        /* System Clocking Ctl 1 */
  37#define CS43130_SP_SRATE        0x01000B        /* Serial Port Sample Rate */
  38#define CS43130_SP_BITSIZE      0x01000C        /* Serial Port Bit Size */
  39#define CS43130_PAD_INT_CFG     0x01000D        /* Pad Interface Config */
  40#define CS43130_DXD1            0x010010        /* DXD1 */
  41#define CS43130_DXD7            0x010025        /* DXD7 */
  42#define CS43130_DXD19           0x010026        /* DXD19 */
  43#define CS43130_DXD17           0x010027        /* DXD17 */
  44#define CS43130_DXD18           0x010028        /* DXD18 */
  45#define CS43130_DXD12           0x01002C        /* DXD12 */
  46#define CS43130_DXD8            0x01002E        /* DXD8 */
  47#define CS43130_PWDN_CTL        0x020000        /* Power Down Ctl */
  48#define CS43130_DXD2            0x020019        /* DXD2 */
  49#define CS43130_CRYSTAL_SET     0x020052        /* Crystal Setting */
  50#define CS43130_PLL_SET_1       0x030001        /* PLL Setting 1 */
  51#define CS43130_PLL_SET_2       0x030002        /* PLL Setting 2 */
  52#define CS43130_PLL_SET_3       0x030003        /* PLL Setting 3 */
  53#define CS43130_PLL_SET_4       0x030004        /* PLL Setting 4 */
  54#define CS43130_PLL_SET_5       0x030005        /* PLL Setting 5 */
  55#define CS43130_PLL_SET_6       0x030008        /* PLL Setting 6 */
  56#define CS43130_PLL_SET_7       0x03000A        /* PLL Setting 7 */
  57#define CS43130_PLL_SET_8       0x03001B        /* PLL Setting 8 */
  58#define CS43130_PLL_SET_9       0x040002        /* PLL Setting 9 */
  59#define CS43130_PLL_SET_10      0x040003        /* PLL Setting 10 */
  60#define CS43130_CLKOUT_CTL      0x040004        /* CLKOUT Ctl */
  61#define CS43130_ASP_NUM_1       0x040010        /* ASP Numerator 1 */
  62#define CS43130_ASP_NUM_2       0x040011        /* ASP Numerator 2 */
  63#define CS43130_ASP_DEN_1       0x040012        /* ASP Denominator 1 */
  64#define CS43130_ASP_DEN_2       0x040013        /* ASP Denominator 2 */
  65#define CS43130_ASP_LRCK_HI_TIME_1 0x040014     /* ASP LRCK High Time 1 */
  66#define CS43130_ASP_LRCK_HI_TIME_2 0x040015     /* ASP LRCK High Time 2 */
  67#define CS43130_ASP_LRCK_PERIOD_1  0x040016     /* ASP LRCK Period 1 */
  68#define CS43130_ASP_LRCK_PERIOD_2  0x040017     /* ASP LRCK Period 2 */
  69#define CS43130_ASP_CLOCK_CONF  0x040018        /* ASP Clock Config */
  70#define CS43130_ASP_FRAME_CONF  0x040019        /* ASP Frame Config */
  71#define CS43130_XSP_NUM_1       0x040020        /* XSP Numerator 1 */
  72#define CS43130_XSP_NUM_2       0x040021        /* XSP Numerator 2 */
  73#define CS43130_XSP_DEN_1       0x040022        /* XSP Denominator 1 */
  74#define CS43130_XSP_DEN_2       0x040023        /* XSP Denominator 2 */
  75#define CS43130_XSP_LRCK_HI_TIME_1 0x040024     /* XSP LRCK High Time 1 */
  76#define CS43130_XSP_LRCK_HI_TIME_2 0x040025     /* XSP LRCK High Time 2 */
  77#define CS43130_XSP_LRCK_PERIOD_1  0x040026     /* XSP LRCK Period 1 */
  78#define CS43130_XSP_LRCK_PERIOD_2  0x040027     /* XSP LRCK Period 2 */
  79#define CS43130_XSP_CLOCK_CONF  0x040028        /* XSP Clock Config */
  80#define CS43130_XSP_FRAME_CONF  0x040029        /* XSP Frame Config */
  81#define CS43130_ASP_CH_1_LOC    0x050000        /* ASP Chan 1 Location */
  82#define CS43130_ASP_CH_2_LOC    0x050001        /* ASP Chan 2 Location */
  83#define CS43130_ASP_CH_1_SZ_EN  0x05000A        /* ASP Chan 1 Size, Enable */
  84#define CS43130_ASP_CH_2_SZ_EN  0x05000B        /* ASP Chan 2 Size, Enable */
  85#define CS43130_XSP_CH_1_LOC    0x060000        /* XSP Chan 1 Location */
  86#define CS43130_XSP_CH_2_LOC    0x060001        /* XSP Chan 2 Location */
  87#define CS43130_XSP_CH_1_SZ_EN  0x06000A        /* XSP Chan 1 Size, Enable */
  88#define CS43130_XSP_CH_2_SZ_EN  0x06000B        /* XSP Chan 2 Size, Enable */
  89#define CS43130_DSD_VOL_B       0x070000        /* DSD Volume B */
  90#define CS43130_DSD_VOL_A       0x070001        /* DSD Volume A */
  91#define CS43130_DSD_PATH_CTL_1  0x070002        /* DSD Proc Path Sig Ctl 1 */
  92#define CS43130_DSD_INT_CFG     0x070003        /* DSD Interface Config */
  93#define CS43130_DSD_PATH_CTL_2  0x070004        /* DSD Proc Path Sig Ctl 2 */
  94#define CS43130_DSD_PCM_MIX_CTL 0x070005        /* DSD and PCM Mixing Ctl */
  95#define CS43130_DSD_PATH_CTL_3  0x070006        /* DSD Proc Path Sig Ctl 3 */
  96#define CS43130_HP_OUT_CTL_1    0x080000        /* HP Output Ctl 1 */
  97#define CS43130_DXD16           0x080024        /* DXD16 */
  98#define CS43130_DXD13           0x080032        /* DXD13 */
  99#define CS43130_PCM_FILT_OPT    0x090000        /* PCM Filter Option */
 100#define CS43130_PCM_VOL_B       0x090001        /* PCM Volume B */
 101#define CS43130_PCM_VOL_A       0x090002        /* PCM Volume A */
 102#define CS43130_PCM_PATH_CTL_1  0x090003        /* PCM Path Signal Ctl 1 */
 103#define CS43130_PCM_PATH_CTL_2  0x090004        /* PCM Path Signal Ctl 2 */
 104#define CS43130_DXD6            0x090097        /* DXD6 */
 105#define CS43130_CLASS_H_CTL     0x0B0000        /* Class H Ctl */
 106#define CS43130_DXD15           0x0B0005        /* DXD15 */
 107#define CS43130_DXD14           0x0B0006        /* DXD14 */
 108#define CS43130_DXD3            0x0C0002        /* DXD3 */
 109#define CS43130_DXD10           0x0C0003        /* DXD10 */
 110#define CS43130_DXD11           0x0C0005        /* DXD11 */
 111#define CS43130_DXD9            0x0C0006        /* DXD9 */
 112#define CS43130_DXD4            0x0C0009        /* DXD4 */
 113#define CS43130_DXD5            0x0C000E        /* DXD5 */
 114#define CS43130_HP_DETECT       0x0D0000        /* HP Detect */
 115#define CS43130_HP_STATUS       0x0D0001        /* HP Status [RO] */
 116#define CS43130_HP_LOAD_1       0x0E0000        /* HP Load 1 */
 117#define CS43130_HP_MEAS_LOAD_1  0x0E0003        /* HP Load Measurement 1 */
 118#define CS43130_HP_MEAS_LOAD_2  0x0E0004        /* HP Load Measurement 2 */
 119#define CS43130_HP_DC_STAT_1    0x0E000D        /* HP DC Load Status 0 [RO] */
 120#define CS43130_HP_DC_STAT_2    0x0E000E        /* HP DC Load Status 1 [RO] */
 121#define CS43130_HP_AC_STAT_1    0x0E0010        /* HP AC Load Status 0 [RO] */
 122#define CS43130_HP_AC_STAT_2    0x0E0011        /* HP AC Load Status 1 [RO] */
 123#define CS43130_HP_LOAD_STAT    0x0E001A        /* HP Load Status [RO] */
 124#define CS43130_INT_STATUS_1    0x0F0000        /* Interrupt Status 1 */
 125#define CS43130_INT_STATUS_2    0x0F0001        /* Interrupt Status 2 */
 126#define CS43130_INT_STATUS_3    0x0F0002        /* Interrupt Status 3 */
 127#define CS43130_INT_STATUS_4    0x0F0003        /* Interrupt Status 4 */
 128#define CS43130_INT_STATUS_5    0x0F0004        /* Interrupt Status 5 */
 129#define CS43130_INT_MASK_1      0x0F0010        /* Interrupt Mask 1 */
 130#define CS43130_INT_MASK_2      0x0F0011        /* Interrupt Mask 2 */
 131#define CS43130_INT_MASK_3      0x0F0012        /* Interrupt Mask 3 */
 132#define CS43130_INT_MASK_4      0x0F0013        /* Interrupt Mask 4 */
 133#define CS43130_INT_MASK_5      0x0F0014        /* Interrupt Mask 5 */
 134
 135#define CS43130_MCLK_SRC_SEL_MASK       0x03
 136#define CS43130_MCLK_SRC_SEL_SHIFT      0
 137#define CS43130_MCLK_INT_MASK           0x04
 138#define CS43130_MCLK_INT_SHIFT          2
 139#define CS43130_CH_BITSIZE_MASK         0x03
 140#define CS43130_CH_EN_MASK              0x04
 141#define CS43130_CH_EN_SHIFT             2
 142#define CS43130_ASP_BITSIZE_MASK        0x03
 143#define CS43130_XSP_BITSIZE_MASK        0x0C
 144#define CS43130_XSP_BITSIZE_SHIFT       2
 145#define CS43130_SP_BITSIZE_ASP_SHIFT    0
 146#define CS43130_HP_DETECT_CTRL_SHIFT    6
 147#define CS43130_HP_DETECT_CTRL_MASK     (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
 148#define CS43130_HP_DETECT_INV_SHIFT     5
 149#define CS43130_HP_DETECT_INV_MASK      (1 << CS43130_HP_DETECT_INV_SHIFT)
 150
 151/* CS43130_INT_MASK_1 */
 152#define CS43130_HP_PLUG_INT_SHIFT       6
 153#define CS43130_HP_PLUG_INT             (1 << CS43130_HP_PLUG_INT_SHIFT)
 154#define CS43130_HP_UNPLUG_INT_SHIFT     5
 155#define CS43130_HP_UNPLUG_INT           (1 << CS43130_HP_UNPLUG_INT_SHIFT)
 156#define CS43130_XTAL_RDY_INT_SHIFT      4
 157#define CS43130_XTAL_RDY_INT_MASK       0x10
 158#define CS43130_XTAL_RDY_INT            (1 << CS43130_XTAL_RDY_INT_SHIFT)
 159#define CS43130_XTAL_ERR_INT_SHIFT      3
 160#define CS43130_XTAL_ERR_INT            (1 << CS43130_XTAL_ERR_INT_SHIFT)
 161#define CS43130_PLL_RDY_INT_MASK        0x04
 162#define CS43130_PLL_RDY_INT_SHIFT       2
 163#define CS43130_PLL_RDY_INT             (1 << CS43130_PLL_RDY_INT_SHIFT)
 164
 165/* CS43130_INT_MASK_4 */
 166#define CS43130_INT_MASK_ALL            0xFF
 167#define CS43130_HPLOAD_NO_DC_INT_SHIFT  7
 168#define CS43130_HPLOAD_NO_DC_INT        (1 << CS43130_HPLOAD_NO_DC_INT_SHIFT)
 169#define CS43130_HPLOAD_UNPLUG_INT_SHIFT 6
 170#define CS43130_HPLOAD_UNPLUG_INT       (1 << CS43130_HPLOAD_UNPLUG_INT_SHIFT)
 171#define CS43130_HPLOAD_OOR_INT_SHIFT    4
 172#define CS43130_HPLOAD_OOR_INT          (1 << CS43130_HPLOAD_OOR_INT_SHIFT)
 173#define CS43130_HPLOAD_AC_INT_SHIFT     3
 174#define CS43130_HPLOAD_AC_INT           (1 << CS43130_HPLOAD_AC_INT_SHIFT)
 175#define CS43130_HPLOAD_DC_INT_SHIFT     2
 176#define CS43130_HPLOAD_DC_INT           (1 << CS43130_HPLOAD_DC_INT_SHIFT)
 177#define CS43130_HPLOAD_OFF_INT_SHIFT    1
 178#define CS43130_HPLOAD_OFF_INT          (1 << CS43130_HPLOAD_OFF_INT_SHIFT)
 179#define CS43130_HPLOAD_ON_INT           1
 180
 181/* CS43130_HP_LOAD_1 */
 182#define CS43130_HPLOAD_EN_SHIFT         7
 183#define CS43130_HPLOAD_EN               (1 << CS43130_HPLOAD_EN_SHIFT)
 184#define CS43130_HPLOAD_CHN_SEL_SHIFT    4
 185#define CS43130_HPLOAD_CHN_SEL          (1 << CS43130_HPLOAD_CHN_SEL_SHIFT)
 186#define CS43130_HPLOAD_AC_START_SHIFT   1
 187#define CS43130_HPLOAD_AC_START         (1 << CS43130_HPLOAD_AC_START_SHIFT)
 188#define CS43130_HPLOAD_DC_START         1
 189
 190/* Reg CS43130_SP_BITSIZE */
 191#define CS43130_SP_BIT_SIZE_8   0x03
 192#define CS43130_SP_BIT_SIZE_16  0x02
 193#define CS43130_SP_BIT_SIZE_24  0x01
 194#define CS43130_SP_BIT_SIZE_32  0x00
 195
 196/* Reg CS43130_SP_CH_SZ_EN */
 197#define CS43130_CH_BIT_SIZE_8   0x00
 198#define CS43130_CH_BIT_SIZE_16  0x01
 199#define CS43130_CH_BIT_SIZE_24  0x02
 200#define CS43130_CH_BIT_SIZE_32  0x03
 201
 202/* PLL */
 203#define CS43130_PLL_START_MASK  0x01
 204#define CS43130_PLL_MODE_MASK   0x02
 205#define CS43130_PLL_MODE_SHIFT  1
 206
 207#define CS43130_PLL_REF_PREDIV_MASK     0x3
 208
 209#define CS43130_SP_STP_MASK     0x10
 210#define CS43130_SP_STP_SHIFT    4
 211#define CS43130_SP_5050_MASK    0x08
 212#define CS43130_SP_5050_SHIFT   3
 213#define CS43130_SP_FSD_MASK     0x07
 214
 215#define CS43130_SP_MODE_MASK    0x10
 216#define CS43130_SP_MODE_SHIFT   4
 217#define CS43130_SP_SCPOL_OUT_MASK       0x08
 218#define CS43130_SP_SCPOL_OUT_SHIFT      3
 219#define CS43130_SP_SCPOL_IN_MASK        0x04
 220#define CS43130_SP_SCPOL_IN_SHIFT       2
 221#define CS43130_SP_LCPOL_OUT_MASK       0x02
 222#define CS43130_SP_LCPOL_OUT_SHIFT      1
 223#define CS43130_SP_LCPOL_IN_MASK        0x01
 224#define CS43130_SP_LCPOL_IN_SHIFT       0
 225
 226/* Reg CS43130_PWDN_CTL */
 227#define CS43130_PDN_XSP_MASK    0x80
 228#define CS43130_PDN_XSP_SHIFT   7
 229#define CS43130_PDN_ASP_MASK    0x40
 230#define CS43130_PDN_ASP_SHIFT   6
 231#define CS43130_PDN_DSPIF_MASK  0x20
 232#define CS43130_PDN_DSDIF_SHIFT 5
 233#define CS43130_PDN_HP_MASK     0x10
 234#define CS43130_PDN_HP_SHIFT    4
 235#define CS43130_PDN_XTAL_MASK   0x08
 236#define CS43130_PDN_XTAL_SHIFT  3
 237#define CS43130_PDN_PLL_MASK    0x04
 238#define CS43130_PDN_PLL_SHIFT   2
 239#define CS43130_PDN_CLKOUT_MASK 0x02
 240#define CS43130_PDN_CLKOUT_SHIFT        1
 241
 242/* Reg CS43130_HP_OUT_CTL_1 */
 243#define CS43130_HP_IN_EN_SHIFT          3
 244#define CS43130_HP_IN_EN_MASK           0x08
 245
 246/* Reg CS43130_PAD_INT_CFG */
 247#define CS43130_ASP_3ST_MASK            0x01
 248#define CS43130_XSP_3ST_MASK            0x02
 249
 250/* Reg CS43130_PLL_SET_2 */
 251#define CS43130_PLL_DIV_DATA_MASK       0x000000FF
 252#define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT       0
 253
 254/* Reg CS43130_PLL_SET_3 */
 255#define CS43130_PLL_DIV_FRAC_1_DATA_SHIFT       8
 256
 257/* Reg CS43130_PLL_SET_4 */
 258#define CS43130_PLL_DIV_FRAC_2_DATA_SHIFT       16
 259
 260/* Reg CS43130_SP_DEN_1 */
 261#define CS43130_SP_M_LSB_DATA_MASK      0x00FF
 262#define CS43130_SP_M_LSB_DATA_SHIFT     0
 263
 264/* Reg CS43130_SP_DEN_2 */
 265#define CS43130_SP_M_MSB_DATA_MASK      0xFF00
 266#define CS43130_SP_M_MSB_DATA_SHIFT     8
 267
 268/* Reg CS43130_SP_NUM_1 */
 269#define CS43130_SP_N_LSB_DATA_MASK      0x00FF
 270#define CS43130_SP_N_LSB_DATA_SHIFT     0
 271
 272/* Reg CS43130_SP_NUM_2 */
 273#define CS43130_SP_N_MSB_DATA_MASK      0xFF00
 274#define CS43130_SP_N_MSB_DATA_SHIFT     8
 275
 276/* Reg CS43130_SP_LRCK_HI_TIME_1 */
 277#define CS43130_SP_LCHI_DATA_MASK       0x00FF
 278#define CS43130_SP_LCHI_LSB_DATA_SHIFT  0
 279
 280/* Reg CS43130_SP_LRCK_HI_TIME_2 */
 281#define CS43130_SP_LCHI_MSB_DATA_SHIFT  8
 282
 283/* Reg CS43130_SP_LRCK_PERIOD_1 */
 284#define CS43130_SP_LCPR_DATA_MASK       0x00FF
 285#define CS43130_SP_LCPR_LSB_DATA_SHIFT  0
 286
 287/* Reg CS43130_SP_LRCK_PERIOD_2 */
 288#define CS43130_SP_LCPR_MSB_DATA_SHIFT  8
 289
 290#define CS43130_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8  | \
 291                        SNDRV_PCM_FMTBIT_S16_LE | \
 292                        SNDRV_PCM_FMTBIT_S24_LE | \
 293                        SNDRV_PCM_FMTBIT_S32_LE)
 294
 295#define CS43130_DOP_FORMATS (SNDRV_PCM_FMTBIT_DSD_U16_LE | \
 296                             SNDRV_PCM_FMTBIT_DSD_U16_BE | \
 297                             SNDRV_PCM_FMTBIT_S24_LE)
 298
 299/* Reg CS43130_CRYSTAL_SET */
 300#define CS43130_XTAL_IBIAS_MASK         0x07
 301
 302/* Reg CS43130_PATH_CTL_1 */
 303#define CS43130_MUTE_MASK               0x03
 304#define CS43130_MUTE_EN                 0x03
 305
 306/* Reg CS43130_DSD_INT_CFG */
 307#define CS43130_DSD_MASTER              0x04
 308
 309/* Reg CS43130_DSD_PATH_CTL_2 */
 310#define CS43130_DSD_SRC_MASK            0x60
 311#define CS43130_DSD_SRC_SHIFT           5
 312#define CS43130_DSD_EN_SHIFT            4
 313#define CS43130_DSD_SPEED_MASK          0x04
 314#define CS43130_DSD_SPEED_SHIFT         2
 315
 316/* Reg CS43130_DSD_PCM_MIX_CTL  */
 317#define CS43130_MIX_PCM_PREP_SHIFT      1
 318#define CS43130_MIX_PCM_PREP_MASK       0x02
 319
 320#define CS43130_MIX_PCM_DSD_SHIFT       0
 321#define CS43130_MIX_PCM_DSD_MASK        0x01
 322
 323/* Reg CS43130_HP_MEAS_LOAD */
 324#define CS43130_HP_MEAS_LOAD_MASK       0x000000FF
 325#define CS43130_HP_MEAS_LOAD_1_SHIFT    0
 326#define CS43130_HP_MEAS_LOAD_2_SHIFT    8
 327
 328#define CS43130_MCLK_22M                22579200
 329#define CS43130_MCLK_24M                24576000
 330
 331#define CS43130_LINEOUT_LOAD            5000
 332#define CS43130_JACK_LINEOUT            (SND_JACK_MECHANICAL | SND_JACK_LINEOUT)
 333#define CS43130_JACK_HEADPHONE          (SND_JACK_MECHANICAL | \
 334                                         SND_JACK_HEADPHONE)
 335#define CS43130_JACK_MASK               (SND_JACK_MECHANICAL | \
 336                                         SND_JACK_LINEOUT | \
 337                                         SND_JACK_HEADPHONE)
 338
 339enum cs43130_dsd_src {
 340        CS43130_DSD_SRC_DSD = 0,
 341        CS43130_DSD_SRC_ASP = 2,
 342        CS43130_DSD_SRC_XSP = 3,
 343};
 344
 345enum cs43130_asp_rate {
 346        CS43130_ASP_SPRATE_32K = 0,
 347        CS43130_ASP_SPRATE_44_1K,
 348        CS43130_ASP_SPRATE_48K,
 349        CS43130_ASP_SPRATE_88_2K,
 350        CS43130_ASP_SPRATE_96K,
 351        CS43130_ASP_SPRATE_176_4K,
 352        CS43130_ASP_SPRATE_192K,
 353        CS43130_ASP_SPRATE_352_8K,
 354        CS43130_ASP_SPRATE_384K,
 355};
 356
 357enum cs43130_mclk_src_sel {
 358        CS43130_MCLK_SRC_EXT = 0,
 359        CS43130_MCLK_SRC_PLL,
 360        CS43130_MCLK_SRC_RCO
 361};
 362
 363enum cs43130_mclk_int_freq {
 364        CS43130_MCLK_24P5 = 0,
 365        CS43130_MCLK_22P5,
 366};
 367
 368enum cs43130_xtal_ibias {
 369        CS43130_XTAL_UNUSED = -1,
 370        CS43130_XTAL_IBIAS_15UA = 2,
 371        CS43130_XTAL_IBIAS_12_5UA = 4,
 372        CS43130_XTAL_IBIAS_7_5UA = 6,
 373};
 374
 375enum cs43130_dai_id {
 376        CS43130_ASP_PCM_DAI = 0,
 377        CS43130_ASP_DOP_DAI,
 378        CS43130_XSP_DOP_DAI,
 379        CS43130_XSP_DSD_DAI,
 380        CS43130_DAI_ID_MAX,
 381};
 382
 383struct cs43130_clk_gen {
 384        unsigned int    mclk_int;
 385        int             fs;
 386        u16             den;
 387        u16             num;
 388};
 389
 390/* frm_size = 16 */
 391static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {
 392        {22579200,      32000,          441,            10,},
 393        {22579200,      44100,          32,             1,},
 394        {22579200,      48000,          147,            5,},
 395        {22579200,      88200,          16,             1,},
 396        {22579200,      96000,          147,            10,},
 397        {22579200,      176400,         8,              1,},
 398        {22579200,      192000,         147,            20,},
 399        {22579200,      352800,         4,              1,},
 400        {22579200,      384000,         147,            40,},
 401        {24576000,      32000,          48,             1,},
 402        {24576000,      44100,          5120,           147,},
 403        {24576000,      48000,          32,             1,},
 404        {24576000,      88200,          2560,           147,},
 405        {24576000,      96000,          16,             1,},
 406        {24576000,      176400,         1280,           147,},
 407        {24576000,      192000,         8,              1,},
 408        {24576000,      352800,         640,            147,},
 409        {24576000,      384000,         4,              1,},
 410};
 411
 412/* frm_size = 32 */
 413static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {
 414        {22579200,      32000,          441,            20,},
 415        {22579200,      44100,          16,             1,},
 416        {22579200,      48000,          147,            10,},
 417        {22579200,      88200,          8,              1,},
 418        {22579200,      96000,          147,            20,},
 419        {22579200,      176400,         4,              1,},
 420        {22579200,      192000,         147,            40,},
 421        {22579200,      352800,         2,              1,},
 422        {22579200,      384000,         147,            80,},
 423        {24576000,      32000,          24,             1,},
 424        {24576000,      44100,          2560,           147,},
 425        {24576000,      48000,          16,             1,},
 426        {24576000,      88200,          1280,           147,},
 427        {24576000,      96000,          8,              1,},
 428        {24576000,      176400,         640,            147,},
 429        {24576000,      192000,         4,              1,},
 430        {24576000,      352800,         320,            147,},
 431        {24576000,      384000,         2,              1,},
 432};
 433
 434/* frm_size = 48 */
 435static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {
 436        {22579200,      32000,          147,            100,},
 437        {22579200,      44100,          32,             3,},
 438        {22579200,      48000,          49,             5,},
 439        {22579200,      88200,          16,             3,},
 440        {22579200,      96000,          49,             10,},
 441        {22579200,      176400,         8,              3,},
 442        {22579200,      192000,         49,             20,},
 443        {22579200,      352800,         4,              3,},
 444        {22579200,      384000,         49,             40,},
 445        {24576000,      32000,          16,             1,},
 446        {24576000,      44100,          5120,           441,},
 447        {24576000,      48000,          32,             3,},
 448        {24576000,      88200,          2560,           441,},
 449        {24576000,      96000,          16,             3,},
 450        {24576000,      176400,         1280,           441,},
 451        {24576000,      192000,         8,              3,},
 452        {24576000,      352800,         640,            441,},
 453        {24576000,      384000,         4,              3,},
 454};
 455
 456/* frm_size = 64 */
 457static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {
 458        {22579200,      32000,          441,            40,},
 459        {22579200,      44100,          8,              1,},
 460        {22579200,      48000,          147,            20,},
 461        {22579200,      88200,          4,              1,},
 462        {22579200,      96000,          147,            40,},
 463        {22579200,      176400,         2,              1,},
 464        {22579200,      192000,         147,            80,},
 465        {22579200,      352800,         1,              1,},
 466        {24576000,      32000,          12,             1,},
 467        {24576000,      44100,          1280,           147,},
 468        {24576000,      48000,          8,              1,},
 469        {24576000,      88200,          640,            147,},
 470        {24576000,      96000,          4,              1,},
 471        {24576000,      176400,         320,            147,},
 472        {24576000,      192000,         2,              1,},
 473        {24576000,      352800,         160,            147,},
 474        {24576000,      384000,         1,              1,},
 475};
 476
 477struct cs43130_bitwidth_map {
 478        unsigned int bitwidth;
 479        u8 sp_bit;
 480        u8 ch_bit;
 481};
 482
 483struct cs43130_rate_map {
 484        int fs;
 485        int val;
 486};
 487
 488#define HP_LEFT                 0
 489#define HP_RIGHT                1
 490#define CS43130_AC_FREQ         10
 491#define CS43130_DC_THRESHOLD    2
 492
 493#define CS43130_NUM_SUPPLIES    5
 494static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
 495        "VA",
 496        "VP",
 497        "VCP",
 498        "VD",
 499        "VL",
 500};
 501
 502#define CS43130_NUM_INT         5       /* number of interrupt status reg */
 503
 504struct cs43130_dai {
 505        unsigned int                    sclk;
 506        unsigned int                    dai_format;
 507        unsigned int                    dai_mode;
 508};
 509
 510struct  cs43130_private {
 511        struct snd_soc_component        *component;
 512        struct regmap                   *regmap;
 513        struct regulator_bulk_data      supplies[CS43130_NUM_SUPPLIES];
 514        struct gpio_desc                *reset_gpio;
 515        unsigned int                    dev_id; /* codec device ID */
 516        int                             xtal_ibias;
 517
 518        /* shared by both DAIs */
 519        struct mutex                    clk_mutex;
 520        int                             clk_req;
 521        bool                            pll_bypass;
 522        struct completion               xtal_rdy;
 523        struct completion               pll_rdy;
 524        unsigned int                    mclk;
 525        unsigned int                    mclk_int;
 526        int                             mclk_int_src;
 527
 528        /* DAI specific */
 529        struct cs43130_dai              dais[CS43130_DAI_ID_MAX];
 530
 531        /* HP load specific */
 532        bool                            dc_meas;
 533        bool                            ac_meas;
 534        bool                            hpload_done;
 535        struct completion               hpload_evt;
 536        unsigned int                    hpload_stat;
 537        u16                             hpload_dc[2];
 538        u16                             dc_threshold[CS43130_DC_THRESHOLD];
 539        u16                             ac_freq[CS43130_AC_FREQ];
 540        u16                             hpload_ac[CS43130_AC_FREQ][2];
 541        struct workqueue_struct         *wq;
 542        struct work_struct              work;
 543        struct snd_soc_jack             jack;
 544};
 545
 546#endif  /* __CS43130_H__ */
 547