1
2
3
4
5
6
7
8
9
10
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30
31#include "rl6231.h"
32#include "rt5651.h"
33
34#define RT5651_DEVICE_ID_VALUE 0x6281
35
36#define RT5651_PR_RANGE_BASE (0xff + 1)
37#define RT5651_PR_SPACING 0x100
38
39#define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
40
41static const struct regmap_range_cfg rt5651_ranges[] = {
42 { .name = "PR", .range_min = RT5651_PR_BASE,
43 .range_max = RT5651_PR_BASE + 0xb4,
44 .selector_reg = RT5651_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5651_PRIV_DATA,
48 .window_len = 0x1, },
49};
50
51static const struct reg_sequence init_list[] = {
52 {RT5651_PR_BASE + 0x3d, 0x3e00},
53};
54
55static const struct reg_default rt5651_reg[] = {
56 { 0x00, 0x0000 },
57 { 0x02, 0xc8c8 },
58 { 0x03, 0xc8c8 },
59 { 0x05, 0x0000 },
60 { 0x0d, 0x0000 },
61 { 0x0e, 0x0000 },
62 { 0x0f, 0x0808 },
63 { 0x10, 0x0808 },
64 { 0x19, 0xafaf },
65 { 0x1a, 0xafaf },
66 { 0x1b, 0x0c00 },
67 { 0x1c, 0x2f2f },
68 { 0x1d, 0x2f2f },
69 { 0x1e, 0x0000 },
70 { 0x27, 0x7860 },
71 { 0x28, 0x7070 },
72 { 0x29, 0x8080 },
73 { 0x2a, 0x5252 },
74 { 0x2b, 0x5454 },
75 { 0x2f, 0x0000 },
76 { 0x30, 0x5000 },
77 { 0x3b, 0x0000 },
78 { 0x3c, 0x006f },
79 { 0x3d, 0x0000 },
80 { 0x3e, 0x006f },
81 { 0x45, 0x6000 },
82 { 0x4d, 0x0000 },
83 { 0x4e, 0x0000 },
84 { 0x4f, 0x0279 },
85 { 0x50, 0x0000 },
86 { 0x51, 0x0000 },
87 { 0x52, 0x0279 },
88 { 0x53, 0xf000 },
89 { 0x61, 0x0000 },
90 { 0x62, 0x0000 },
91 { 0x63, 0x00c0 },
92 { 0x64, 0x0000 },
93 { 0x65, 0x0000 },
94 { 0x66, 0x0000 },
95 { 0x70, 0x8000 },
96 { 0x71, 0x8000 },
97 { 0x73, 0x1104 },
98 { 0x74, 0x0c00 },
99 { 0x75, 0x1400 },
100 { 0x77, 0x0c00 },
101 { 0x78, 0x4000 },
102 { 0x79, 0x0123 },
103 { 0x80, 0x0000 },
104 { 0x81, 0x0000 },
105 { 0x82, 0x0000 },
106 { 0x83, 0x0800 },
107 { 0x84, 0x0000 },
108 { 0x85, 0x0008 },
109 { 0x89, 0x0000 },
110 { 0x8e, 0x0004 },
111 { 0x8f, 0x1100 },
112 { 0x90, 0x0000 },
113 { 0x93, 0x2000 },
114 { 0x94, 0x0200 },
115 { 0xb0, 0x2080 },
116 { 0xb1, 0x0000 },
117 { 0xb4, 0x2206 },
118 { 0xb5, 0x1f00 },
119 { 0xb6, 0x0000 },
120 { 0xbb, 0x0000 },
121 { 0xbc, 0x0000 },
122 { 0xbd, 0x0000 },
123 { 0xbe, 0x0000 },
124 { 0xbf, 0x0000 },
125 { 0xc0, 0x0400 },
126 { 0xc1, 0x0000 },
127 { 0xc2, 0x0000 },
128 { 0xcf, 0x0013 },
129 { 0xd0, 0x0680 },
130 { 0xd1, 0x1c17 },
131 { 0xd3, 0xb320 },
132 { 0xd9, 0x0809 },
133 { 0xfa, 0x0010 },
134 { 0xfe, 0x10ec },
135 { 0xff, 0x6281 },
136};
137
138static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
139{
140 int i;
141
142 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
143 if ((reg >= rt5651_ranges[i].window_start &&
144 reg <= rt5651_ranges[i].window_start +
145 rt5651_ranges[i].window_len) ||
146 (reg >= rt5651_ranges[i].range_min &&
147 reg <= rt5651_ranges[i].range_max)) {
148 return true;
149 }
150 }
151
152 switch (reg) {
153 case RT5651_RESET:
154 case RT5651_PRIV_DATA:
155 case RT5651_EQ_CTRL1:
156 case RT5651_ALC_1:
157 case RT5651_IRQ_CTRL2:
158 case RT5651_INT_IRQ_ST:
159 case RT5651_PGM_REG_ARR1:
160 case RT5651_PGM_REG_ARR3:
161 case RT5651_VENDOR_ID:
162 case RT5651_DEVICE_ID:
163 return true;
164 default:
165 return false;
166 }
167}
168
169static bool rt5651_readable_register(struct device *dev, unsigned int reg)
170{
171 int i;
172
173 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
174 if ((reg >= rt5651_ranges[i].window_start &&
175 reg <= rt5651_ranges[i].window_start +
176 rt5651_ranges[i].window_len) ||
177 (reg >= rt5651_ranges[i].range_min &&
178 reg <= rt5651_ranges[i].range_max)) {
179 return true;
180 }
181 }
182
183 switch (reg) {
184 case RT5651_RESET:
185 case RT5651_VERSION_ID:
186 case RT5651_VENDOR_ID:
187 case RT5651_DEVICE_ID:
188 case RT5651_HP_VOL:
189 case RT5651_LOUT_CTRL1:
190 case RT5651_LOUT_CTRL2:
191 case RT5651_IN1_IN2:
192 case RT5651_IN3:
193 case RT5651_INL1_INR1_VOL:
194 case RT5651_INL2_INR2_VOL:
195 case RT5651_DAC1_DIG_VOL:
196 case RT5651_DAC2_DIG_VOL:
197 case RT5651_DAC2_CTRL:
198 case RT5651_ADC_DIG_VOL:
199 case RT5651_ADC_DATA:
200 case RT5651_ADC_BST_VOL:
201 case RT5651_STO1_ADC_MIXER:
202 case RT5651_STO2_ADC_MIXER:
203 case RT5651_AD_DA_MIXER:
204 case RT5651_STO_DAC_MIXER:
205 case RT5651_DD_MIXER:
206 case RT5651_DIG_INF_DATA:
207 case RT5651_PDM_CTL:
208 case RT5651_REC_L1_MIXER:
209 case RT5651_REC_L2_MIXER:
210 case RT5651_REC_R1_MIXER:
211 case RT5651_REC_R2_MIXER:
212 case RT5651_HPO_MIXER:
213 case RT5651_OUT_L1_MIXER:
214 case RT5651_OUT_L2_MIXER:
215 case RT5651_OUT_L3_MIXER:
216 case RT5651_OUT_R1_MIXER:
217 case RT5651_OUT_R2_MIXER:
218 case RT5651_OUT_R3_MIXER:
219 case RT5651_LOUT_MIXER:
220 case RT5651_PWR_DIG1:
221 case RT5651_PWR_DIG2:
222 case RT5651_PWR_ANLG1:
223 case RT5651_PWR_ANLG2:
224 case RT5651_PWR_MIXER:
225 case RT5651_PWR_VOL:
226 case RT5651_PRIV_INDEX:
227 case RT5651_PRIV_DATA:
228 case RT5651_I2S1_SDP:
229 case RT5651_I2S2_SDP:
230 case RT5651_ADDA_CLK1:
231 case RT5651_ADDA_CLK2:
232 case RT5651_DMIC:
233 case RT5651_TDM_CTL_1:
234 case RT5651_TDM_CTL_2:
235 case RT5651_TDM_CTL_3:
236 case RT5651_GLB_CLK:
237 case RT5651_PLL_CTRL1:
238 case RT5651_PLL_CTRL2:
239 case RT5651_PLL_MODE_1:
240 case RT5651_PLL_MODE_2:
241 case RT5651_PLL_MODE_3:
242 case RT5651_PLL_MODE_4:
243 case RT5651_PLL_MODE_5:
244 case RT5651_PLL_MODE_6:
245 case RT5651_PLL_MODE_7:
246 case RT5651_DEPOP_M1:
247 case RT5651_DEPOP_M2:
248 case RT5651_DEPOP_M3:
249 case RT5651_CHARGE_PUMP:
250 case RT5651_MICBIAS:
251 case RT5651_A_JD_CTL1:
252 case RT5651_EQ_CTRL1:
253 case RT5651_EQ_CTRL2:
254 case RT5651_ALC_1:
255 case RT5651_ALC_2:
256 case RT5651_ALC_3:
257 case RT5651_JD_CTRL1:
258 case RT5651_JD_CTRL2:
259 case RT5651_IRQ_CTRL1:
260 case RT5651_IRQ_CTRL2:
261 case RT5651_INT_IRQ_ST:
262 case RT5651_GPIO_CTRL1:
263 case RT5651_GPIO_CTRL2:
264 case RT5651_GPIO_CTRL3:
265 case RT5651_PGM_REG_ARR1:
266 case RT5651_PGM_REG_ARR2:
267 case RT5651_PGM_REG_ARR3:
268 case RT5651_PGM_REG_ARR4:
269 case RT5651_PGM_REG_ARR5:
270 case RT5651_SCB_FUNC:
271 case RT5651_SCB_CTRL:
272 case RT5651_BASE_BACK:
273 case RT5651_MP3_PLUS1:
274 case RT5651_MP3_PLUS2:
275 case RT5651_ADJ_HPF_CTRL1:
276 case RT5651_ADJ_HPF_CTRL2:
277 case RT5651_HP_CALIB_AMP_DET:
278 case RT5651_HP_CALIB2:
279 case RT5651_SV_ZCD1:
280 case RT5651_SV_ZCD2:
281 case RT5651_D_MISC:
282 case RT5651_DUMMY2:
283 case RT5651_DUMMY3:
284 return true;
285 default:
286 return false;
287 }
288}
289
290static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
291static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
292static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
293static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
294static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
295
296
297static const DECLARE_TLV_DB_RANGE(bst_tlv,
298 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
299 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
300 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
301 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
302 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
303 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
304 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
305);
306
307
308static const char * const rt5651_data_select[] = {
309 "Normal", "Swap", "left copy to right", "right copy to left"};
310
311static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
312 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
313
314static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
315 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
316
317static const struct snd_kcontrol_new rt5651_snd_controls[] = {
318
319 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
320 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
321
322 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
323 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
324
325
326 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
327 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
328 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
329 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
330 175, 0, dac_vol_tlv),
331 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
332 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
333 175, 0, dac_vol_tlv),
334
335 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
336 RT5651_BST_SFT1, 8, 0, bst_tlv),
337 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
338 RT5651_BST_SFT2, 8, 0, bst_tlv),
339
340 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
341 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
342 31, 1, in_vol_tlv),
343
344 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
345 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
346 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
347 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
348 127, 0, adc_vol_tlv),
349 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
350 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
351 127, 0, adc_vol_tlv),
352
353 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
354 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
355 3, 0, adc_bst_tlv),
356
357
358 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
359 RT5651_STO1_T_SFT, 1, 0),
360 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
361 RT5651_STO2_T_SFT, 1, 0),
362 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
363 RT5651_DMIC_1_M_SFT, 1, 0),
364
365 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
366 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
367};
368
369
370
371
372
373
374
375
376
377static int set_dmic_clk(struct snd_soc_dapm_widget *w,
378 struct snd_kcontrol *kcontrol, int event)
379{
380 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
381 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
382 int idx, rate;
383
384 rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap,
385 RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT);
386 idx = rl6231_calc_dmic_clk(rate);
387 if (idx < 0)
388 dev_err(component->dev, "Failed to set DMIC clock\n");
389 else
390 snd_soc_component_update_bits(component, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
391 idx << RT5651_DMIC_CLK_SFT);
392
393 return idx;
394}
395
396
397static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
398 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
399 RT5651_M_STO1_ADC_L1_SFT, 1, 1),
400 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
401 RT5651_M_STO1_ADC_L2_SFT, 1, 1),
402};
403
404static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
405 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
406 RT5651_M_STO1_ADC_R1_SFT, 1, 1),
407 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
408 RT5651_M_STO1_ADC_R2_SFT, 1, 1),
409};
410
411static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
412 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
413 RT5651_M_STO2_ADC_L1_SFT, 1, 1),
414 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
415 RT5651_M_STO2_ADC_L2_SFT, 1, 1),
416};
417
418static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
419 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
420 RT5651_M_STO2_ADC_R1_SFT, 1, 1),
421 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
422 RT5651_M_STO2_ADC_R2_SFT, 1, 1),
423};
424
425static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
426 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
427 RT5651_M_ADCMIX_L_SFT, 1, 1),
428 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
429 RT5651_M_IF1_DAC_L_SFT, 1, 1),
430};
431
432static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
433 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
434 RT5651_M_ADCMIX_R_SFT, 1, 1),
435 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
436 RT5651_M_IF1_DAC_R_SFT, 1, 1),
437};
438
439static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
440 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
441 RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
442 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
443 RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
444 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
445 RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
446};
447
448static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
449 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
450 RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
451 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
452 RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
453 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
454 RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
455};
456
457static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
458 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
459 RT5651_M_STO_DD_L1_SFT, 1, 1),
460 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
461 RT5651_M_STO_DD_L2_SFT, 1, 1),
462 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
463 RT5651_M_STO_DD_R2_L_SFT, 1, 1),
464};
465
466static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
467 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
468 RT5651_M_STO_DD_R1_SFT, 1, 1),
469 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
470 RT5651_M_STO_DD_R2_SFT, 1, 1),
471 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
472 RT5651_M_STO_DD_L2_R_SFT, 1, 1),
473};
474
475
476static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
477 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
478 RT5651_M_IN1_L_RM_L_SFT, 1, 1),
479 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
480 RT5651_M_BST3_RM_L_SFT, 1, 1),
481 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
482 RT5651_M_BST2_RM_L_SFT, 1, 1),
483 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
484 RT5651_M_BST1_RM_L_SFT, 1, 1),
485};
486
487static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
488 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
489 RT5651_M_IN1_R_RM_R_SFT, 1, 1),
490 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
491 RT5651_M_BST3_RM_R_SFT, 1, 1),
492 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
493 RT5651_M_BST2_RM_R_SFT, 1, 1),
494 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
495 RT5651_M_BST1_RM_R_SFT, 1, 1),
496};
497
498
499
500static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
501 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
502 RT5651_M_BST1_OM_L_SFT, 1, 1),
503 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
504 RT5651_M_BST2_OM_L_SFT, 1, 1),
505 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
506 RT5651_M_IN1_L_OM_L_SFT, 1, 1),
507 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
508 RT5651_M_RM_L_OM_L_SFT, 1, 1),
509 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
510 RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
511};
512
513static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
514 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
515 RT5651_M_BST2_OM_R_SFT, 1, 1),
516 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
517 RT5651_M_BST1_OM_R_SFT, 1, 1),
518 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
519 RT5651_M_IN1_R_OM_R_SFT, 1, 1),
520 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
521 RT5651_M_RM_R_OM_R_SFT, 1, 1),
522 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
523 RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
524};
525
526static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
527 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
528 RT5651_M_DAC1_HM_SFT, 1, 1),
529 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
530 RT5651_M_HPVOL_HM_SFT, 1, 1),
531};
532
533static const struct snd_kcontrol_new rt5651_lout_mix[] = {
534 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
535 RT5651_M_DAC_L1_LM_SFT, 1, 1),
536 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
537 RT5651_M_DAC_R1_LM_SFT, 1, 1),
538 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
539 RT5651_M_OV_L_LM_SFT, 1, 1),
540 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
541 RT5651_M_OV_R_LM_SFT, 1, 1),
542};
543
544static const struct snd_kcontrol_new outvol_l_control =
545 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
546 RT5651_VOL_L_SFT, 1, 1);
547
548static const struct snd_kcontrol_new outvol_r_control =
549 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
550 RT5651_VOL_R_SFT, 1, 1);
551
552static const struct snd_kcontrol_new lout_l_mute_control =
553 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
554 RT5651_L_MUTE_SFT, 1, 1);
555
556static const struct snd_kcontrol_new lout_r_mute_control =
557 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
558 RT5651_R_MUTE_SFT, 1, 1);
559
560static const struct snd_kcontrol_new hpovol_l_control =
561 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
562 RT5651_VOL_L_SFT, 1, 1);
563
564static const struct snd_kcontrol_new hpovol_r_control =
565 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
566 RT5651_VOL_R_SFT, 1, 1);
567
568static const struct snd_kcontrol_new hpo_l_mute_control =
569 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
570 RT5651_L_MUTE_SFT, 1, 1);
571
572static const struct snd_kcontrol_new hpo_r_mute_control =
573 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
574 RT5651_R_MUTE_SFT, 1, 1);
575
576
577static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
578
579static SOC_ENUM_SINGLE_DECL(
580 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
581 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
582
583static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
584 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
585
586static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
587 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
588
589static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
590
591static SOC_ENUM_SINGLE_DECL(
592 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
593 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
594
595static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
596 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
597
598static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
599 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
600
601
602static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
603
604static SOC_ENUM_SINGLE_DECL(
605 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
606 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
607
608static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
609 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
610
611static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
612
613static SOC_ENUM_SINGLE_DECL(
614 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
615 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
616
617static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
618 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
619
620static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
621
622static SOC_ENUM_SINGLE_DECL(
623 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
624 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
625
626static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
627 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
628
629static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
630
631static SOC_ENUM_SINGLE_DECL(
632 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
633 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
634
635static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
636 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
637
638
639
640static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
641
642static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
643 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
644
645static const struct snd_kcontrol_new rt5651_dac_l2_mux =
646 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
647
648static SOC_ENUM_SINGLE_DECL(
649 rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
650 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
651
652static const struct snd_kcontrol_new rt5651_dac_r2_mux =
653 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
654
655
656
657static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
658
659static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
660 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
661
662static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
663 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
664
665
666static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
667
668static SOC_ENUM_SINGLE_DECL(
669 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
670 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
671
672static SOC_ENUM_SINGLE_DECL(
673 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
674 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
675
676static const struct snd_kcontrol_new rt5651_pdm_l_mux =
677 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
678
679static const struct snd_kcontrol_new rt5651_pdm_r_mux =
680 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
681
682static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
683 struct snd_kcontrol *kcontrol, int event)
684{
685 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
686 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
687
688 switch (event) {
689 case SND_SOC_DAPM_POST_PMU:
690
691 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
692 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
693 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
694 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
695 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
696 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
697 RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
698 RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
699 regmap_write(rt5651->regmap, RT5651_PR_BASE +
700 RT5651_HP_DCC_INT1, 0x9f00);
701
702 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
703 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
704 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
705 RT5651_PWR_HA,
706 RT5651_PWR_HA);
707 usleep_range(10000, 15000);
708 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
709 RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
710 RT5651_PWR_FV1 | RT5651_PWR_FV2);
711 break;
712
713 default:
714 return 0;
715 }
716
717 return 0;
718}
719
720static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
721 struct snd_kcontrol *kcontrol, int event)
722{
723 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
724 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
725
726 switch (event) {
727 case SND_SOC_DAPM_POST_PMU:
728
729 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
730 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
731 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
732 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
733 RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
734
735 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
736 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
737 RT5651_CP_FQ3_MASK,
738 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
739 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
740 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
741
742 regmap_write(rt5651->regmap, RT5651_PR_BASE +
743 RT5651_MAMP_INT_REG2, 0x1c00);
744 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
745 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
746 RT5651_HP_CP_PD | RT5651_HP_SG_EN);
747 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
748 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
749 rt5651->hp_mute = 0;
750 break;
751
752 case SND_SOC_DAPM_PRE_PMD:
753 rt5651->hp_mute = 1;
754 usleep_range(70000, 75000);
755 break;
756
757 default:
758 return 0;
759 }
760
761 return 0;
762}
763
764static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
765 struct snd_kcontrol *kcontrol, int event)
766{
767
768 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
769 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
770
771 switch (event) {
772 case SND_SOC_DAPM_POST_PMU:
773 if (!rt5651->hp_mute)
774 usleep_range(80000, 85000);
775
776 break;
777
778 default:
779 return 0;
780 }
781
782 return 0;
783}
784
785static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
786 struct snd_kcontrol *kcontrol, int event)
787{
788 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
789
790 switch (event) {
791 case SND_SOC_DAPM_POST_PMU:
792 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
793 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
794 break;
795
796 case SND_SOC_DAPM_PRE_PMD:
797 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
798 RT5651_PWR_BST1_OP2, 0);
799 break;
800
801 default:
802 return 0;
803 }
804
805 return 0;
806}
807
808static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
809 struct snd_kcontrol *kcontrol, int event)
810{
811 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
812
813 switch (event) {
814 case SND_SOC_DAPM_POST_PMU:
815 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
816 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
817 break;
818
819 case SND_SOC_DAPM_PRE_PMD:
820 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
821 RT5651_PWR_BST2_OP2, 0);
822 break;
823
824 default:
825 return 0;
826 }
827
828 return 0;
829}
830
831static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
832 struct snd_kcontrol *kcontrol, int event)
833{
834 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
835
836 switch (event) {
837 case SND_SOC_DAPM_POST_PMU:
838 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
839 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
840 break;
841
842 case SND_SOC_DAPM_PRE_PMD:
843 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
844 RT5651_PWR_BST3_OP2, 0);
845 break;
846
847 default:
848 return 0;
849 }
850
851 return 0;
852}
853
854static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
855
856 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
857 15, 0, NULL, 0),
858 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
859 14, 0, NULL, 0),
860 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
861 13, 0, NULL, 0),
862 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
863 12, 0, NULL, 0),
864 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
865 11, 0, NULL, 0),
866
867
868 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
869 RT5651_PWR_LDO_BIT, 0, NULL, 0),
870 SND_SOC_DAPM_SUPPLY("micbias1", RT5651_PWR_ANLG2,
871 RT5651_PWR_MB1_BIT, 0, NULL, 0),
872
873 SND_SOC_DAPM_INPUT("MIC1"),
874 SND_SOC_DAPM_INPUT("MIC2"),
875 SND_SOC_DAPM_INPUT("MIC3"),
876
877 SND_SOC_DAPM_INPUT("IN1P"),
878 SND_SOC_DAPM_INPUT("IN2P"),
879 SND_SOC_DAPM_INPUT("IN2N"),
880 SND_SOC_DAPM_INPUT("IN3P"),
881 SND_SOC_DAPM_INPUT("DMIC L1"),
882 SND_SOC_DAPM_INPUT("DMIC R1"),
883 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
884 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
885
886 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
887 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
888 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
889 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
890 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
891 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
892 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
893 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
894 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
895
896 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
897 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
898 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
899 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
900 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
901 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
902 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
903 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
904
905
906 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
907 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
908 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
909 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
910
911 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
912 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
913 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
914 RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
915 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
916 RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
917
918 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
919 &rt5651_sto1_adc_l2_mux),
920 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
921 &rt5651_sto1_adc_r2_mux),
922 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
923 &rt5651_sto1_adc_l1_mux),
924 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
925 &rt5651_sto1_adc_r1_mux),
926 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
927 &rt5651_sto2_adc_l2_mux),
928 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
929 &rt5651_sto2_adc_l1_mux),
930 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
931 &rt5651_sto2_adc_r1_mux),
932 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
933 &rt5651_sto2_adc_r2_mux),
934
935 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
936 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
937 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
938 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
939 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
940 rt5651_sto1_adc_l_mix,
941 ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
942 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
943 rt5651_sto1_adc_r_mix,
944 ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
945 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
946 rt5651_sto2_adc_l_mix,
947 ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
948 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
949 rt5651_sto2_adc_r_mix,
950 ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
951
952
953 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
954 RT5651_PWR_I2S1_BIT, 0, NULL, 0),
955 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
956 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
957 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
958 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
959 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
960 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
961 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
962 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
963 RT5651_PWR_I2S2_BIT, 0, NULL, 0),
964 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
965 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
966 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
967 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
968 &rt5651_if2_adc_src_mux),
969
970
971
972 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
973 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
974 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
975 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
976
977 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
978 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
979 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
980 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
981
982
983 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
984
985
986
987 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
988 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
989 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
990 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
991
992
993 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
994 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
995 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
996 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
997
998 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
999 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1000 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1001 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1002
1003 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1004 rt5651_sto_dac_l_mix,
1005 ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1006 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1007 rt5651_sto_dac_r_mix,
1008 ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1009 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1010 rt5651_dd_dac_l_mix,
1011 ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1012 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1013 rt5651_dd_dac_r_mix,
1014 ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1015
1016
1017 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1018 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1019 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1020 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1021 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1022 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1023
1024 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1025 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1026 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1027 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1028
1029 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1030 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1031 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1032 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1033 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1034 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1035 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1036 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1037 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1038 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1039 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1040 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1041 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1042 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1043 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1044 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1045
1046 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1047 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1048 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1049 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1050 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1051 RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1052 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1053 RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1054 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1055 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1056
1057 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1058 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1059 SND_SOC_DAPM_POST_PMU),
1060 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1061 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1062 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1063 &hpo_l_mute_control),
1064 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1065 &hpo_r_mute_control),
1066 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1067 &lout_l_mute_control),
1068 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1069 &lout_r_mute_control),
1070 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1071
1072
1073 SND_SOC_DAPM_OUTPUT("HPOL"),
1074 SND_SOC_DAPM_OUTPUT("HPOR"),
1075 SND_SOC_DAPM_OUTPUT("LOUTL"),
1076 SND_SOC_DAPM_OUTPUT("LOUTR"),
1077 SND_SOC_DAPM_OUTPUT("PDML"),
1078 SND_SOC_DAPM_OUTPUT("PDMR"),
1079};
1080
1081static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1082 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1083 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1084 {"I2S1", NULL, "I2S1 ASRC"},
1085 {"I2S2", NULL, "I2S2 ASRC"},
1086
1087 {"IN1P", NULL, "LDO"},
1088 {"IN2P", NULL, "LDO"},
1089 {"IN3P", NULL, "LDO"},
1090
1091 {"IN1P", NULL, "MIC1"},
1092 {"IN2P", NULL, "MIC2"},
1093 {"IN2N", NULL, "MIC2"},
1094 {"IN3P", NULL, "MIC3"},
1095
1096 {"BST1", NULL, "IN1P"},
1097 {"BST2", NULL, "IN2P"},
1098 {"BST2", NULL, "IN2N"},
1099 {"BST3", NULL, "IN3P"},
1100
1101 {"INL1 VOL", NULL, "IN2P"},
1102 {"INR1 VOL", NULL, "IN2N"},
1103
1104 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
1105 {"RECMIXL", "BST3 Switch", "BST3"},
1106 {"RECMIXL", "BST2 Switch", "BST2"},
1107 {"RECMIXL", "BST1 Switch", "BST1"},
1108
1109 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
1110 {"RECMIXR", "BST3 Switch", "BST3"},
1111 {"RECMIXR", "BST2 Switch", "BST2"},
1112 {"RECMIXR", "BST1 Switch", "BST1"},
1113
1114 {"ADC L", NULL, "RECMIXL"},
1115 {"ADC L", NULL, "ADC L Power"},
1116 {"ADC R", NULL, "RECMIXR"},
1117 {"ADC R", NULL, "ADC R Power"},
1118
1119 {"DMIC L1", NULL, "DMIC CLK"},
1120 {"DMIC R1", NULL, "DMIC CLK"},
1121
1122 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1123 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1124 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1125 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1126
1127 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1128 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1129 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1130 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1131
1132 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1133 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1134 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1135 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1136
1137 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1138 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1139 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1140 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1141
1142 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1143 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1144 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
1145 {"Stereo1 Filter", NULL, "ADC ASRC"},
1146
1147 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1148 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1149 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1150
1151 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1152 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1153 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
1154 {"Stereo2 Filter", NULL, "ADC ASRC"},
1155
1156 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1157 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1158 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1159
1160 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1161 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1162 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1163 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1164
1165 {"IF1 ADC1", NULL, "I2S1"},
1166
1167 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1168 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1169 {"IF2 ADC", NULL, "I2S2"},
1170
1171 {"AIF1TX", NULL, "IF1 ADC1"},
1172 {"AIF1TX", NULL, "IF1 ADC2"},
1173 {"AIF2TX", NULL, "IF2 ADC"},
1174
1175 {"IF1 DAC", NULL, "AIF1RX"},
1176 {"IF1 DAC", NULL, "I2S1"},
1177 {"IF2 DAC", NULL, "AIF2RX"},
1178 {"IF2 DAC", NULL, "I2S2"},
1179
1180 {"IF1 DAC1 L", NULL, "IF1 DAC"},
1181 {"IF1 DAC1 R", NULL, "IF1 DAC"},
1182 {"IF1 DAC2 L", NULL, "IF1 DAC"},
1183 {"IF1 DAC2 R", NULL, "IF1 DAC"},
1184 {"IF2 DAC L", NULL, "IF2 DAC"},
1185 {"IF2 DAC R", NULL, "IF2 DAC"},
1186
1187 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1188 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1189 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1190 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1191
1192 {"Audio DSP", NULL, "DAC MIXL"},
1193 {"Audio DSP", NULL, "DAC MIXR"},
1194
1195 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1196 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1197 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1198
1199 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1200 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1201 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1202
1203 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1204 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1205 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1206 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1207 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1208 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1209 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1210 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1211 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1212 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1213
1214 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1215 {"PDM L Mux", "DD MIX", "DAC MIXL"},
1216 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1217 {"PDM R Mux", "DD MIX", "DAC MIXR"},
1218
1219 {"DAC L1", NULL, "Stereo DAC MIXL"},
1220 {"DAC L1", NULL, "DAC L1 Power"},
1221 {"DAC R1", NULL, "Stereo DAC MIXR"},
1222 {"DAC R1", NULL, "DAC R1 Power"},
1223
1224 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1225 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1226 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1227 {"DD MIXL", NULL, "Stero2 DAC Power"},
1228
1229 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1230 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1231 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1232 {"DD MIXR", NULL, "Stero2 DAC Power"},
1233
1234 {"OUT MIXL", "BST1 Switch", "BST1"},
1235 {"OUT MIXL", "BST2 Switch", "BST2"},
1236 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1237 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1238 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1239
1240 {"OUT MIXR", "BST2 Switch", "BST2"},
1241 {"OUT MIXR", "BST1 Switch", "BST1"},
1242 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1243 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1244 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1245
1246 {"HPOVOL L", "Switch", "OUT MIXL"},
1247 {"HPOVOL R", "Switch", "OUT MIXR"},
1248 {"OUTVOL L", "Switch", "OUT MIXL"},
1249 {"OUTVOL R", "Switch", "OUT MIXR"},
1250
1251 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1252 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1253 {"HPOL MIX", NULL, "HP L Amp"},
1254 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1255 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1256 {"HPOR MIX", NULL, "HP R Amp"},
1257
1258 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1259 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1260 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1261 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1262
1263 {"HP Amp", NULL, "HPOL MIX"},
1264 {"HP Amp", NULL, "HPOR MIX"},
1265 {"HP Amp", NULL, "Amp Power"},
1266 {"HPO L Playback", "Switch", "HP Amp"},
1267 {"HPO R Playback", "Switch", "HP Amp"},
1268 {"HPOL", NULL, "HPO L Playback"},
1269 {"HPOR", NULL, "HPO R Playback"},
1270
1271 {"LOUT L Playback", "Switch", "LOUT MIX"},
1272 {"LOUT R Playback", "Switch", "LOUT MIX"},
1273 {"LOUTL", NULL, "LOUT L Playback"},
1274 {"LOUTL", NULL, "Amp Power"},
1275 {"LOUTR", NULL, "LOUT R Playback"},
1276 {"LOUTR", NULL, "Amp Power"},
1277
1278 {"PDML", NULL, "PDM L Mux"},
1279 {"PDMR", NULL, "PDM R Mux"},
1280};
1281
1282static int rt5651_hw_params(struct snd_pcm_substream *substream,
1283 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1284{
1285 struct snd_soc_component *component = dai->component;
1286 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1287 unsigned int val_len = 0, val_clk, mask_clk;
1288 int pre_div, bclk_ms, frame_size;
1289
1290 rt5651->lrck[dai->id] = params_rate(params);
1291 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1292
1293 if (pre_div < 0) {
1294 dev_err(component->dev, "Unsupported clock setting\n");
1295 return -EINVAL;
1296 }
1297 frame_size = snd_soc_params_to_frame_size(params);
1298 if (frame_size < 0) {
1299 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
1300 return -EINVAL;
1301 }
1302 bclk_ms = frame_size > 32 ? 1 : 0;
1303 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1304
1305 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1306 rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1307 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1308 bclk_ms, pre_div, dai->id);
1309
1310 switch (params_width(params)) {
1311 case 16:
1312 break;
1313 case 20:
1314 val_len |= RT5651_I2S_DL_20;
1315 break;
1316 case 24:
1317 val_len |= RT5651_I2S_DL_24;
1318 break;
1319 case 8:
1320 val_len |= RT5651_I2S_DL_8;
1321 break;
1322 default:
1323 return -EINVAL;
1324 }
1325
1326 switch (dai->id) {
1327 case RT5651_AIF1:
1328 mask_clk = RT5651_I2S_PD1_MASK;
1329 val_clk = pre_div << RT5651_I2S_PD1_SFT;
1330 snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
1331 RT5651_I2S_DL_MASK, val_len);
1332 snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
1333 break;
1334 case RT5651_AIF2:
1335 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1336 val_clk = pre_div << RT5651_I2S_PD2_SFT;
1337 snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
1338 RT5651_I2S_DL_MASK, val_len);
1339 snd_soc_component_update_bits(component, RT5651_ADDA_CLK1, mask_clk, val_clk);
1340 break;
1341 default:
1342 dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
1343 return -EINVAL;
1344 }
1345
1346 return 0;
1347}
1348
1349static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1350{
1351 struct snd_soc_component *component = dai->component;
1352 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1353 unsigned int reg_val = 0;
1354
1355 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1356 case SND_SOC_DAIFMT_CBM_CFM:
1357 rt5651->master[dai->id] = 1;
1358 break;
1359 case SND_SOC_DAIFMT_CBS_CFS:
1360 reg_val |= RT5651_I2S_MS_S;
1361 rt5651->master[dai->id] = 0;
1362 break;
1363 default:
1364 return -EINVAL;
1365 }
1366
1367 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1368 case SND_SOC_DAIFMT_NB_NF:
1369 break;
1370 case SND_SOC_DAIFMT_IB_NF:
1371 reg_val |= RT5651_I2S_BP_INV;
1372 break;
1373 default:
1374 return -EINVAL;
1375 }
1376
1377 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1378 case SND_SOC_DAIFMT_I2S:
1379 break;
1380 case SND_SOC_DAIFMT_LEFT_J:
1381 reg_val |= RT5651_I2S_DF_LEFT;
1382 break;
1383 case SND_SOC_DAIFMT_DSP_A:
1384 reg_val |= RT5651_I2S_DF_PCM_A;
1385 break;
1386 case SND_SOC_DAIFMT_DSP_B:
1387 reg_val |= RT5651_I2S_DF_PCM_B;
1388 break;
1389 default:
1390 return -EINVAL;
1391 }
1392
1393 switch (dai->id) {
1394 case RT5651_AIF1:
1395 snd_soc_component_update_bits(component, RT5651_I2S1_SDP,
1396 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1397 RT5651_I2S_DF_MASK, reg_val);
1398 break;
1399 case RT5651_AIF2:
1400 snd_soc_component_update_bits(component, RT5651_I2S2_SDP,
1401 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1402 RT5651_I2S_DF_MASK, reg_val);
1403 break;
1404 default:
1405 dev_err(component->dev, "Wrong dai->id: %d\n", dai->id);
1406 return -EINVAL;
1407 }
1408 return 0;
1409}
1410
1411static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1412 int clk_id, unsigned int freq, int dir)
1413{
1414 struct snd_soc_component *component = dai->component;
1415 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1416 unsigned int reg_val = 0;
1417 unsigned int pll_bit = 0;
1418
1419 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1420 return 0;
1421
1422 switch (clk_id) {
1423 case RT5651_SCLK_S_MCLK:
1424 reg_val |= RT5651_SCLK_SRC_MCLK;
1425 break;
1426 case RT5651_SCLK_S_PLL1:
1427 reg_val |= RT5651_SCLK_SRC_PLL1;
1428 pll_bit |= RT5651_PWR_PLL;
1429 break;
1430 case RT5651_SCLK_S_RCCLK:
1431 reg_val |= RT5651_SCLK_SRC_RCCLK;
1432 break;
1433 default:
1434 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1435 return -EINVAL;
1436 }
1437 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1438 RT5651_PWR_PLL, pll_bit);
1439 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1440 RT5651_SCLK_SRC_MASK, reg_val);
1441 rt5651->sysclk = freq;
1442 rt5651->sysclk_src = clk_id;
1443
1444 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1445
1446 return 0;
1447}
1448
1449static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1450 unsigned int freq_in, unsigned int freq_out)
1451{
1452 struct snd_soc_component *component = dai->component;
1453 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1454 struct rl6231_pll_code pll_code;
1455 int ret;
1456
1457 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1458 freq_out == rt5651->pll_out)
1459 return 0;
1460
1461 if (!freq_in || !freq_out) {
1462 dev_dbg(component->dev, "PLL disabled\n");
1463
1464 rt5651->pll_in = 0;
1465 rt5651->pll_out = 0;
1466 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1467 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1468 return 0;
1469 }
1470
1471 switch (source) {
1472 case RT5651_PLL1_S_MCLK:
1473 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1474 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1475 break;
1476 case RT5651_PLL1_S_BCLK1:
1477 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1478 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1479 break;
1480 case RT5651_PLL1_S_BCLK2:
1481 snd_soc_component_update_bits(component, RT5651_GLB_CLK,
1482 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1483 break;
1484 default:
1485 dev_err(component->dev, "Unknown PLL source %d\n", source);
1486 return -EINVAL;
1487 }
1488
1489 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1490 if (ret < 0) {
1491 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
1492 return ret;
1493 }
1494
1495 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1496 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1497 pll_code.n_code, pll_code.k_code);
1498
1499 snd_soc_component_write(component, RT5651_PLL_CTRL1,
1500 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
1501 snd_soc_component_write(component, RT5651_PLL_CTRL2,
1502 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
1503 pll_code.m_bp << RT5651_PLL_M_BP_SFT);
1504
1505 rt5651->pll_in = freq_in;
1506 rt5651->pll_out = freq_out;
1507 rt5651->pll_src = source;
1508
1509 return 0;
1510}
1511
1512static int rt5651_set_bias_level(struct snd_soc_component *component,
1513 enum snd_soc_bias_level level)
1514{
1515 switch (level) {
1516 case SND_SOC_BIAS_PREPARE:
1517 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
1518 if (snd_soc_component_read32(component, RT5651_PLL_MODE_1) & 0x9200)
1519 snd_soc_component_update_bits(component, RT5651_D_MISC,
1520 0xc00, 0xc00);
1521 }
1522 break;
1523 case SND_SOC_BIAS_STANDBY:
1524 if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
1525 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1526 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1527 RT5651_PWR_BG | RT5651_PWR_VREF2,
1528 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1529 RT5651_PWR_BG | RT5651_PWR_VREF2);
1530 usleep_range(10000, 15000);
1531 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1532 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1533 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1534 snd_soc_component_update_bits(component, RT5651_D_MISC, 0x1, 0x1);
1535 }
1536 break;
1537
1538 case SND_SOC_BIAS_OFF:
1539 snd_soc_component_write(component, RT5651_D_MISC, 0x0010);
1540 snd_soc_component_write(component, RT5651_PWR_DIG1, 0x0000);
1541 snd_soc_component_write(component, RT5651_PWR_DIG2, 0x0000);
1542 snd_soc_component_write(component, RT5651_PWR_VOL, 0x0000);
1543 snd_soc_component_write(component, RT5651_PWR_MIXER, 0x0000);
1544
1545 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1546 ~RT5651_PWR_LDO_DVO_MASK, 0);
1547
1548 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1549 ~(RT5651_PWR_PLL | RT5651_PWR_JD_M), 0);
1550 break;
1551
1552 default:
1553 break;
1554 }
1555
1556 return 0;
1557}
1558
1559static void rt5651_enable_micbias1_for_ovcd(struct snd_soc_component *component)
1560{
1561 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1562
1563 snd_soc_dapm_mutex_lock(dapm);
1564 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO");
1565 snd_soc_dapm_force_enable_pin_unlocked(dapm, "micbias1");
1566
1567 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock");
1568 snd_soc_dapm_sync_unlocked(dapm);
1569 snd_soc_dapm_mutex_unlock(dapm);
1570}
1571
1572static void rt5651_disable_micbias1_for_ovcd(struct snd_soc_component *component)
1573{
1574 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1575
1576 snd_soc_dapm_mutex_lock(dapm);
1577 snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock");
1578 snd_soc_dapm_disable_pin_unlocked(dapm, "micbias1");
1579 snd_soc_dapm_disable_pin_unlocked(dapm, "LDO");
1580 snd_soc_dapm_sync_unlocked(dapm);
1581 snd_soc_dapm_mutex_unlock(dapm);
1582}
1583
1584static void rt5651_clear_micbias1_ovcd(struct snd_soc_component *component)
1585{
1586 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
1587 RT5651_MB1_OC_CLR, 0);
1588}
1589
1590static bool rt5651_micbias1_ovcd(struct snd_soc_component *component)
1591{
1592 int val;
1593
1594 val = snd_soc_component_read32(component, RT5651_IRQ_CTRL2);
1595 dev_dbg(component->dev, "irq ctrl2 %#04x\n", val);
1596
1597 return (val & RT5651_MB1_OC_CLR);
1598}
1599
1600static bool rt5651_jack_inserted(struct snd_soc_component *component)
1601{
1602 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1603 int val;
1604
1605 val = snd_soc_component_read32(component, RT5651_INT_IRQ_ST);
1606 dev_dbg(component->dev, "irq status %#04x\n", val);
1607
1608 switch (rt5651->jd_src) {
1609 case RT5651_JD1_1:
1610 val &= 0x1000;
1611 break;
1612 case RT5651_JD1_2:
1613 val &= 0x2000;
1614 break;
1615 case RT5651_JD2:
1616 val &= 0x4000;
1617 break;
1618 default:
1619 break;
1620 }
1621
1622 return val == 0;
1623}
1624
1625
1626#define JACK_SETTLE_TIME 100
1627#define JACK_DETECT_COUNT 5
1628#define JACK_DETECT_MAXCOUNT 20
1629
1630static int rt5651_detect_headset(struct snd_soc_component *component)
1631{
1632 int i, headset_count = 0, headphone_count = 0;
1633
1634
1635
1636
1637
1638
1639
1640
1641 for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) {
1642
1643 rt5651_clear_micbias1_ovcd(component);
1644
1645 msleep(JACK_SETTLE_TIME);
1646
1647
1648 if (!rt5651_jack_inserted(component))
1649 return 0;
1650
1651 if (rt5651_micbias1_ovcd(component)) {
1652
1653
1654
1655
1656
1657 dev_dbg(component->dev, "mic-gnd shorted\n");
1658 headset_count = 0;
1659 headphone_count++;
1660 if (headphone_count == JACK_DETECT_COUNT)
1661 return SND_JACK_HEADPHONE;
1662 } else {
1663 dev_dbg(component->dev, "mic-gnd open\n");
1664 headphone_count = 0;
1665 headset_count++;
1666 if (headset_count == JACK_DETECT_COUNT)
1667 return SND_JACK_HEADSET;
1668 }
1669 }
1670
1671 dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
1672 return SND_JACK_HEADPHONE;
1673}
1674
1675static void rt5651_jack_detect_work(struct work_struct *work)
1676{
1677 struct rt5651_priv *rt5651 =
1678 container_of(work, struct rt5651_priv, jack_detect_work);
1679 int report = 0;
1680
1681 if (rt5651_jack_inserted(rt5651->component)) {
1682 rt5651_enable_micbias1_for_ovcd(rt5651->component);
1683 report = rt5651_detect_headset(rt5651->component);
1684 rt5651_disable_micbias1_for_ovcd(rt5651->component);
1685 }
1686
1687 snd_soc_jack_report(rt5651->hp_jack, report, SND_JACK_HEADSET);
1688}
1689
1690static irqreturn_t rt5651_irq(int irq, void *data)
1691{
1692 struct rt5651_priv *rt5651 = data;
1693
1694 queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
1695
1696 return IRQ_HANDLED;
1697}
1698
1699static int rt5651_set_jack(struct snd_soc_component *component,
1700 struct snd_soc_jack *hp_jack, void *data)
1701{
1702 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1703 int ret;
1704
1705 if (!rt5651->irq)
1706 return -EINVAL;
1707
1708
1709 snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
1710 RT5651_GP1_PIN_MASK, RT5651_GP1_PIN_IRQ);
1711
1712
1713 switch (rt5651->jd_src) {
1714 case RT5651_JD1_1:
1715 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1716 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_1);
1717 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL1,
1718 RT5651_JD1_1_IRQ_EN, RT5651_JD1_1_IRQ_EN);
1719 break;
1720 case RT5651_JD1_2:
1721 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1722 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD1_2);
1723 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL1,
1724 RT5651_JD1_2_IRQ_EN, RT5651_JD1_2_IRQ_EN);
1725 break;
1726 case RT5651_JD2:
1727 snd_soc_component_update_bits(component, RT5651_JD_CTRL2,
1728 RT5651_JD_TRG_SEL_MASK, RT5651_JD_TRG_SEL_JD2);
1729 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL1,
1730 RT5651_JD2_IRQ_EN, RT5651_JD2_IRQ_EN);
1731 break;
1732 case RT5651_JD_NULL:
1733 return 0;
1734 default:
1735 dev_err(component->dev, "Currently only JD1_1 / JD1_2 / JD2 are supported\n");
1736 return -EINVAL;
1737 }
1738
1739
1740 snd_soc_component_update_bits(component, RT5651_PWR_ANLG2,
1741 RT5651_PWR_JD_M, RT5651_PWR_JD_M);
1742
1743
1744 snd_soc_component_write(component, RT5651_PR_BASE + RT5651_BIAS_CUR4,
1745 0xa800 | rt5651->ovcd_sf);
1746
1747 snd_soc_component_update_bits(component, RT5651_MICBIAS,
1748 RT5651_MIC1_OVCD_MASK |
1749 RT5651_MIC1_OVTH_MASK |
1750 RT5651_PWR_CLK12M_MASK |
1751 RT5651_PWR_MB_MASK,
1752 RT5651_MIC1_OVCD_EN |
1753 rt5651->ovcd_th |
1754 RT5651_PWR_MB_PU |
1755 RT5651_PWR_CLK12M_PU);
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766 snd_soc_component_update_bits(component, RT5651_IRQ_CTRL2,
1767 RT5651_MB1_OC_STKY_MASK, RT5651_MB1_OC_STKY_EN);
1768
1769 rt5651->hp_jack = hp_jack;
1770
1771 ret = devm_request_threaded_irq(component->dev, rt5651->irq, NULL,
1772 rt5651_irq,
1773 IRQF_TRIGGER_RISING |
1774 IRQF_TRIGGER_FALLING |
1775 IRQF_ONESHOT, "rt5651", rt5651);
1776 if (ret) {
1777 dev_err(component->dev, "Failed to reguest IRQ: %d\n", ret);
1778 return ret;
1779 }
1780
1781
1782 queue_work(system_power_efficient_wq, &rt5651->jack_detect_work);
1783
1784 return 0;
1785}
1786
1787
1788
1789
1790
1791
1792
1793
1794static void rt5651_apply_properties(struct snd_soc_component *component)
1795{
1796 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1797 u32 val;
1798
1799 if (device_property_read_bool(component->dev, "realtek,in2-differential"))
1800 snd_soc_component_update_bits(component, RT5651_IN1_IN2,
1801 RT5651_IN_DF2, RT5651_IN_DF2);
1802
1803 if (device_property_read_bool(component->dev, "realtek,dmic-en"))
1804 snd_soc_component_update_bits(component, RT5651_GPIO_CTRL1,
1805 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
1806
1807 if (device_property_read_u32(component->dev,
1808 "realtek,jack-detect-source", &val) == 0)
1809 rt5651->jd_src = val;
1810
1811
1812
1813
1814
1815
1816 rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
1817 rt5651->ovcd_sf = RT5651_MIC_OVCD_SF_0P75;
1818
1819 if (device_property_read_u32(component->dev,
1820 "realtek,over-current-threshold-microamp", &val) == 0) {
1821 switch (val) {
1822 case 600:
1823 rt5651->ovcd_th = RT5651_MIC1_OVTH_600UA;
1824 break;
1825 case 1500:
1826 rt5651->ovcd_th = RT5651_MIC1_OVTH_1500UA;
1827 break;
1828 case 2000:
1829 rt5651->ovcd_th = RT5651_MIC1_OVTH_2000UA;
1830 break;
1831 default:
1832 dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n",
1833 val);
1834 }
1835 }
1836
1837 if (device_property_read_u32(component->dev,
1838 "realtek,over-current-scale-factor", &val) == 0) {
1839 if (val <= RT5651_OVCD_SF_1P5)
1840 rt5651->ovcd_sf = val << RT5651_MIC_OVCD_SF_SFT;
1841 else
1842 dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n",
1843 val);
1844 }
1845}
1846
1847static int rt5651_probe(struct snd_soc_component *component)
1848{
1849 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1850
1851 rt5651->component = component;
1852
1853 snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
1854 RT5651_PWR_LDO_DVO_MASK, RT5651_PWR_LDO_DVO_1_2V);
1855
1856 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1857
1858 rt5651_apply_properties(component);
1859
1860 return 0;
1861}
1862
1863#ifdef CONFIG_PM
1864static int rt5651_suspend(struct snd_soc_component *component)
1865{
1866 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1867
1868 regcache_cache_only(rt5651->regmap, true);
1869 regcache_mark_dirty(rt5651->regmap);
1870 return 0;
1871}
1872
1873static int rt5651_resume(struct snd_soc_component *component)
1874{
1875 struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
1876
1877 regcache_cache_only(rt5651->regmap, false);
1878 snd_soc_component_cache_sync(component);
1879
1880 return 0;
1881}
1882#else
1883#define rt5651_suspend NULL
1884#define rt5651_resume NULL
1885#endif
1886
1887#define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1888#define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1889 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1890
1891static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
1892 .hw_params = rt5651_hw_params,
1893 .set_fmt = rt5651_set_dai_fmt,
1894 .set_sysclk = rt5651_set_dai_sysclk,
1895 .set_pll = rt5651_set_dai_pll,
1896};
1897
1898static struct snd_soc_dai_driver rt5651_dai[] = {
1899 {
1900 .name = "rt5651-aif1",
1901 .id = RT5651_AIF1,
1902 .playback = {
1903 .stream_name = "AIF1 Playback",
1904 .channels_min = 1,
1905 .channels_max = 2,
1906 .rates = RT5651_STEREO_RATES,
1907 .formats = RT5651_FORMATS,
1908 },
1909 .capture = {
1910 .stream_name = "AIF1 Capture",
1911 .channels_min = 1,
1912 .channels_max = 2,
1913 .rates = RT5651_STEREO_RATES,
1914 .formats = RT5651_FORMATS,
1915 },
1916 .ops = &rt5651_aif_dai_ops,
1917 },
1918 {
1919 .name = "rt5651-aif2",
1920 .id = RT5651_AIF2,
1921 .playback = {
1922 .stream_name = "AIF2 Playback",
1923 .channels_min = 1,
1924 .channels_max = 2,
1925 .rates = RT5651_STEREO_RATES,
1926 .formats = RT5651_FORMATS,
1927 },
1928 .capture = {
1929 .stream_name = "AIF2 Capture",
1930 .channels_min = 1,
1931 .channels_max = 2,
1932 .rates = RT5651_STEREO_RATES,
1933 .formats = RT5651_FORMATS,
1934 },
1935 .ops = &rt5651_aif_dai_ops,
1936 },
1937};
1938
1939static const struct snd_soc_component_driver soc_component_dev_rt5651 = {
1940 .probe = rt5651_probe,
1941 .suspend = rt5651_suspend,
1942 .resume = rt5651_resume,
1943 .set_bias_level = rt5651_set_bias_level,
1944 .set_jack = rt5651_set_jack,
1945 .controls = rt5651_snd_controls,
1946 .num_controls = ARRAY_SIZE(rt5651_snd_controls),
1947 .dapm_widgets = rt5651_dapm_widgets,
1948 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
1949 .dapm_routes = rt5651_dapm_routes,
1950 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
1951 .use_pmdown_time = 1,
1952 .endianness = 1,
1953 .non_legacy_dai_naming = 1,
1954};
1955
1956static const struct regmap_config rt5651_regmap = {
1957 .reg_bits = 8,
1958 .val_bits = 16,
1959
1960 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
1961 RT5651_PR_SPACING),
1962 .volatile_reg = rt5651_volatile_register,
1963 .readable_reg = rt5651_readable_register,
1964
1965 .cache_type = REGCACHE_RBTREE,
1966 .reg_defaults = rt5651_reg,
1967 .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
1968 .ranges = rt5651_ranges,
1969 .num_ranges = ARRAY_SIZE(rt5651_ranges),
1970 .use_single_rw = true,
1971};
1972
1973#if defined(CONFIG_OF)
1974static const struct of_device_id rt5651_of_match[] = {
1975 { .compatible = "realtek,rt5651", },
1976 {},
1977};
1978MODULE_DEVICE_TABLE(of, rt5651_of_match);
1979#endif
1980
1981#ifdef CONFIG_ACPI
1982static const struct acpi_device_id rt5651_acpi_match[] = {
1983 { "10EC5651", 0 },
1984 { },
1985};
1986MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match);
1987#endif
1988
1989static const struct i2c_device_id rt5651_i2c_id[] = {
1990 { "rt5651", 0 },
1991 { }
1992};
1993MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
1994
1995
1996
1997
1998
1999static int rt5651_i2c_probe(struct i2c_client *i2c,
2000 const struct i2c_device_id *id)
2001{
2002 struct rt5651_priv *rt5651;
2003 int ret;
2004
2005 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
2006 GFP_KERNEL);
2007 if (NULL == rt5651)
2008 return -ENOMEM;
2009
2010 i2c_set_clientdata(i2c, rt5651);
2011
2012 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
2013 if (IS_ERR(rt5651->regmap)) {
2014 ret = PTR_ERR(rt5651->regmap);
2015 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2016 ret);
2017 return ret;
2018 }
2019
2020 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
2021 if (ret != RT5651_DEVICE_ID_VALUE) {
2022 dev_err(&i2c->dev,
2023 "Device with ID register %#x is not rt5651\n", ret);
2024 return -ENODEV;
2025 }
2026
2027 regmap_write(rt5651->regmap, RT5651_RESET, 0);
2028
2029 ret = regmap_register_patch(rt5651->regmap, init_list,
2030 ARRAY_SIZE(init_list));
2031 if (ret != 0)
2032 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2033
2034 rt5651->irq = i2c->irq;
2035 rt5651->hp_mute = 1;
2036
2037 INIT_WORK(&rt5651->jack_detect_work, rt5651_jack_detect_work);
2038
2039 ret = devm_snd_soc_register_component(&i2c->dev,
2040 &soc_component_dev_rt5651,
2041 rt5651_dai, ARRAY_SIZE(rt5651_dai));
2042
2043 return ret;
2044}
2045
2046static int rt5651_i2c_remove(struct i2c_client *i2c)
2047{
2048 struct rt5651_priv *rt5651 = i2c_get_clientdata(i2c);
2049
2050 cancel_work_sync(&rt5651->jack_detect_work);
2051
2052 return 0;
2053}
2054
2055static struct i2c_driver rt5651_i2c_driver = {
2056 .driver = {
2057 .name = "rt5651",
2058 .acpi_match_table = ACPI_PTR(rt5651_acpi_match),
2059 .of_match_table = of_match_ptr(rt5651_of_match),
2060 },
2061 .probe = rt5651_i2c_probe,
2062 .remove = rt5651_i2c_remove,
2063 .id_table = rt5651_i2c_id,
2064};
2065module_i2c_driver(rt5651_i2c_driver);
2066
2067MODULE_DESCRIPTION("ASoC RT5651 driver");
2068MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2069MODULE_LICENSE("GPL v2");
2070
