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12#include <linux/gpio/consumer.h>
13#include <linux/i2c.h>
14#include <linux/module.h>
15#include <linux/regmap.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19#include <sound/soc-dai.h>
20#include <sound/tlv.h>
21
22#define AUD96P22_RESET 0x00
23#define RST_DAC_DPZ BIT(0)
24#define RST_ADC_DPZ BIT(1)
25#define AUD96P22_I2S1_CONFIG_0 0x03
26#define I2S1_MS_MODE BIT(3)
27#define I2S1_MODE_MASK 0x7
28#define I2S1_MODE_RIGHT_J 0x0
29#define I2S1_MODE_I2S 0x1
30#define I2S1_MODE_LEFT_J 0x2
31#define AUD96P22_PD_0 0x15
32#define AUD96P22_PD_1 0x16
33#define AUD96P22_PD_3 0x18
34#define AUD96P22_PD_4 0x19
35#define AUD96P22_MUTE_0 0x1d
36#define AUD96P22_MUTE_2 0x1f
37#define AUD96P22_MUTE_4 0x21
38#define AUD96P22_RECVOL_0 0x24
39#define AUD96P22_RECVOL_1 0x25
40#define AUD96P22_PGA1VOL_0 0x26
41#define AUD96P22_PGA1VOL_1 0x27
42#define AUD96P22_LMVOL_0 0x34
43#define AUD96P22_LMVOL_1 0x35
44#define AUD96P22_HS1VOL_0 0x38
45#define AUD96P22_HS1VOL_1 0x39
46#define AUD96P22_PGA1SEL_0 0x47
47#define AUD96P22_PGA1SEL_1 0x48
48#define AUD96P22_LDR1SEL_0 0x59
49#define AUD96P22_LDR1SEL_1 0x60
50#define AUD96P22_LDR2SEL_0 0x5d
51#define AUD96P22_REG_MAX 0xfb
52
53struct aud96p22_priv {
54 struct regmap *regmap;
55};
56
57static int aud96p22_adc_event(struct snd_soc_dapm_widget *w,
58 struct snd_kcontrol *kcontrol, int event)
59{
60 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
61 struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
62 struct regmap *regmap = priv->regmap;
63
64 if (event != SND_SOC_DAPM_POST_PMU)
65 return -EINVAL;
66
67
68 regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, 0);
69 regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, RST_ADC_DPZ);
70
71 return 0;
72}
73
74static int aud96p22_dac_event(struct snd_soc_dapm_widget *w,
75 struct snd_kcontrol *kcontrol, int event)
76{
77 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
78 struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
79 struct regmap *regmap = priv->regmap;
80
81 if (event != SND_SOC_DAPM_POST_PMU)
82 return -EINVAL;
83
84
85 regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, 0);
86 regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, RST_DAC_DPZ);
87
88 return 0;
89}
90
91static const DECLARE_TLV_DB_SCALE(lm_tlv, -11550, 50, 0);
92static const DECLARE_TLV_DB_SCALE(hs_tlv, -3900, 300, 0);
93static const DECLARE_TLV_DB_SCALE(rec_tlv, -9550, 50, 0);
94static const DECLARE_TLV_DB_SCALE(pga_tlv, -1800, 100, 0);
95
96static const struct snd_kcontrol_new aud96p22_snd_controls[] = {
97
98 SOC_DOUBLE_R_TLV("Master Playback Volume", AUD96P22_LMVOL_0,
99 AUD96P22_LMVOL_1, 0, 0xff, 0, lm_tlv),
100 SOC_DOUBLE_R_TLV("Headphone Volume", AUD96P22_HS1VOL_0,
101 AUD96P22_HS1VOL_1, 0, 0xf, 0, hs_tlv),
102 SOC_DOUBLE_R_TLV("Master Capture Volume", AUD96P22_RECVOL_0,
103 AUD96P22_RECVOL_1, 0, 0xff, 0, rec_tlv),
104 SOC_DOUBLE_R_TLV("Analogue Capture Volume", AUD96P22_PGA1VOL_0,
105 AUD96P22_PGA1VOL_1, 0, 0x37, 0, pga_tlv),
106
107
108 SOC_DOUBLE("Master Playback Switch", AUD96P22_MUTE_2, 0, 1, 1, 1),
109 SOC_DOUBLE("Headphone Switch", AUD96P22_MUTE_2, 4, 5, 1, 1),
110 SOC_DOUBLE("Line Out Switch", AUD96P22_MUTE_4, 0, 1, 1, 1),
111 SOC_DOUBLE("Speaker Switch", AUD96P22_MUTE_4, 2, 3, 1, 1),
112 SOC_DOUBLE("Master Capture Switch", AUD96P22_MUTE_0, 0, 1, 1, 1),
113 SOC_DOUBLE("Analogue Capture Switch", AUD96P22_MUTE_0, 2, 3, 1, 1),
114};
115
116
117static const unsigned int ain_mux_values[] = {
118 0, 1, 3, 4, 5,
119};
120
121static const char * const ainl_mux_texts[] = {
122 "AINL1 differential",
123 "AINL1 single-ended",
124 "AINL3 single-ended",
125 "AINL2 differential",
126 "AINL2 single-ended",
127};
128
129static const char * const ainr_mux_texts[] = {
130 "AINR1 differential",
131 "AINR1 single-ended",
132 "AINR3 single-ended",
133 "AINR2 differential",
134 "AINR2 single-ended",
135};
136
137static SOC_VALUE_ENUM_SINGLE_DECL(ainl_mux_enum, AUD96P22_PGA1SEL_0,
138 0, 0x7, ainl_mux_texts, ain_mux_values);
139static SOC_VALUE_ENUM_SINGLE_DECL(ainr_mux_enum, AUD96P22_PGA1SEL_1,
140 0, 0x7, ainr_mux_texts, ain_mux_values);
141
142static const struct snd_kcontrol_new ainl_mux_kcontrol =
143 SOC_DAPM_ENUM("AINL Mux", ainl_mux_enum);
144static const struct snd_kcontrol_new ainr_mux_kcontrol =
145 SOC_DAPM_ENUM("AINR Mux", ainr_mux_enum);
146
147
148static const struct snd_kcontrol_new ld1_left_kcontrols[] = {
149 SOC_DAPM_SINGLE("DACL LD1L Switch", AUD96P22_LDR1SEL_0, 0, 1, 0),
150 SOC_DAPM_SINGLE("AINL LD1L Switch", AUD96P22_LDR1SEL_0, 1, 1, 0),
151 SOC_DAPM_SINGLE("AINR LD1L Switch", AUD96P22_LDR1SEL_0, 2, 1, 0),
152};
153
154static const struct snd_kcontrol_new ld1_right_kcontrols[] = {
155 SOC_DAPM_SINGLE("DACR LD1R Switch", AUD96P22_LDR1SEL_1, 8, 1, 0),
156 SOC_DAPM_SINGLE("AINR LD1R Switch", AUD96P22_LDR1SEL_1, 9, 1, 0),
157 SOC_DAPM_SINGLE("AINL LD1R Switch", AUD96P22_LDR1SEL_1, 10, 1, 0),
158};
159
160static const struct snd_kcontrol_new ld2_kcontrols[] = {
161 SOC_DAPM_SINGLE("DACL LD2 Switch", AUD96P22_LDR2SEL_0, 0, 1, 0),
162 SOC_DAPM_SINGLE("AINL LD2 Switch", AUD96P22_LDR2SEL_0, 1, 1, 0),
163 SOC_DAPM_SINGLE("DACR LD2 Switch", AUD96P22_LDR2SEL_0, 2, 1, 0),
164};
165
166static const struct snd_soc_dapm_widget aud96p22_dapm_widgets[] = {
167
168 SND_SOC_DAPM_SUPPLY("POWER", AUD96P22_PD_0, 0, 0, NULL, 0),
169
170
171 SND_SOC_DAPM_INPUT("AINL1P"),
172 SND_SOC_DAPM_INPUT("AINL2P"),
173 SND_SOC_DAPM_INPUT("AINL3"),
174 SND_SOC_DAPM_INPUT("AINL1N"),
175 SND_SOC_DAPM_INPUT("AINL2N"),
176 SND_SOC_DAPM_INPUT("AINR2N"),
177 SND_SOC_DAPM_INPUT("AINR1N"),
178 SND_SOC_DAPM_INPUT("AINR3"),
179 SND_SOC_DAPM_INPUT("AINR2P"),
180 SND_SOC_DAPM_INPUT("AINR1P"),
181
182
183 SND_SOC_DAPM_MUX("AINLMUX", AUD96P22_PD_1, 2, 0, &ainl_mux_kcontrol),
184 SND_SOC_DAPM_MUX("AINRMUX", AUD96P22_PD_1, 3, 0, &ainr_mux_kcontrol),
185
186
187 SND_SOC_DAPM_ADC_E("ADCL", "Capture Left", AUD96P22_PD_1, 0, 0,
188 aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
189 SND_SOC_DAPM_ADC_E("ADCR", "Capture Right", AUD96P22_PD_1, 1, 0,
190 aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
191
192
193 SND_SOC_DAPM_DAC_E("DACL", "Playback Left", AUD96P22_PD_3, 0, 0,
194 aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
195 SND_SOC_DAPM_DAC_E("DACR", "Playback Right", AUD96P22_PD_3, 1, 0,
196 aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
197
198
199 SND_SOC_DAPM_MIXER("LD1L", AUD96P22_PD_3, 6, 0, ld1_left_kcontrols,
200 ARRAY_SIZE(ld1_left_kcontrols)),
201 SND_SOC_DAPM_MIXER("LD1R", AUD96P22_PD_3, 7, 0, ld1_right_kcontrols,
202 ARRAY_SIZE(ld1_right_kcontrols)),
203 SND_SOC_DAPM_MIXER("LD2", AUD96P22_PD_4, 2, 0, ld2_kcontrols,
204 ARRAY_SIZE(ld2_kcontrols)),
205
206
207 SND_SOC_DAPM_SUPPLY("HS1L", AUD96P22_PD_3, 4, 0, NULL, 0),
208 SND_SOC_DAPM_SUPPLY("HS1R", AUD96P22_PD_3, 5, 0, NULL, 0),
209
210
211 SND_SOC_DAPM_OUTPUT("HSOUTL"),
212 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
213 SND_SOC_DAPM_OUTPUT("LINEOUTMP"),
214 SND_SOC_DAPM_OUTPUT("LINEOUTMN"),
215 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
216 SND_SOC_DAPM_OUTPUT("HSOUTR"),
217};
218
219static const struct snd_soc_dapm_route aud96p22_dapm_routes[] = {
220 { "AINLMUX", "AINL1 differential", "AINL1N" },
221 { "AINLMUX", "AINL1 single-ended", "AINL1P" },
222 { "AINLMUX", "AINL3 single-ended", "AINL3" },
223 { "AINLMUX", "AINL2 differential", "AINL2N" },
224 { "AINLMUX", "AINL2 single-ended", "AINL2P" },
225
226 { "AINRMUX", "AINR1 differential", "AINR1N" },
227 { "AINRMUX", "AINR1 single-ended", "AINR1P" },
228 { "AINRMUX", "AINR3 single-ended", "AINR3" },
229 { "AINRMUX", "AINR2 differential", "AINR2N" },
230 { "AINRMUX", "AINR2 single-ended", "AINR2P" },
231
232 { "ADCL", NULL, "AINLMUX" },
233 { "ADCR", NULL, "AINRMUX" },
234
235 { "ADCL", NULL, "POWER" },
236 { "ADCR", NULL, "POWER" },
237 { "DACL", NULL, "POWER" },
238 { "DACR", NULL, "POWER" },
239
240 { "LD1L", "DACL LD1L Switch", "DACL" },
241 { "LD1L", "AINL LD1L Switch", "AINLMUX" },
242 { "LD1L", "AINR LD1L Switch", "AINRMUX" },
243
244 { "LD1R", "DACR LD1R Switch", "DACR" },
245 { "LD1R", "AINR LD1R Switch", "AINRMUX" },
246 { "LD1R", "AINL LD1R Switch", "AINLMUX" },
247
248 { "LD2", "DACL LD2 Switch", "DACL" },
249 { "LD2", "AINL LD2 Switch", "AINLMUX" },
250 { "LD2", "DACR LD2 Switch", "DACR" },
251
252 { "HSOUTL", NULL, "LD1L" },
253 { "HSOUTR", NULL, "LD1R" },
254 { "HSOUTL", NULL, "HS1L" },
255 { "HSOUTR", NULL, "HS1R" },
256
257 { "LINEOUTL", NULL, "LD1L" },
258 { "LINEOUTR", NULL, "LD1R" },
259
260 { "LINEOUTMP", NULL, "LD2" },
261 { "LINEOUTMN", NULL, "LD2" },
262};
263
264static const struct snd_soc_component_driver aud96p22_driver = {
265 .controls = aud96p22_snd_controls,
266 .num_controls = ARRAY_SIZE(aud96p22_snd_controls),
267 .dapm_widgets = aud96p22_dapm_widgets,
268 .num_dapm_widgets = ARRAY_SIZE(aud96p22_dapm_widgets),
269 .dapm_routes = aud96p22_dapm_routes,
270 .num_dapm_routes = ARRAY_SIZE(aud96p22_dapm_routes),
271 .idle_bias_on = 1,
272 .use_pmdown_time = 1,
273 .endianness = 1,
274 .non_legacy_dai_naming = 1,
275};
276
277static int aud96p22_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
278{
279 struct aud96p22_priv *priv = snd_soc_component_get_drvdata(dai->component);
280 struct regmap *regmap = priv->regmap;
281 unsigned int val;
282
283
284 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
285 case SND_SOC_DAIFMT_CBS_CFS:
286 val = 0;
287 break;
288 case SND_SOC_DAIFMT_CBM_CFM:
289 val = I2S1_MS_MODE;
290 break;
291 default:
292 return -EINVAL;
293 }
294
295 regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MS_MODE, val);
296
297
298 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
299 case SND_SOC_DAIFMT_RIGHT_J:
300 val = I2S1_MODE_RIGHT_J;
301 break;
302 case SND_SOC_DAIFMT_I2S:
303 val = I2S1_MODE_I2S;
304 break;
305 case SND_SOC_DAIFMT_LEFT_J:
306 val = I2S1_MODE_LEFT_J;
307 break;
308 default:
309 return -EINVAL;
310 }
311
312 regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MODE_MASK, val);
313
314 return 0;
315}
316
317static const struct snd_soc_dai_ops aud96p22_dai_ops = {
318 .set_fmt = aud96p22_set_fmt,
319};
320
321#define AUD96P22_RATES SNDRV_PCM_RATE_8000_192000
322#define AUD96P22_FORMATS (\
323 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
324 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
325
326static struct snd_soc_dai_driver aud96p22_dai = {
327 .name = "aud96p22-dai",
328 .playback = {
329 .stream_name = "Playback",
330 .channels_min = 1,
331 .channels_max = 2,
332 .rates = AUD96P22_RATES,
333 .formats = AUD96P22_FORMATS,
334 },
335 .capture = {
336 .stream_name = "Capture",
337 .channels_min = 1,
338 .channels_max = 2,
339 .rates = AUD96P22_RATES,
340 .formats = AUD96P22_FORMATS,
341 },
342 .ops = &aud96p22_dai_ops,
343};
344
345static const struct regmap_config aud96p22_regmap = {
346 .reg_bits = 8,
347 .val_bits = 8,
348 .max_register = AUD96P22_REG_MAX,
349 .cache_type = REGCACHE_RBTREE,
350};
351
352static int aud96p22_i2c_probe(struct i2c_client *i2c,
353 const struct i2c_device_id *id)
354{
355 struct device *dev = &i2c->dev;
356 struct aud96p22_priv *priv;
357 int ret;
358
359 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
360 if (priv == NULL)
361 return -ENOMEM;
362
363 priv->regmap = devm_regmap_init_i2c(i2c, &aud96p22_regmap);
364 if (IS_ERR(priv->regmap)) {
365 ret = PTR_ERR(priv->regmap);
366 dev_err(dev, "failed to init i2c regmap: %d\n", ret);
367 return ret;
368 }
369
370 i2c_set_clientdata(i2c, priv);
371
372 ret = devm_snd_soc_register_component(dev, &aud96p22_driver, &aud96p22_dai, 1);
373 if (ret) {
374 dev_err(dev, "failed to register component: %d\n", ret);
375 return ret;
376 }
377
378 return 0;
379}
380
381static int aud96p22_i2c_remove(struct i2c_client *i2c)
382{
383 return 0;
384}
385
386static const struct of_device_id aud96p22_dt_ids[] = {
387 { .compatible = "zte,zx-aud96p22", },
388 { }
389};
390MODULE_DEVICE_TABLE(of, aud96p22_dt_ids);
391
392static struct i2c_driver aud96p22_i2c_driver = {
393 .driver = {
394 .name = "zx_aud96p22",
395 .of_match_table = aud96p22_dt_ids,
396 },
397 .probe = aud96p22_i2c_probe,
398 .remove = aud96p22_i2c_remove,
399};
400module_i2c_driver(aud96p22_i2c_driver);
401
402MODULE_DESCRIPTION("ZTE ASoC AUD96P22 CODEC driver");
403MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
404MODULE_LICENSE("GPL v2");
405
