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13#ifndef _FSL_ASRC_H
14#define _FSL_ASRC_H
15
16#define IN 0
17#define OUT 1
18
19#define ASRC_DMA_BUFFER_NUM 2
20#define ASRC_INPUTFIFO_THRESHOLD 32
21#define ASRC_OUTPUTFIFO_THRESHOLD 32
22#define ASRC_FIFO_THRESHOLD_MIN 0
23#define ASRC_FIFO_THRESHOLD_MAX 63
24#define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
25#define ASRC_MAX_BUFFER_SIZE (1024 * 48)
26#define ASRC_OUTPUT_LAST_SAMPLE 8
27
28#define IDEAL_RATIO_RATE 1000000
29
30#define REG_ASRCTR 0x00
31#define REG_ASRIER 0x04
32#define REG_ASRCNCR 0x0C
33#define REG_ASRCFG 0x10
34#define REG_ASRCSR 0x14
35
36#define REG_ASRCDR1 0x18
37#define REG_ASRCDR2 0x1C
38#define REG_ASRCDR(i) ((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
39
40#define REG_ASRSTR 0x20
41#define REG_ASRRA 0x24
42#define REG_ASRRB 0x28
43#define REG_ASRRC 0x2C
44#define REG_ASRPM1 0x40
45#define REG_ASRPM2 0x44
46#define REG_ASRPM3 0x48
47#define REG_ASRPM4 0x4C
48#define REG_ASRPM5 0x50
49#define REG_ASRTFR1 0x54
50#define REG_ASRCCR 0x5C
51
52#define REG_ASRDIA 0x60
53#define REG_ASRDOA 0x64
54#define REG_ASRDIB 0x68
55#define REG_ASRDOB 0x6C
56#define REG_ASRDIC 0x70
57#define REG_ASRDOC 0x74
58#define REG_ASRDI(i) (REG_ASRDIA + (i << 3))
59#define REG_ASRDO(i) (REG_ASRDOA + (i << 3))
60#define REG_ASRDx(x, i) ((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
61
62#define REG_ASRIDRHA 0x80
63#define REG_ASRIDRLA 0x84
64#define REG_ASRIDRHB 0x88
65#define REG_ASRIDRLB 0x8C
66#define REG_ASRIDRHC 0x90
67#define REG_ASRIDRLC 0x94
68#define REG_ASRIDRH(i) (REG_ASRIDRHA + (i << 3))
69#define REG_ASRIDRL(i) (REG_ASRIDRLA + (i << 3))
70
71#define REG_ASR76K 0x98
72#define REG_ASR56K 0x9C
73
74#define REG_ASRMCRA 0xA0
75#define REG_ASRFSTA 0xA4
76#define REG_ASRMCRB 0xA8
77#define REG_ASRFSTB 0xAC
78#define REG_ASRMCRC 0xB0
79#define REG_ASRFSTC 0xB4
80#define REG_ASRMCR(i) (REG_ASRMCRA + (i << 3))
81#define REG_ASRFST(i) (REG_ASRFSTA + (i << 3))
82
83#define REG_ASRMCR1A 0xC0
84#define REG_ASRMCR1B 0xC4
85#define REG_ASRMCR1C 0xC8
86#define REG_ASRMCR1(i) (REG_ASRMCR1A + (i << 2))
87
88
89
90#define ASRCTR_ATSi_SHIFT(i) (20 + i)
91#define ASRCTR_ATSi_MASK(i) (1 << ASRCTR_ATSi_SHIFT(i))
92#define ASRCTR_ATS(i) (1 << ASRCTR_ATSi_SHIFT(i))
93#define ASRCTR_USRi_SHIFT(i) (14 + (i << 1))
94#define ASRCTR_USRi_MASK(i) (1 << ASRCTR_USRi_SHIFT(i))
95#define ASRCTR_USR(i) (1 << ASRCTR_USRi_SHIFT(i))
96#define ASRCTR_IDRi_SHIFT(i) (13 + (i << 1))
97#define ASRCTR_IDRi_MASK(i) (1 << ASRCTR_IDRi_SHIFT(i))
98#define ASRCTR_IDR(i) (1 << ASRCTR_IDRi_SHIFT(i))
99#define ASRCTR_SRST_SHIFT 4
100#define ASRCTR_SRST_MASK (1 << ASRCTR_SRST_SHIFT)
101#define ASRCTR_SRST (1 << ASRCTR_SRST_SHIFT)
102#define ASRCTR_ASRCEi_SHIFT(i) (1 + i)
103#define ASRCTR_ASRCEi_MASK(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
104#define ASRCTR_ASRCE(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
105#define ASRCTR_ASRCEi_ALL_MASK (0x7 << ASRCTR_ASRCEi_SHIFT(0))
106#define ASRCTR_ASRCEN_SHIFT 0
107#define ASRCTR_ASRCEN_MASK (1 << ASRCTR_ASRCEN_SHIFT)
108#define ASRCTR_ASRCEN (1 << ASRCTR_ASRCEN_SHIFT)
109
110
111#define ASRIER_AFPWE_SHIFT 7
112#define ASRIER_AFPWE_MASK (1 << ASRIER_AFPWE_SHIFT)
113#define ASRIER_AFPWE (1 << ASRIER_AFPWE_SHIFT)
114#define ASRIER_AOLIE_SHIFT 6
115#define ASRIER_AOLIE_MASK (1 << ASRIER_AOLIE_SHIFT)
116#define ASRIER_AOLIE (1 << ASRIER_AOLIE_SHIFT)
117#define ASRIER_ADOEi_SHIFT(i) (3 + i)
118#define ASRIER_ADOEi_MASK(i) (1 << ASRIER_ADOEi_SHIFT(i))
119#define ASRIER_ADOE(i) (1 << ASRIER_ADOEi_SHIFT(i))
120#define ASRIER_ADIEi_SHIFT(i) (0 + i)
121#define ASRIER_ADIEi_MASK(i) (1 << ASRIER_ADIEi_SHIFT(i))
122#define ASRIER_ADIE(i) (1 << ASRIER_ADIEi_SHIFT(i))
123
124
125#define ASRCNCR_ANCi_SHIFT(i, b) (b * i)
126#define ASRCNCR_ANCi_MASK(i, b) (((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
127#define ASRCNCR_ANCi(i, v, b) ((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
128
129
130#define ASRCFG_INIRQi_SHIFT(i) (21 + i)
131#define ASRCFG_INIRQi_MASK(i) (1 << ASRCFG_INIRQi_SHIFT(i))
132#define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
133#define ASRCFG_NDPRi_SHIFT(i) (18 + i)
134#define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
135#define ASRCFG_NDPRi_ALL_SHIFT 18
136#define ASRCFG_NDPRi_ALL_MASK (7 << ASRCFG_NDPRi_ALL_SHIFT)
137#define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
138#define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
139#define ASRCFG_POSTMODi_WIDTH 2
140#define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
141#define ASRCFG_POSTMODi_ALL_MASK (ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
142#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
143#define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
144#define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
145#define ASRCFG_POSTMODi_DOWN(i) (2 << ASRCFG_POSTMODi_SHIFT(i))
146#define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
147#define ASRCFG_PREMODi_WIDTH 2
148#define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
149#define ASRCFG_PREMODi_ALL_MASK (ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
150#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
151#define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
152#define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
153#define ASRCFG_PREMODi_DOWN(i) (2 << ASRCFG_PREMODi_SHIFT(i))
154#define ASRCFG_PREMODi_BYPASS(i) (3 << ASRCFG_PREMODi_SHIFT(i))
155
156
157#define ASRCSR_AxCSi_WIDTH 4
158#define ASRCSR_AxCSi_MASK ((1 << ASRCSR_AxCSi_WIDTH) - 1)
159#define ASRCSR_AOCSi_SHIFT(i) (12 + (i << 2))
160#define ASRCSR_AOCSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
161#define ASRCSR_AOCS(i, v) ((v) << ASRCSR_AOCSi_SHIFT(i))
162#define ASRCSR_AICSi_SHIFT(i) (i << 2)
163#define ASRCSR_AICSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
164#define ASRCSR_AICS(i, v) ((v) << ASRCSR_AICSi_SHIFT(i))
165
166
167#define ASRCDRi_AxCPi_WIDTH 3
168#define ASRCDRi_AICPi_SHIFT(i) (0 + (i % 2) * 6)
169#define ASRCDRi_AICPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
170#define ASRCDRi_AICP(i, v) ((v) << ASRCDRi_AICPi_SHIFT(i))
171#define ASRCDRi_AICDi_SHIFT(i) (3 + (i % 2) * 6)
172#define ASRCDRi_AICDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
173#define ASRCDRi_AICD(i, v) ((v) << ASRCDRi_AICDi_SHIFT(i))
174#define ASRCDRi_AOCPi_SHIFT(i) ((i < 2) ? 12 + i * 6 : 6)
175#define ASRCDRi_AOCPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
176#define ASRCDRi_AOCP(i, v) ((v) << ASRCDRi_AOCPi_SHIFT(i))
177#define ASRCDRi_AOCDi_SHIFT(i) ((i < 2) ? 15 + i * 6 : 9)
178#define ASRCDRi_AOCDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
179#define ASRCDRi_AOCD(i, v) ((v) << ASRCDRi_AOCDi_SHIFT(i))
180
181
182#define ASRSTR_DSLCNT_SHIFT 21
183#define ASRSTR_DSLCNT_MASK (1 << ASRSTR_DSLCNT_SHIFT)
184#define ASRSTR_DSLCNT (1 << ASRSTR_DSLCNT_SHIFT)
185#define ASRSTR_ATQOL_SHIFT 20
186#define ASRSTR_ATQOL_MASK (1 << ASRSTR_ATQOL_SHIFT)
187#define ASRSTR_ATQOL (1 << ASRSTR_ATQOL_SHIFT)
188#define ASRSTR_AOOLi_SHIFT(i) (17 + i)
189#define ASRSTR_AOOLi_MASK(i) (1 << ASRSTR_AOOLi_SHIFT(i))
190#define ASRSTR_AOOL(i) (1 << ASRSTR_AOOLi_SHIFT(i))
191#define ASRSTR_AIOLi_SHIFT(i) (14 + i)
192#define ASRSTR_AIOLi_MASK(i) (1 << ASRSTR_AIOLi_SHIFT(i))
193#define ASRSTR_AIOL(i) (1 << ASRSTR_AIOLi_SHIFT(i))
194#define ASRSTR_AODOi_SHIFT(i) (11 + i)
195#define ASRSTR_AODOi_MASK(i) (1 << ASRSTR_AODOi_SHIFT(i))
196#define ASRSTR_AODO(i) (1 << ASRSTR_AODOi_SHIFT(i))
197#define ASRSTR_AIDUi_SHIFT(i) (8 + i)
198#define ASRSTR_AIDUi_MASK(i) (1 << ASRSTR_AIDUi_SHIFT(i))
199#define ASRSTR_AIDU(i) (1 << ASRSTR_AIDUi_SHIFT(i))
200#define ASRSTR_FPWT_SHIFT 7
201#define ASRSTR_FPWT_MASK (1 << ASRSTR_FPWT_SHIFT)
202#define ASRSTR_FPWT (1 << ASRSTR_FPWT_SHIFT)
203#define ASRSTR_AOLE_SHIFT 6
204#define ASRSTR_AOLE_MASK (1 << ASRSTR_AOLE_SHIFT)
205#define ASRSTR_AOLE (1 << ASRSTR_AOLE_SHIFT)
206#define ASRSTR_AODEi_SHIFT(i) (3 + i)
207#define ASRSTR_AODFi_MASK(i) (1 << ASRSTR_AODEi_SHIFT(i))
208#define ASRSTR_AODF(i) (1 << ASRSTR_AODEi_SHIFT(i))
209#define ASRSTR_AIDEi_SHIFT(i) (0 + i)
210#define ASRSTR_AIDEi_MASK(i) (1 << ASRSTR_AIDEi_SHIFT(i))
211#define ASRSTR_AIDE(i) (1 << ASRSTR_AIDEi_SHIFT(i))
212
213
214#define ASRTFR1_TF_BASE_WIDTH 7
215#define ASRTFR1_TF_BASE_SHIFT 6
216#define ASRTFR1_TF_BASE_MASK (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
217#define ASRTFR1_TF_BASE(i) ((i) << ASRTFR1_TF_BASE_SHIFT)
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224#define ASRMCRi_ZEROBUFi_SHIFT 23
225#define ASRMCRi_ZEROBUFi_MASK (1 << ASRMCRi_ZEROBUFi_SHIFT)
226#define ASRMCRi_ZEROBUFi (1 << ASRMCRi_ZEROBUFi_SHIFT)
227#define ASRMCRi_EXTTHRSHi_SHIFT 22
228#define ASRMCRi_EXTTHRSHi_MASK (1 << ASRMCRi_EXTTHRSHi_SHIFT)
229#define ASRMCRi_EXTTHRSHi (1 << ASRMCRi_EXTTHRSHi_SHIFT)
230#define ASRMCRi_BUFSTALLi_SHIFT 21
231#define ASRMCRi_BUFSTALLi_MASK (1 << ASRMCRi_BUFSTALLi_SHIFT)
232#define ASRMCRi_BUFSTALLi (1 << ASRMCRi_BUFSTALLi_SHIFT)
233#define ASRMCRi_BYPASSPOLYi_SHIFT 20
234#define ASRMCRi_BYPASSPOLYi_MASK (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
235#define ASRMCRi_BYPASSPOLYi (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
236#define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH 6
237#define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT 12
238#define ASRMCRi_OUTFIFO_THRESHOLD_MASK (((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
239#define ASRMCRi_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
240#define ASRMCRi_RSYNIFi_SHIFT 11
241#define ASRMCRi_RSYNIFi_MASK (1 << ASRMCRi_RSYNIFi_SHIFT)
242#define ASRMCRi_RSYNIFi (1 << ASRMCRi_RSYNIFi_SHIFT)
243#define ASRMCRi_RSYNOFi_SHIFT 10
244#define ASRMCRi_RSYNOFi_MASK (1 << ASRMCRi_RSYNOFi_SHIFT)
245#define ASRMCRi_RSYNOFi (1 << ASRMCRi_RSYNOFi_SHIFT)
246#define ASRMCRi_INFIFO_THRESHOLD_WIDTH 6
247#define ASRMCRi_INFIFO_THRESHOLD_SHIFT 0
248#define ASRMCRi_INFIFO_THRESHOLD_MASK (((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
249#define ASRMCRi_INFIFO_THRESHOLD(v) (((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
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256#define ASRFSTi_OAFi_SHIFT 23
257#define ASRFSTi_OAFi_MASK (1 << ASRFSTi_OAFi_SHIFT)
258#define ASRFSTi_OAFi (1 << ASRFSTi_OAFi_SHIFT)
259#define ASRFSTi_OUTPUT_FIFO_WIDTH 7
260#define ASRFSTi_OUTPUT_FIFO_SHIFT 12
261#define ASRFSTi_OUTPUT_FIFO_MASK (((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
262#define ASRFSTi_IAEi_SHIFT 11
263#define ASRFSTi_IAEi_MASK (1 << ASRFSTi_IAEi_SHIFT)
264#define ASRFSTi_IAEi (1 << ASRFSTi_IAEi_SHIFT)
265#define ASRFSTi_INPUT_FIFO_WIDTH 7
266#define ASRFSTi_INPUT_FIFO_SHIFT 0
267#define ASRFSTi_INPUT_FIFO_MASK ((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
268
269
270#define ASRMCR1i_IWD_WIDTH 3
271#define ASRMCR1i_IWD_SHIFT 9
272#define ASRMCR1i_IWD_MASK (((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
273#define ASRMCR1i_IWD(v) ((v) << ASRMCR1i_IWD_SHIFT)
274#define ASRMCR1i_IMSB_SHIFT 8
275#define ASRMCR1i_IMSB_MASK (1 << ASRMCR1i_IMSB_SHIFT)
276#define ASRMCR1i_IMSB_MSB (1 << ASRMCR1i_IMSB_SHIFT)
277#define ASRMCR1i_IMSB_LSB (0 << ASRMCR1i_IMSB_SHIFT)
278#define ASRMCR1i_OMSB_SHIFT 2
279#define ASRMCR1i_OMSB_MASK (1 << ASRMCR1i_OMSB_SHIFT)
280#define ASRMCR1i_OMSB_MSB (1 << ASRMCR1i_OMSB_SHIFT)
281#define ASRMCR1i_OMSB_LSB (0 << ASRMCR1i_OMSB_SHIFT)
282#define ASRMCR1i_OSGN_SHIFT 1
283#define ASRMCR1i_OSGN_MASK (1 << ASRMCR1i_OSGN_SHIFT)
284#define ASRMCR1i_OSGN (1 << ASRMCR1i_OSGN_SHIFT)
285#define ASRMCR1i_OW16_SHIFT 0
286#define ASRMCR1i_OW16_MASK (1 << ASRMCR1i_OW16_SHIFT)
287#define ASRMCR1i_OW16(v) ((v) << ASRMCR1i_OW16_SHIFT)
288
289
290enum asrc_pair_index {
291 ASRC_INVALID_PAIR = -1,
292 ASRC_PAIR_A = 0,
293 ASRC_PAIR_B = 1,
294 ASRC_PAIR_C = 2,
295};
296
297#define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1)
298
299enum asrc_inclk {
300 INCLK_NONE = 0x03,
301 INCLK_ESAI_RX = 0x00,
302 INCLK_SSI1_RX = 0x01,
303 INCLK_SSI2_RX = 0x02,
304 INCLK_SSI3_RX = 0x07,
305 INCLK_SPDIF_RX = 0x04,
306 INCLK_MLB_CLK = 0x05,
307 INCLK_PAD = 0x06,
308 INCLK_ESAI_TX = 0x08,
309 INCLK_SSI1_TX = 0x09,
310 INCLK_SSI2_TX = 0x0a,
311 INCLK_SSI3_TX = 0x0b,
312 INCLK_SPDIF_TX = 0x0c,
313 INCLK_ASRCK1_CLK = 0x0f,
314};
315
316enum asrc_outclk {
317 OUTCLK_NONE = 0x03,
318 OUTCLK_ESAI_TX = 0x00,
319 OUTCLK_SSI1_TX = 0x01,
320 OUTCLK_SSI2_TX = 0x02,
321 OUTCLK_SSI3_TX = 0x07,
322 OUTCLK_SPDIF_TX = 0x04,
323 OUTCLK_MLB_CLK = 0x05,
324 OUTCLK_PAD = 0x06,
325 OUTCLK_ESAI_RX = 0x08,
326 OUTCLK_SSI1_RX = 0x09,
327 OUTCLK_SSI2_RX = 0x0a,
328 OUTCLK_SSI3_RX = 0x0b,
329 OUTCLK_SPDIF_RX = 0x0c,
330 OUTCLK_ASRCK1_CLK = 0x0f,
331};
332
333#define ASRC_CLK_MAX_NUM 16
334
335enum asrc_word_width {
336 ASRC_WIDTH_24_BIT = 0,
337 ASRC_WIDTH_16_BIT = 1,
338 ASRC_WIDTH_8_BIT = 2,
339};
340
341struct asrc_config {
342 enum asrc_pair_index pair;
343 unsigned int channel_num;
344 unsigned int buffer_num;
345 unsigned int dma_buffer_size;
346 unsigned int input_sample_rate;
347 unsigned int output_sample_rate;
348 enum asrc_word_width input_word_width;
349 enum asrc_word_width output_word_width;
350 enum asrc_inclk inclk;
351 enum asrc_outclk outclk;
352};
353
354struct asrc_req {
355 unsigned int chn_num;
356 enum asrc_pair_index index;
357};
358
359struct asrc_querybuf {
360 unsigned int buffer_index;
361 unsigned int input_length;
362 unsigned int output_length;
363 unsigned long input_offset;
364 unsigned long output_offset;
365};
366
367struct asrc_convert_buffer {
368 void *input_buffer_vaddr;
369 void *output_buffer_vaddr;
370 unsigned int input_buffer_length;
371 unsigned int output_buffer_length;
372};
373
374struct asrc_status_flags {
375 enum asrc_pair_index index;
376 unsigned int overload_error;
377};
378
379enum asrc_error_status {
380 ASRC_TASK_Q_OVERLOAD = 0x01,
381 ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
382 ASRC_INPUT_TASK_OVERLOAD = 0x04,
383 ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
384 ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
385};
386
387struct dma_block {
388 dma_addr_t dma_paddr;
389 void *dma_vaddr;
390 unsigned int length;
391};
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407struct fsl_asrc_pair {
408 struct fsl_asrc *asrc_priv;
409 struct asrc_config *config;
410 unsigned int error;
411
412 enum asrc_pair_index index;
413 unsigned int channels;
414
415 struct dma_async_tx_descriptor *desc[2];
416 struct dma_chan *dma_chan[2];
417 struct imx_dma_data dma_data;
418 unsigned int pos;
419
420 void *private;
421};
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443struct fsl_asrc {
444 struct snd_dmaengine_dai_dma_data dma_params_rx;
445 struct snd_dmaengine_dai_dma_data dma_params_tx;
446 struct platform_device *pdev;
447 struct regmap *regmap;
448 unsigned long paddr;
449 struct clk *mem_clk;
450 struct clk *ipg_clk;
451 struct clk *spba_clk;
452 struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
453 spinlock_t lock;
454
455 struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM];
456 unsigned int channel_bits;
457 unsigned int channel_avail;
458
459 int asrc_rate;
460 int asrc_width;
461
462 u32 regcache_cfg;
463};
464
465#define DRV_NAME "fsl-asrc-dai"
466extern struct snd_soc_component_driver fsl_asrc_component;
467struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir);
468#endif
469
