linux/sound/soc/intel/haswell/sst-haswell-ipc.h
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   1/*
   2 * Intel SST Haswell/Broadwell IPC Support
   3 *
   4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License version
   8 * 2 as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 */
  16
  17#ifndef __SST_HASWELL_IPC_H
  18#define __SST_HASWELL_IPC_H
  19
  20#include <linux/types.h>
  21#include <linux/kernel.h>
  22#include <linux/platform_device.h>
  23#include <sound/asound.h>
  24
  25#define DRV_NAME "haswell-dai"
  26
  27#define SST_HSW_NO_CHANNELS             4
  28#define SST_HSW_MAX_DX_REGIONS          14
  29#define SST_HSW_DX_CONTEXT_SIZE        (640 * 1024)
  30#define SST_HSW_CHANNELS_ALL            0xffffffff
  31
  32#define SST_HSW_FW_LOG_CONFIG_DWORDS    12
  33#define SST_HSW_GLOBAL_LOG              15
  34
  35/**
  36 * Upfront defined maximum message size that is
  37 * expected by the in/out communication pipes in FW.
  38 */
  39#define SST_HSW_IPC_MAX_PAYLOAD_SIZE    400
  40#define SST_HSW_MAX_INFO_SIZE           64
  41#define SST_HSW_BUILD_HASH_LENGTH       40
  42#define SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE    500
  43#define WAVES_PARAM_COUNT               128
  44#define WAVES_PARAM_LINES               160
  45
  46struct sst_hsw;
  47struct sst_hsw_stream;
  48struct sst_hsw_log_stream;
  49struct sst_pdata;
  50struct sst_module;
  51struct sst_module_runtime;
  52extern struct sst_ops haswell_ops;
  53
  54/* Stream Allocate Path ID */
  55enum sst_hsw_stream_path_id {
  56        SST_HSW_STREAM_PATH_SSP0_OUT = 0,
  57        SST_HSW_STREAM_PATH_SSP0_IN = 1,
  58        SST_HSW_STREAM_PATH_MAX_PATH_ID = 2,
  59};
  60
  61/* Stream Allocate Stream Type */
  62enum sst_hsw_stream_type {
  63        SST_HSW_STREAM_TYPE_RENDER = 0,
  64        SST_HSW_STREAM_TYPE_SYSTEM = 1,
  65        SST_HSW_STREAM_TYPE_CAPTURE = 2,
  66        SST_HSW_STREAM_TYPE_LOOPBACK = 3,
  67        SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4,
  68};
  69
  70/* Stream Allocate Stream Format */
  71enum sst_hsw_stream_format {
  72        SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0,
  73        SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1,
  74        SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2,
  75        SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3,
  76};
  77
  78/* Device ID */
  79enum sst_hsw_device_id {
  80        SST_HSW_DEVICE_SSP_0   = 0,
  81        SST_HSW_DEVICE_SSP_1   = 1,
  82};
  83
  84/* Device Master Clock Frequency */
  85enum sst_hsw_device_mclk {
  86        SST_HSW_DEVICE_MCLK_OFF         = 0,
  87        SST_HSW_DEVICE_MCLK_FREQ_6_MHZ  = 1,
  88        SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2,
  89        SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3,
  90};
  91
  92/* Device Clock Master */
  93enum sst_hsw_device_mode {
  94        SST_HSW_DEVICE_CLOCK_SLAVE   = 0,
  95        SST_HSW_DEVICE_CLOCK_MASTER  = 1,
  96        SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2,
  97};
  98
  99/* DX Power State */
 100enum sst_hsw_dx_state {
 101        SST_HSW_DX_STATE_D0     = 0,
 102        SST_HSW_DX_STATE_D1     = 1,
 103        SST_HSW_DX_STATE_D3     = 3,
 104        SST_HSW_DX_STATE_MAX    = 3,
 105};
 106
 107/* Audio stream stage IDs */
 108enum sst_hsw_fx_stage_id {
 109        SST_HSW_STAGE_ID_WAVES = 0,
 110        SST_HSW_STAGE_ID_DTS   = 1,
 111        SST_HSW_STAGE_ID_DOLBY = 2,
 112        SST_HSW_STAGE_ID_BOOST = 3,
 113        SST_HSW_STAGE_ID_MAX_FX_ID
 114};
 115
 116/* DX State Type */
 117enum sst_hsw_dx_type {
 118        SST_HSW_DX_TYPE_FW_IMAGE = 0,
 119        SST_HSW_DX_TYPE_MEMORY_DUMP = 1
 120};
 121
 122/* Volume Curve Type*/
 123enum sst_hsw_volume_curve {
 124        SST_HSW_VOLUME_CURVE_NONE = 0,
 125        SST_HSW_VOLUME_CURVE_FADE = 1
 126};
 127
 128/* Sample ordering */
 129enum sst_hsw_interleaving {
 130        SST_HSW_INTERLEAVING_PER_CHANNEL = 0,
 131        SST_HSW_INTERLEAVING_PER_SAMPLE  = 1,
 132};
 133
 134/* Channel indices */
 135enum sst_hsw_channel_index {
 136        SST_HSW_CHANNEL_LEFT            = 0,
 137        SST_HSW_CHANNEL_CENTER          = 1,
 138        SST_HSW_CHANNEL_RIGHT           = 2,
 139        SST_HSW_CHANNEL_LEFT_SURROUND   = 3,
 140        SST_HSW_CHANNEL_CENTER_SURROUND = 3,
 141        SST_HSW_CHANNEL_RIGHT_SURROUND  = 4,
 142        SST_HSW_CHANNEL_LFE             = 7,
 143        SST_HSW_CHANNEL_INVALID         = 0xF,
 144};
 145
 146/* List of supported channel maps. */
 147enum sst_hsw_channel_config {
 148        SST_HSW_CHANNEL_CONFIG_MONO      = 0, /* mono only. */
 149        SST_HSW_CHANNEL_CONFIG_STEREO    = 1, /* L & R. */
 150        SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */
 151        SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */
 152        SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */
 153        SST_HSW_CHANNEL_CONFIG_QUATRO    = 5, /* L, R, Ls & Rs; PCM only. */
 154        SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */
 155        SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */
 156        SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */
 157        SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */
 158        SST_HSW_CHANNEL_CONFIG_INVALID,
 159};
 160
 161/* List of supported bit depths. */
 162enum sst_hsw_bitdepth {
 163        SST_HSW_DEPTH_8BIT  = 8,
 164        SST_HSW_DEPTH_16BIT = 16,
 165        SST_HSW_DEPTH_24BIT = 24, /* Default. */
 166        SST_HSW_DEPTH_32BIT = 32,
 167        SST_HSW_DEPTH_INVALID = 33,
 168};
 169
 170enum sst_hsw_module_id {
 171        SST_HSW_MODULE_BASE_FW = 0x0,
 172        SST_HSW_MODULE_MP3     = 0x1,
 173        SST_HSW_MODULE_AAC_5_1 = 0x2,
 174        SST_HSW_MODULE_AAC_2_0 = 0x3,
 175        SST_HSW_MODULE_SRC     = 0x4,
 176        SST_HSW_MODULE_WAVES   = 0x5,
 177        SST_HSW_MODULE_DOLBY   = 0x6,
 178        SST_HSW_MODULE_BOOST   = 0x7,
 179        SST_HSW_MODULE_LPAL    = 0x8,
 180        SST_HSW_MODULE_DTS     = 0x9,
 181        SST_HSW_MODULE_PCM_CAPTURE = 0xA,
 182        SST_HSW_MODULE_PCM_SYSTEM = 0xB,
 183        SST_HSW_MODULE_PCM_REFERENCE = 0xC,
 184        SST_HSW_MODULE_PCM = 0xD,
 185        SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE,
 186        SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF,
 187        SST_HSW_MAX_MODULE_ID,
 188};
 189
 190enum sst_hsw_performance_action {
 191        SST_HSW_PERF_START = 0,
 192        SST_HSW_PERF_STOP = 1,
 193};
 194
 195struct sst_hsw_transfer_info {
 196        uint32_t destination;       /* destination address */
 197        uint32_t reverse:1;         /* if 1 data flows from destination */
 198        uint32_t size:31;           /* transfer size in bytes.*/
 199        uint16_t first_page_offset; /* offset to data in the first page. */
 200        uint8_t  packed_pages;   /* page addresses. Each occupies 20 bits */
 201} __attribute__((packed));
 202
 203struct sst_hsw_transfer_list {
 204        uint32_t transfers_count;
 205        struct sst_hsw_transfer_info transfers;
 206} __attribute__((packed));
 207
 208struct sst_hsw_transfer_parameter {
 209        uint32_t parameter_id;
 210        uint32_t data_size;
 211        union {
 212                uint8_t data[1];
 213                struct sst_hsw_transfer_list transfer_list;
 214        };
 215} __attribute__((packed));
 216
 217/* SST firmware module info */
 218struct sst_hsw_module_info {
 219        u8 name[SST_HSW_MAX_INFO_SIZE];
 220        u8 version[SST_HSW_MAX_INFO_SIZE];
 221} __attribute__((packed));
 222
 223/* Module entry point */
 224struct sst_hsw_module_entry {
 225        enum sst_hsw_module_id module_id;
 226        u32 entry_point;
 227} __attribute__((packed));
 228
 229/* Module map - alignement matches DSP */
 230struct sst_hsw_module_map {
 231        u8 module_entries_count;
 232        struct sst_hsw_module_entry module_entries[1];
 233} __attribute__((packed));
 234
 235struct sst_hsw_memory_info {
 236        u32 offset;
 237        u32 size;
 238} __attribute__((packed));
 239
 240struct sst_hsw_fx_enable {
 241        struct sst_hsw_module_map module_map;
 242        struct sst_hsw_memory_info persistent_mem;
 243} __attribute__((packed));
 244
 245struct sst_hsw_ipc_module_config {
 246        struct sst_hsw_module_map map;
 247        struct sst_hsw_memory_info persistent_mem;
 248        struct sst_hsw_memory_info scratch_mem;
 249} __attribute__((packed));
 250
 251struct sst_hsw_get_fx_param {
 252        u32 parameter_id;
 253        u32 param_size;
 254} __attribute__((packed));
 255
 256struct sst_hsw_perf_action {
 257        u32 action;
 258} __attribute__((packed));
 259
 260struct sst_hsw_perf_data {
 261        u64 timestamp;
 262        u64 cycles;
 263        u64 datatime;
 264} __attribute__((packed));
 265
 266/* FW version */
 267struct sst_hsw_ipc_fw_version {
 268        u8 build;
 269        u8 minor;
 270        u8 major;
 271        u8 type;
 272        u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH];
 273        u32 fw_log_providers_hash;
 274} __attribute__((packed));
 275
 276/* Stream ring info */
 277struct sst_hsw_ipc_stream_ring {
 278        u32 ring_pt_address;
 279        u32 num_pages;
 280        u32 ring_size;
 281        u32 ring_offset;
 282        u32 ring_first_pfn;
 283} __attribute__((packed));
 284
 285/* Debug Dump Log Enable Request */
 286struct sst_hsw_ipc_debug_log_enable_req {
 287        struct sst_hsw_ipc_stream_ring ringinfo;
 288        u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
 289} __attribute__((packed));
 290
 291/* Debug Dump Log Reply */
 292struct sst_hsw_ipc_debug_log_reply {
 293        u32 log_buffer_begining;
 294        u32 log_buffer_size;
 295} __attribute__((packed));
 296
 297/* Stream glitch position */
 298struct sst_hsw_ipc_stream_glitch_position {
 299        u32 glitch_type;
 300        u32 present_pos;
 301        u32 write_pos;
 302} __attribute__((packed));
 303
 304/* Stream get position */
 305struct sst_hsw_ipc_stream_get_position {
 306        u32 position;
 307        u32 fw_cycle_count;
 308} __attribute__((packed));
 309
 310/* Stream set position */
 311struct sst_hsw_ipc_stream_set_position {
 312        u32 position;
 313        u32 end_of_buffer;
 314} __attribute__((packed));
 315
 316/* Stream Free Request */
 317struct sst_hsw_ipc_stream_free_req {
 318        u8 stream_id;
 319        u8 reserved[3];
 320} __attribute__((packed));
 321
 322/* Set Volume Request */
 323struct sst_hsw_ipc_volume_req {
 324        u32 channel;
 325        u32 target_volume;
 326        u64 curve_duration;
 327        u32 curve_type;
 328} __attribute__((packed));
 329
 330/* Device Configuration Request */
 331struct sst_hsw_ipc_device_config_req {
 332        u32 ssp_interface;
 333        u32 clock_frequency;
 334        u32 mode;
 335        u16 clock_divider;
 336        u8 channels;
 337        u8 reserved;
 338} __attribute__((packed));
 339
 340/* Audio Data formats */
 341struct sst_hsw_audio_data_format_ipc {
 342        u32 frequency;
 343        u32 bitdepth;
 344        u32 map;
 345        u32 config;
 346        u32 style;
 347        u8 ch_num;
 348        u8 valid_bit;
 349        u8 reserved[2];
 350} __attribute__((packed));
 351
 352/* Stream Allocate Request */
 353struct sst_hsw_ipc_stream_alloc_req {
 354        u8 path_id;
 355        u8 stream_type;
 356        u8 format_id;
 357        u8 reserved;
 358        struct sst_hsw_audio_data_format_ipc format;
 359        struct sst_hsw_ipc_stream_ring ringinfo;
 360        struct sst_hsw_module_map map;
 361        struct sst_hsw_memory_info persistent_mem;
 362        struct sst_hsw_memory_info scratch_mem;
 363        u32 number_of_notifications;
 364} __attribute__((packed));
 365
 366/* Stream Allocate Reply */
 367struct sst_hsw_ipc_stream_alloc_reply {
 368        u32 stream_hw_id;
 369        u32 mixer_hw_id; // returns rate ????
 370        u32 read_position_register_address;
 371        u32 presentation_position_register_address;
 372        u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
 373        u32 volume_register_address[SST_HSW_NO_CHANNELS];
 374} __attribute__((packed));
 375
 376/* Get Mixer Stream Info */
 377struct sst_hsw_ipc_stream_info_reply {
 378        u32 mixer_hw_id;
 379        u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
 380        u32 volume_register_address[SST_HSW_NO_CHANNELS];
 381} __attribute__((packed));
 382
 383/* DX State Request */
 384struct sst_hsw_ipc_dx_req {
 385        u8 state;
 386        u8 reserved[3];
 387} __attribute__((packed));
 388
 389/* DX State Reply Memory Info Item */
 390struct sst_hsw_ipc_dx_memory_item {
 391        u32 offset;
 392        u32 size;
 393        u32 source;
 394} __attribute__((packed));
 395
 396/* DX State Reply */
 397struct sst_hsw_ipc_dx_reply {
 398        u32 entries_no;
 399        struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS];
 400} __attribute__((packed));
 401
 402struct sst_hsw_ipc_fw_version;
 403
 404/* SST Init & Free */
 405struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length,
 406        u32 fw_offset);
 407void sst_hsw_free(struct sst_hsw *hsw);
 408int sst_hsw_fw_get_version(struct sst_hsw *hsw,
 409        struct sst_hsw_ipc_fw_version *version);
 410u32 create_channel_map(enum sst_hsw_channel_config config);
 411
 412/* Stream Mixer Controls - */
 413int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
 414        struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume);
 415int sst_hsw_stream_get_volume(struct sst_hsw *hsw,
 416        struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume);
 417
 418/* Global Mixer Controls - */
 419int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 420        u32 volume);
 421int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 422        u32 *volume);
 423
 424/* Stream API */
 425struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
 426        u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data),
 427        void *data);
 428
 429int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
 430
 431/* Stream Configuration */
 432int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 433        enum sst_hsw_stream_path_id path_id,
 434        enum sst_hsw_stream_type stream_type,
 435        enum sst_hsw_stream_format format_id);
 436
 437int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 438        u32 ring_pt_address, u32 num_pages,
 439        u32 ring_size, u32 ring_offset, u32 ring_first_pfn);
 440
 441int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
 442
 443int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 444        u32 bits);
 445int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 446        int rate);
 447int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 448        enum sst_hsw_bitdepth bits);
 449int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
 450        struct sst_hsw_stream *stream, int channels);
 451int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
 452        struct sst_hsw_stream *stream, u32 map,
 453        enum sst_hsw_channel_config config);
 454int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 455        enum sst_hsw_interleaving style);
 456int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
 457        struct sst_hsw_stream *stream, struct sst_module_runtime *runtime);
 458int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
 459        struct sst_hsw_stream *stream, u32 offset, u32 size);
 460int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
 461        struct sst_hsw_stream *stream, u32 offset, u32 size);
 462snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
 463        struct sst_hsw_stream *stream);
 464void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
 465        struct sst_hsw_stream *stream, snd_pcm_uframes_t val);
 466bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
 467        struct sst_hsw_stream *stream);
 468void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
 469        struct sst_hsw_stream *stream, bool val);
 470int sst_hsw_mixer_get_info(struct sst_hsw *hsw);
 471
 472/* Stream ALSA trigger operations */
 473int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 474        int wait);
 475int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 476        int wait);
 477int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
 478
 479/* Stream pointer positions */
 480int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw,
 481        struct sst_hsw_stream *stream, u32 *position);
 482int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw,
 483        struct sst_hsw_stream *stream, u32 *position);
 484u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
 485        struct sst_hsw_stream *stream);
 486u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
 487        struct sst_hsw_stream *stream);
 488
 489/* HW port config */
 490int sst_hsw_device_set_config(struct sst_hsw *hsw,
 491        enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
 492        enum sst_hsw_device_mode mode, u32 clock_divider);
 493
 494/* DX Config */
 495int sst_hsw_dx_set_state(struct sst_hsw *hsw,
 496        enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx);
 497
 498/* init */
 499int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata);
 500void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata);
 501struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw);
 502
 503/* fw module function */
 504void sst_hsw_init_module_state(struct sst_hsw *hsw);
 505bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id);
 506bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id);
 507void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id);
 508void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id);
 509bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id);
 510void sst_hsw_reset_param_buf(struct sst_hsw *hsw);
 511int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf);
 512int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf);
 513int sst_hsw_launch_param_buf(struct sst_hsw *hsw);
 514
 515int sst_hsw_module_load(struct sst_hsw *hsw,
 516        u32 module_id, u32 instance_id, char *name);
 517int sst_hsw_module_enable(struct sst_hsw *hsw,
 518        u32 module_id, u32 instance_id);
 519int sst_hsw_module_disable(struct sst_hsw *hsw,
 520        u32 module_id, u32 instance_id);
 521int sst_hsw_module_set_param(struct sst_hsw *hsw,
 522        u32 module_id, u32 instance_id, u32 parameter_id,
 523        u32 param_size, char *param);
 524
 525/* runtime module management */
 526struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
 527        int mod_id, int offset);
 528void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime);
 529
 530/* PM */
 531int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw);
 532int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw);
 533int sst_hsw_dsp_load(struct sst_hsw *hsw);
 534int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw);
 535
 536#endif
 537