LXR linux/sound/soc/intel/skylake/cnl-sst-dsp.h

   1/*
   2 * Cannonlake SST DSP Support
   3 *
   4 * Copyright (C) 2016-17, Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as version 2, as
   8 * published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * General Public License for more details.
  14 */
  15
  16#ifndef __CNL_SST_DSP_H__
  17#define __CNL_SST_DSP_H__
  18
  19struct sst_dsp;
  20struct skl_sst;
  21struct sst_dsp_device;
  22struct sst_generic_ipc;
  23
  24/* Intel HD Audio General DSP Registers */
  25#define CNL_ADSP_GEN_BASE               0x0
  26#define CNL_ADSP_REG_ADSPCS             (CNL_ADSP_GEN_BASE + 0x04)
  27#define CNL_ADSP_REG_ADSPIC             (CNL_ADSP_GEN_BASE + 0x08)
  28#define CNL_ADSP_REG_ADSPIS             (CNL_ADSP_GEN_BASE + 0x0c)
  29
  30/* Intel HD Audio Inter-Processor Communication Registers */
  31#define CNL_ADSP_IPC_BASE               0xc0
  32#define CNL_ADSP_REG_HIPCTDR            (CNL_ADSP_IPC_BASE + 0x00)
  33#define CNL_ADSP_REG_HIPCTDA            (CNL_ADSP_IPC_BASE + 0x04)
  34#define CNL_ADSP_REG_HIPCTDD            (CNL_ADSP_IPC_BASE + 0x08)
  35#define CNL_ADSP_REG_HIPCIDR            (CNL_ADSP_IPC_BASE + 0x10)
  36#define CNL_ADSP_REG_HIPCIDA            (CNL_ADSP_IPC_BASE + 0x14)
  37#define CNL_ADSP_REG_HIPCIDD            (CNL_ADSP_IPC_BASE + 0x18)
  38#define CNL_ADSP_REG_HIPCCTL            (CNL_ADSP_IPC_BASE + 0x28)
  39
  40/* HIPCTDR */
  41#define CNL_ADSP_REG_HIPCTDR_BUSY       BIT(31)
  42
  43/* HIPCTDA */
  44#define CNL_ADSP_REG_HIPCTDA_DONE       BIT(31)
  45
  46/* HIPCIDR */
  47#define CNL_ADSP_REG_HIPCIDR_BUSY       BIT(31)
  48
  49/* HIPCIDA */
  50#define CNL_ADSP_REG_HIPCIDA_DONE       BIT(31)
  51
  52/* CNL HIPCCTL */
  53#define CNL_ADSP_REG_HIPCCTL_DONE       BIT(1)
  54#define CNL_ADSP_REG_HIPCCTL_BUSY       BIT(0)
  55
  56/* CNL HIPCT */
  57#define CNL_ADSP_REG_HIPCT_BUSY         BIT(31)
  58
  59/* Intel HD Audio SRAM Window 1 */
  60#define CNL_ADSP_SRAM1_BASE             0xa0000
  61
  62#define CNL_ADSP_MMIO_LEN               0x10000
  63
  64#define CNL_ADSP_W0_STAT_SZ             0x1000
  65
  66#define CNL_ADSP_W0_UP_SZ               0x1000
  67
  68#define CNL_ADSP_W1_SZ                  0x1000
  69
  70#define CNL_FW_STS_MASK                 0xf
  71
  72#define CNL_ADSPIC_IPC                  0x1
  73#define CNL_ADSPIS_IPC                  0x1
  74
  75#define CNL_DSP_CORES           4
  76#define CNL_DSP_CORES_MASK      ((1 << CNL_DSP_CORES) - 1)
  77
  78/* core reset - asserted high */
  79#define CNL_ADSPCS_CRST_SHIFT   0
  80#define CNL_ADSPCS_CRST(x)      (x << CNL_ADSPCS_CRST_SHIFT)
  81
  82/* core run/stall - when set to 1 core is stalled */
  83#define CNL_ADSPCS_CSTALL_SHIFT 8
  84#define CNL_ADSPCS_CSTALL(x)    (x << CNL_ADSPCS_CSTALL_SHIFT)
  85
  86/* set power active - when set to 1 turn core on */
  87#define CNL_ADSPCS_SPA_SHIFT    16
  88#define CNL_ADSPCS_SPA(x)       (x << CNL_ADSPCS_SPA_SHIFT)
  89
  90/* current power active - power status of cores, set by hardware */
  91#define CNL_ADSPCS_CPA_SHIFT    24
  92#define CNL_ADSPCS_CPA(x)       (x << CNL_ADSPCS_CPA_SHIFT)
  93
  94int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core);
  95int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core);
  96irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id);
  97void cnl_dsp_free(struct sst_dsp *dsp);
  98
  99void cnl_ipc_int_enable(struct sst_dsp *ctx);
 100void cnl_ipc_int_disable(struct sst_dsp *ctx);
 101void cnl_ipc_op_int_enable(struct sst_dsp *ctx);
 102void cnl_ipc_op_int_disable(struct sst_dsp *ctx);
 103bool cnl_ipc_int_status(struct sst_dsp *ctx);
 104void cnl_ipc_free(struct sst_generic_ipc *ipc);
 105
 106int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 107                     const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 108                     struct skl_sst **dsp);
 109int cnl_sst_init_fw(struct device *dev, struct skl_sst *ctx);
 110void cnl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
 111
 112#endif /*__CNL_SST_DSP_H__*/
 113