LXR linux/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c

   1/*
   2 * Ptrace test for TAR, PPR, DSCR registers in the TM Suspend context
   3 *
   4 * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version
   9 * 2 of the License, or (at your option) any later version.
  10 */
  11#include "ptrace.h"
  12#include "tm.h"
  13#include "ptrace-tar.h"
  14
  15int shm_id;
  16int *cptr, *pptr;
  17
  18__attribute__((used)) void wait_parent(void)
  19{
  20        cptr[2] = 1;
  21        while (!cptr[1])
  22                asm volatile("" : : : "memory");
  23}
  24
  25void tm_spd_tar(void)
  26{
  27        unsigned long result, texasr;
  28        unsigned long regs[3];
  29        int ret;
  30
  31        cptr = (int *)shmat(shm_id, NULL, 0);
  32
  33trans:
  34        cptr[2] = 0;
  35        asm __volatile__(
  36                "li     4, %[tar_1];"
  37                "mtspr %[sprn_tar],  4;"        /* TAR_1 */
  38                "li     4, %[dscr_1];"
  39                "mtspr %[sprn_dscr], 4;"        /* DSCR_1 */
  40                "or     31,31,31;"              /* PPR_1*/
  41
  42                "1: ;"
  43                "tbegin.;"
  44                "beq 2f;"
  45
  46                "li     4, %[tar_2];"
  47                "mtspr %[sprn_tar],  4;"        /* TAR_2 */
  48                "li     4, %[dscr_2];"
  49                "mtspr %[sprn_dscr], 4;"        /* DSCR_2 */
  50                "or     1,1,1;"                 /* PPR_2 */
  51
  52                "tsuspend.;"
  53                "li     4, %[tar_3];"
  54                "mtspr %[sprn_tar],  4;"        /* TAR_3 */
  55                "li     4, %[dscr_3];"
  56                "mtspr %[sprn_dscr], 4;"        /* DSCR_3 */
  57                "or     6,6,6;"                 /* PPR_3 */
  58                "bl wait_parent;"
  59                "tresume.;"
  60
  61                "tend.;"
  62                "li 0, 0;"
  63                "ori %[res], 0, 0;"
  64                "b 3f;"
  65
  66                /* Transaction abort handler */
  67                "2: ;"
  68                "li 0, 1;"
  69                "ori %[res], 0, 0;"
  70                "mfspr %[texasr], %[sprn_texasr];"
  71
  72                "3: ;"
  73
  74                : [res] "=r" (result), [texasr] "=r" (texasr)
  75                : [val] "r" (cptr[1]), [sprn_dscr]"i"(SPRN_DSCR),
  76                [sprn_tar]"i"(SPRN_TAR), [sprn_ppr]"i"(SPRN_PPR),
  77                [sprn_texasr]"i"(SPRN_TEXASR), [tar_1]"i"(TAR_1),
  78                [dscr_1]"i"(DSCR_1), [tar_2]"i"(TAR_2), [dscr_2]"i"(DSCR_2),
  79                [tar_3]"i"(TAR_3), [dscr_3]"i"(DSCR_3)
  80                : "memory", "r0", "r1", "r3", "r4", "r5", "r6"
  81                );
  82
  83        /* TM failed, analyse */
  84        if (result) {
  85                if (!cptr[0])
  86                        goto trans;
  87
  88                regs[0] = mfspr(SPRN_TAR);
  89                regs[1] = mfspr(SPRN_PPR);
  90                regs[2] = mfspr(SPRN_DSCR);
  91
  92                shmdt(&cptr);
  93                printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n",
  94                                user_read, regs[0], regs[1], regs[2]);
  95
  96                ret = validate_tar_registers(regs, TAR_4, PPR_4, DSCR_4);
  97                if (ret)
  98                        exit(1);
  99                exit(0);
 100        }
 101        shmdt(&cptr);
 102        exit(1);
 103}
 104
 105int trace_tm_spd_tar(pid_t child)
 106{
 107        unsigned long regs[3];
 108
 109        FAIL_IF(start_trace(child));
 110        FAIL_IF(show_tar_registers(child, regs));
 111        printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n",
 112                        ptrace_read_running, regs[0], regs[1], regs[2]);
 113
 114        FAIL_IF(validate_tar_registers(regs, TAR_3, PPR_3, DSCR_3));
 115        FAIL_IF(show_tm_checkpointed_state(child, regs));
 116        printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n",
 117                        ptrace_read_ckpt, regs[0], regs[1], regs[2]);
 118
 119        FAIL_IF(validate_tar_registers(regs, TAR_1, PPR_1, DSCR_1));
 120        FAIL_IF(write_ckpt_tar_registers(child, TAR_4, PPR_4, DSCR_4));
 121        printf("%-30s TAR: %u PPR: %lx DSCR: %u\n",
 122                        ptrace_write_ckpt, TAR_4, PPR_4, DSCR_4);
 123
 124        pptr[0] = 1;
 125        pptr[1] = 1;
 126        FAIL_IF(stop_trace(child));
 127        return TEST_PASS;
 128}
 129
 130int ptrace_tm_spd_tar(void)
 131{
 132        pid_t pid;
 133        int ret, status;
 134
 135        SKIP_IF(!have_htm());
 136        shm_id = shmget(IPC_PRIVATE, sizeof(int) * 3, 0777|IPC_CREAT);
 137        pid = fork();
 138        if (pid == 0)
 139                tm_spd_tar();
 140
 141        pptr = (int *)shmat(shm_id, NULL, 0);
 142        pptr[0] = 0;
 143        pptr[1] = 0;
 144
 145        if (pid) {
 146                while (!pptr[2])
 147                        asm volatile("" : : : "memory");
 148                ret = trace_tm_spd_tar(pid);
 149                if (ret) {
 150                        kill(pid, SIGTERM);
 151                        shmdt(&pptr);
 152                        shmctl(shm_id, IPC_RMID, NULL);
 153                        return TEST_FAIL;
 154                }
 155
 156                shmdt(&pptr);
 157
 158                ret = wait(&status);
 159                shmctl(shm_id, IPC_RMID, NULL);
 160                if (ret != pid) {
 161                        printf("Child's exit status not captured\n");
 162                        return TEST_FAIL;
 163                }
 164
 165                return (WIFEXITED(status) && WEXITSTATUS(status)) ? TEST_FAIL :
 166                        TEST_PASS;
 167        }
 168        return TEST_PASS;
 169}
 170
 171int main(int argc, char *argv[])
 172{
 173        return test_harness(ptrace_tm_spd_tar, "ptrace_tm_spd_tar");
 174}
 175