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15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/irq.h>
21#include <linux/gpio.h>
22#include <linux/platform_device.h>
23#include <linux/mfd/mc13783.h>
24#include <linux/spi/spi.h>
25#include <linux/spi/l4f00242t03.h>
26#include <linux/regulator/machine.h>
27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/memory.h>
34#include <asm/mach/map.h>
35
36#include "3ds_debugboard.h"
37#include "common.h"
38#include "devices-imx31.h"
39#include "ehci.h"
40#include "hardware.h"
41#include "iomux-mx3.h"
42#include "ulpi.h"
43
44static int mx31_3ds_pins[] = {
45
46 MX31_PIN_CTS1__CTS1,
47 MX31_PIN_RTS1__RTS1,
48 MX31_PIN_TXD1__TXD1,
49 MX31_PIN_RXD1__RXD1,
50 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
51
52 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
53 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
54
55 MX31_PIN_CSPI2_SCLK__SCLK,
56 MX31_PIN_CSPI2_MOSI__MOSI,
57 MX31_PIN_CSPI2_MISO__MISO,
58 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
59 MX31_PIN_CSPI2_SS0__SS0,
60 MX31_PIN_CSPI2_SS2__SS2,
61
62 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
63
64 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
65
66 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
67 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
68 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
69 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
70 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
71 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
72 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
73 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
74 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
75 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
76 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
77 MX31_PIN_USBOTG_STP__USBOTG_STP,
78
79 MX31_PIN_KEY_ROW0_KEY_ROW0,
80 MX31_PIN_KEY_ROW1_KEY_ROW1,
81 MX31_PIN_KEY_ROW2_KEY_ROW2,
82 MX31_PIN_KEY_COL0_KEY_COL0,
83 MX31_PIN_KEY_COL1_KEY_COL1,
84 MX31_PIN_KEY_COL2_KEY_COL2,
85 MX31_PIN_KEY_COL3_KEY_COL3,
86
87 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
88 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
89 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
90 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
91 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
92 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
93 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
94 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
95 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
96 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
97 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
98 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
99
100 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
101
102 MX31_PIN_I2C_CLK__I2C1_SCL,
103 MX31_PIN_I2C_DAT__I2C1_SDA,
104
105 MX31_PIN_SD1_DATA3__SD1_DATA3,
106 MX31_PIN_SD1_DATA2__SD1_DATA2,
107 MX31_PIN_SD1_DATA1__SD1_DATA1,
108 MX31_PIN_SD1_DATA0__SD1_DATA0,
109 MX31_PIN_SD1_CLK__SD1_CLK,
110 MX31_PIN_SD1_CMD__SD1_CMD,
111 MX31_PIN_GPIO3_1__GPIO3_1,
112 MX31_PIN_GPIO3_0__GPIO3_0,
113
114 MX31_PIN_LD0__LD0,
115 MX31_PIN_LD1__LD1,
116 MX31_PIN_LD2__LD2,
117 MX31_PIN_LD3__LD3,
118 MX31_PIN_LD4__LD4,
119 MX31_PIN_LD5__LD5,
120 MX31_PIN_LD6__LD6,
121 MX31_PIN_LD7__LD7,
122 MX31_PIN_LD8__LD8,
123 MX31_PIN_LD9__LD9,
124 MX31_PIN_LD10__LD10,
125 MX31_PIN_LD11__LD11,
126 MX31_PIN_LD12__LD12,
127 MX31_PIN_LD13__LD13,
128 MX31_PIN_LD14__LD14,
129 MX31_PIN_LD15__LD15,
130 MX31_PIN_LD16__LD16,
131 MX31_PIN_LD17__LD17,
132 MX31_PIN_VSYNC3__VSYNC3,
133 MX31_PIN_HSYNC__HSYNC,
134 MX31_PIN_FPSHIFT__FPSHIFT,
135 MX31_PIN_CONTRAST__CONTRAST,
136
137 MX31_PIN_STXD4__STXD4,
138 MX31_PIN_SRXD4__SRXD4,
139 MX31_PIN_SCK4__SCK4,
140 MX31_PIN_SFS4__SFS4,
141};
142
143
144
145
146static const struct fb_videomode fb_modedb[] = {
147 {
148 .name = "Epson-VGA",
149 .refresh = 60,
150 .xres = 480,
151 .yres = 640,
152 .pixclock = 41701,
153 .left_margin = 20,
154 .right_margin = 41,
155 .upper_margin = 10,
156 .lower_margin = 5,
157 .hsync_len = 20,
158 .vsync_len = 10,
159 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
160 .vmode = FB_VMODE_NONINTERLACED,
161 .flag = 0,
162 },
163};
164
165static struct mx3fb_platform_data mx3fb_pdata __initdata = {
166 .name = "Epson-VGA",
167 .mode = fb_modedb,
168 .num_modes = ARRAY_SIZE(fb_modedb),
169};
170
171
172static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
173 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
174 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
175};
176
177
178
179
180#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
181#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
182
183static struct gpio mx31_3ds_sdhc1_gpios[] = {
184 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
185 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
186};
187
188static int mx31_3ds_sdhc1_init(struct device *dev,
189 irq_handler_t detect_irq,
190 void *data)
191{
192 int ret;
193
194 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
195 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
196 if (ret) {
197 pr_warn("Unable to request the SD/MMC GPIOs.\n");
198 return ret;
199 }
200
201 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
202 detect_irq,
203 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
204 "sdhc1-detect", data);
205 if (ret) {
206 pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
207 goto gpio_free;
208 }
209
210 return 0;
211
212gpio_free:
213 gpio_free_array(mx31_3ds_sdhc1_gpios,
214 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
215 return ret;
216}
217
218static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
219{
220 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
221 gpio_free_array(mx31_3ds_sdhc1_gpios,
222 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
223}
224
225static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
226{
227
228
229
230
231
232
233
234
235 if (vdd > 7)
236 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
237 else
238 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
239}
240
241static struct imxmmc_platform_data sdhc1_pdata = {
242 .init = mx31_3ds_sdhc1_init,
243 .exit = mx31_3ds_sdhc1_exit,
244 .setpower = mx31_3ds_sdhc1_setpower,
245};
246
247
248
249
250
251static const uint32_t mx31_3ds_keymap[] = {
252 KEY(0, 0, KEY_UP),
253 KEY(0, 1, KEY_DOWN),
254 KEY(1, 0, KEY_RIGHT),
255 KEY(1, 1, KEY_LEFT),
256 KEY(1, 2, KEY_ENTER),
257 KEY(2, 0, KEY_F6),
258 KEY(2, 1, KEY_F8),
259 KEY(2, 2, KEY_F9),
260 KEY(2, 3, KEY_F10),
261};
262
263static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
264 .keymap = mx31_3ds_keymap,
265 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
266};
267
268
269static struct regulator_init_data pwgtx_init = {
270 .constraints = {
271 .boot_on = 1,
272 .always_on = 1,
273 },
274};
275
276static struct regulator_init_data gpo_init = {
277 .constraints = {
278 .boot_on = 1,
279 .always_on = 1,
280 }
281};
282
283static struct regulator_consumer_supply vmmc2_consumers[] = {
284 REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"),
285};
286
287static struct regulator_init_data vmmc2_init = {
288 .constraints = {
289 .min_uV = 3000000,
290 .max_uV = 3000000,
291 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
292 REGULATOR_CHANGE_STATUS,
293 },
294 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
295 .consumer_supplies = vmmc2_consumers,
296};
297
298static struct regulator_consumer_supply vmmc1_consumers[] = {
299 REGULATOR_SUPPLY("vcore", "spi0.0"),
300};
301
302static struct regulator_init_data vmmc1_init = {
303 .constraints = {
304 .min_uV = 2800000,
305 .max_uV = 2800000,
306 .apply_uV = 1,
307 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
308 REGULATOR_CHANGE_STATUS,
309 },
310 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
311 .consumer_supplies = vmmc1_consumers,
312};
313
314static struct regulator_consumer_supply vgen_consumers[] = {
315 REGULATOR_SUPPLY("vdd", "spi0.0"),
316};
317
318static struct regulator_init_data vgen_init = {
319 .constraints = {
320 .min_uV = 1800000,
321 .max_uV = 1800000,
322 .apply_uV = 1,
323 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
324 REGULATOR_CHANGE_STATUS,
325 },
326 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
327 .consumer_supplies = vgen_consumers,
328};
329
330static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
331 {
332 .id = MC13783_REG_PWGT1SPI,
333 .init_data = &pwgtx_init,
334 }, {
335 .id = MC13783_REG_PWGT2SPI,
336 .init_data = &pwgtx_init,
337 }, {
338
339 .id = MC13783_REG_GPO1,
340 .init_data = &gpo_init,
341 }, {
342 .id = MC13783_REG_GPO3,
343 .init_data = &gpo_init,
344 }, {
345 .id = MC13783_REG_VMMC2,
346 .init_data = &vmmc2_init,
347 }, {
348 .id = MC13783_REG_VMMC1,
349 .init_data = &vmmc1_init,
350 }, {
351 .id = MC13783_REG_VGEN,
352 .init_data = &vgen_init,
353 },
354};
355
356
357static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
358 .dac_ssi_port = MC13783_SSI1_PORT,
359 .adc_ssi_port = MC13783_SSI1_PORT,
360};
361
362static struct mc13xxx_platform_data mc13783_pdata = {
363 .regulators = {
364 .regulators = mx31_3ds_regulators,
365 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
366 },
367 .codec = &mx31_3ds_codec,
368 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
369
370};
371
372static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
373 .flags = IMX_SSI_DMA | IMX_SSI_NET,
374};
375
376
377static const struct spi_imx_master spi0_pdata __initconst = {
378 .num_chipselect = 3,
379};
380
381static const struct spi_imx_master spi1_pdata __initconst = {
382 .num_chipselect = 3,
383};
384
385static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
386 {
387 .modalias = "mc13783",
388 .max_speed_hz = 1000000,
389 .bus_num = 1,
390 .chip_select = 2,
391 .platform_data = &mc13783_pdata,
392
393 .mode = SPI_CS_HIGH,
394 }, {
395 .modalias = "l4f00242t03",
396 .max_speed_hz = 5000000,
397 .bus_num = 0,
398 .chip_select = 2,
399 .platform_data = &mx31_3ds_l4f00242t03_pdata,
400 },
401};
402
403
404
405
406static const struct mxc_nand_platform_data
407mx31_3ds_nand_board_info __initconst = {
408 .width = 1,
409 .hw_ecc = 1,
410#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
411 .flash_bbt = 1,
412#endif
413};
414
415
416
417
418
419#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
420 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
421
422#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
423#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
424
425static int mx31_3ds_usbotg_init(void)
426{
427 int err;
428
429 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
430 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
431 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
432 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
433 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
434 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
435 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
436 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
437 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
438 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
439 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
440 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
441
442 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
443 if (err) {
444 pr_err("Failed to request the USB OTG reset gpio\n");
445 return err;
446 }
447
448 err = gpio_direction_output(USBOTG_RST_B, 0);
449 if (err) {
450 pr_err("Failed to drive the USB OTG reset gpio\n");
451 goto usbotg_free_reset;
452 }
453
454 mdelay(1);
455 gpio_set_value(USBOTG_RST_B, 1);
456 return 0;
457
458usbotg_free_reset:
459 gpio_free(USBOTG_RST_B);
460 return err;
461}
462
463static int mx31_3ds_otg_init(struct platform_device *pdev)
464{
465 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
466}
467
468static int mx31_3ds_host2_init(struct platform_device *pdev)
469{
470 int err;
471
472 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
473 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
474 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
475 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
476 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
477 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
478 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
479 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
480 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
481 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
482 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
483 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
484
485 err = gpio_request(USBH2_RST_B, "usbh2-reset");
486 if (err) {
487 pr_err("Failed to request the USB Host 2 reset gpio\n");
488 return err;
489 }
490
491 err = gpio_direction_output(USBH2_RST_B, 0);
492 if (err) {
493 pr_err("Failed to drive the USB Host 2 reset gpio\n");
494 goto usbotg_free_reset;
495 }
496
497 mdelay(1);
498 gpio_set_value(USBH2_RST_B, 1);
499
500 mdelay(10);
501
502 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
503
504usbotg_free_reset:
505 gpio_free(USBH2_RST_B);
506 return err;
507}
508
509static struct mxc_usbh_platform_data otg_pdata __initdata = {
510 .init = mx31_3ds_otg_init,
511 .portsc = MXC_EHCI_MODE_ULPI,
512};
513
514static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
515 .init = mx31_3ds_host2_init,
516 .portsc = MXC_EHCI_MODE_ULPI,
517};
518
519static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
520 .operating_mode = FSL_USB2_DR_DEVICE,
521 .phy_mode = FSL_USB2_PHY_ULPI,
522};
523
524static bool otg_mode_host __initdata;
525
526static int __init mx31_3ds_otg_mode(char *options)
527{
528 if (!strcmp(options, "host"))
529 otg_mode_host = true;
530 else if (!strcmp(options, "device"))
531 otg_mode_host = false;
532 else
533 pr_info("otg_mode neither \"host\" nor \"device\". "
534 "Defaulting to device\n");
535 return 1;
536}
537__setup("otg_mode=", mx31_3ds_otg_mode);
538
539static const struct imxuart_platform_data uart_pdata __initconst = {
540 .flags = IMXUART_HAVE_RTSCTS,
541};
542
543static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
544 .bitrate = 100000,
545};
546
547static void __init mx31_3ds_init(void)
548{
549 imx31_soc_init();
550
551
552 mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
553
554 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
555 "mx31_3ds");
556
557 imx31_add_imx_uart0(&uart_pdata);
558 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
559
560 imx31_add_spi_imx1(&spi1_pdata);
561
562 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
563
564 imx31_add_imx2_wdt();
565 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
566
567 imx31_add_spi_imx0(&spi0_pdata);
568 imx31_add_ipu_core();
569 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
570
571 imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
572
573 imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
574}
575
576static void __init mx31_3ds_late(void)
577{
578 mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
579 spi_register_board_info(mx31_3ds_spi_devs,
580 ARRAY_SIZE(mx31_3ds_spi_devs));
581
582 mx31_3ds_usbotg_init();
583 if (otg_mode_host) {
584 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
585 ULPI_OTG_DRVVBUS_EXT);
586 if (otg_pdata.otg)
587 imx31_add_mxc_ehci_otg(&otg_pdata);
588 }
589 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
590 ULPI_OTG_DRVVBUS_EXT);
591 if (usbh2_pdata.otg)
592 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
593
594 if (!otg_mode_host)
595 imx31_add_fsl_usb2_udc(&usbotg_pdata);
596
597 if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
598 printk(KERN_WARNING "Init of the debug board failed, all "
599 "devices on the debug board are unusable.\n");
600
601 imx31_add_mxc_mmc(0, &sdhc1_pdata);
602}
603
604static void __init mx31_3ds_timer_init(void)
605{
606 mx31_clocks_init(26000000);
607}
608
609MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
610
611 .atag_offset = 0x100,
612 .map_io = mx31_map_io,
613 .init_early = imx31_init_early,
614 .init_irq = mx31_init_irq,
615 .init_time = mx31_3ds_timer_init,
616 .init_machine = mx31_3ds_init,
617 .init_late = mx31_3ds_late,
618 .restart = mxc_restart,
619MACHINE_END
620
