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23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/gpio.h>
27#include <linux/platform_device.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32
33#include "board-mx31lilly.h"
34#include "common.h"
35#include "devices-imx31.h"
36#include "hardware.h"
37#include "iomux-mx3.h"
38
39
40
41
42
43
44
45static unsigned int lilly_db_board_pins[] __initdata = {
46 MX31_PIN_SD1_DATA3__SD1_DATA3,
47 MX31_PIN_SD1_DATA2__SD1_DATA2,
48 MX31_PIN_SD1_DATA1__SD1_DATA1,
49 MX31_PIN_SD1_DATA0__SD1_DATA0,
50 MX31_PIN_SD1_CLK__SD1_CLK,
51 MX31_PIN_SD1_CMD__SD1_CMD,
52 MX31_PIN_LD0__LD0,
53 MX31_PIN_LD1__LD1,
54 MX31_PIN_LD2__LD2,
55 MX31_PIN_LD3__LD3,
56 MX31_PIN_LD4__LD4,
57 MX31_PIN_LD5__LD5,
58 MX31_PIN_LD6__LD6,
59 MX31_PIN_LD7__LD7,
60 MX31_PIN_LD8__LD8,
61 MX31_PIN_LD9__LD9,
62 MX31_PIN_LD10__LD10,
63 MX31_PIN_LD11__LD11,
64 MX31_PIN_LD12__LD12,
65 MX31_PIN_LD13__LD13,
66 MX31_PIN_LD14__LD14,
67 MX31_PIN_LD15__LD15,
68 MX31_PIN_LD16__LD16,
69 MX31_PIN_LD17__LD17,
70 MX31_PIN_VSYNC3__VSYNC3,
71 MX31_PIN_HSYNC__HSYNC,
72 MX31_PIN_FPSHIFT__FPSHIFT,
73 MX31_PIN_DRDY0__DRDY0,
74 MX31_PIN_CONTRAST__CONTRAST,
75};
76
77
78
79static int mxc_mmc1_get_ro(struct device *dev)
80{
81 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
82}
83
84static int gpio_det, gpio_wp;
85
86#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
87 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
88
89static int mxc_mmc1_init(struct device *dev,
90 irq_handler_t detect_irq, void *data)
91{
92 int ret;
93
94 gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
95 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
96
97 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
98 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
99 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
100 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
101 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
102 mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
103
104 ret = gpio_request(gpio_det, "MMC detect");
105 if (ret)
106 return ret;
107
108 ret = gpio_request(gpio_wp, "MMC w/p");
109 if (ret)
110 goto exit_free_det;
111
112 gpio_direction_input(gpio_det);
113 gpio_direction_input(gpio_wp);
114
115 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
116 detect_irq, IRQF_TRIGGER_FALLING,
117 "MMC detect", data);
118 if (ret)
119 goto exit_free_wp;
120
121 return 0;
122
123exit_free_wp:
124 gpio_free(gpio_wp);
125
126exit_free_det:
127 gpio_free(gpio_det);
128
129 return ret;
130}
131
132static void mxc_mmc1_exit(struct device *dev, void *data)
133{
134 gpio_free(gpio_det);
135 gpio_free(gpio_wp);
136 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
137}
138
139static const struct imxmmc_platform_data mmc_pdata __initconst = {
140 .get_ro = mxc_mmc1_get_ro,
141 .init = mxc_mmc1_init,
142 .exit = mxc_mmc1_exit,
143};
144
145
146static const struct fb_videomode fb_modedb = {
147
148 .name = "CRT-VGA",
149 .refresh = 64,
150 .xres = 640,
151 .yres = 480,
152 .pixclock = 30000,
153 .left_margin = 200,
154 .right_margin = 2,
155 .upper_margin = 2,
156 .lower_margin = 2,
157 .hsync_len = 3,
158 .vsync_len = 1,
159 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
160 .vmode = FB_VMODE_NONINTERLACED,
161 .flag = 0,
162};
163
164static struct mx3fb_platform_data fb_pdata __initdata = {
165 .name = "CRT-VGA",
166 .mode = &fb_modedb,
167 .num_modes = 1,
168};
169
170#define LCD_VCC_EN_GPIO (7)
171
172static void __init mx31lilly_init_fb(void)
173{
174 if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) {
175 printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n");
176 return;
177 }
178
179 imx31_add_ipu_core();
180 imx31_add_mx3_sdc_fb(&fb_pdata);
181 gpio_direction_output(LCD_VCC_EN_GPIO, 1);
182}
183
184void __init mx31lilly_db_init(void)
185{
186 mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
187 ARRAY_SIZE(lilly_db_board_pins),
188 "development board pins");
189 imx31_add_mxc_mmc(0, &mmc_pdata);
190 mx31lilly_init_fb();
191}
192
