LXR linux/arch/arm/mach-omap1/ams-delta-fiq.c

   1/*
   2 *  Amstrad E3 FIQ handling
   3 *
   4 *  Copyright (C) 2009 Janusz Krzysztofik
   5 *  Copyright (c) 2006 Matt Callow
   6 *  Copyright (c) 2004 Amstrad Plc
   7 *  Copyright (C) 2001 RidgeRun, Inc.
   8 *
   9 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
  10 * in the MontaVista 2.4 kernel (and the Amstrad changes therein)
  11 *
  12 * This program is free software; you can redistribute it and/or modify it
  13 * under the terms of the GNU General Public License version 2 as published by
  14 * the Free Software Foundation.
  15 */
  16#include <linux/gpio.h>
  17#include <linux/interrupt.h>
  18#include <linux/irq.h>
  19#include <linux/module.h>
  20#include <linux/io.h>
  21
  22#include <mach/board-ams-delta.h>
  23
  24#include <asm/fiq.h>
  25
  26#include <mach/ams-delta-fiq.h>
  27
  28static struct fiq_handler fh = {
  29        .name   = "ams-delta-fiq"
  30};
  31
  32/*
  33 * This buffer is shared between FIQ and IRQ contexts.
  34 * The FIQ and IRQ isrs can both read and write it.
  35 * It is structured as a header section several 32bit slots,
  36 * followed by the circular buffer where the FIQ isr stores
  37 * keystrokes received from the qwerty keyboard.
  38 * See ams-delta-fiq.h for details of offsets.
  39 */
  40unsigned int fiq_buffer[1024];
  41EXPORT_SYMBOL(fiq_buffer);
  42
  43static unsigned int irq_counter[16];
  44
  45static irqreturn_t deferred_fiq(int irq, void *dev_id)
  46{
  47        int gpio, irq_num, fiq_count;
  48        struct irq_chip *irq_chip;
  49
  50        irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
  51
  52        /*
  53         * For each handled GPIO interrupt, keep calling its interrupt handler
  54         * until the IRQ counter catches the FIQ incremented interrupt counter.
  55         */
  56        for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
  57                        gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
  58                irq_num = gpio_to_irq(gpio);
  59                fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
  60
  61                if (irq_counter[gpio] < fiq_count &&
  62                                gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
  63                        struct irq_data *d = irq_get_irq_data(irq_num);
  64
  65                        /*
  66                         * handle_simple_irq() that OMAP GPIO edge
  67                         * interrupts default to since commit 80ac93c27441
  68                         * requires interrupt already acked and unmasked.
  69                         */
  70                        if (irq_chip) {
  71                                if (irq_chip->irq_ack)
  72                                        irq_chip->irq_ack(d);
  73                                if (irq_chip->irq_unmask)
  74                                        irq_chip->irq_unmask(d);
  75                        }
  76                }
  77                for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
  78                        generic_handle_irq(irq_num);
  79        }
  80        return IRQ_HANDLED;
  81}
  82
  83void __init ams_delta_init_fiq(void)
  84{
  85        void *fiqhandler_start;
  86        unsigned int fiqhandler_length;
  87        struct pt_regs FIQ_regs;
  88        unsigned long val, offset;
  89        int i, retval;
  90
  91        fiqhandler_start = &qwerty_fiqin_start;
  92        fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
  93        pr_info("Installing fiq handler from %p, length 0x%x\n",
  94                        fiqhandler_start, fiqhandler_length);
  95
  96        retval = claim_fiq(&fh);
  97        if (retval) {
  98                pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
  99                                retval);
 100                return;
 101        }
 102
 103        retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
 104                        IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
 105        if (retval < 0) {
 106                pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
 107                release_fiq(&fh);
 108                return;
 109        }
 110        /*
 111         * Since no set_type() method is provided by OMAP irq chip,
 112         * switch to edge triggered interrupt type manually.
 113         */
 114        offset = IRQ_ILR0_REG_OFFSET +
 115                        ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
 116        val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
 117        omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
 118
 119        set_fiq_handler(fiqhandler_start, fiqhandler_length);
 120
 121        /*
 122         * Initialise the buffer which is shared
 123         * between FIQ mode and IRQ mode
 124         */
 125        fiq_buffer[FIQ_GPIO_INT_MASK]   = 0;
 126        fiq_buffer[FIQ_MASK]            = 0;
 127        fiq_buffer[FIQ_STATE]           = 0;
 128        fiq_buffer[FIQ_KEY]             = 0;
 129        fiq_buffer[FIQ_KEYS_CNT]        = 0;
 130        fiq_buffer[FIQ_KEYS_HICNT]      = 0;
 131        fiq_buffer[FIQ_TAIL_OFFSET]     = 0;
 132        fiq_buffer[FIQ_HEAD_OFFSET]     = 0;
 133        fiq_buffer[FIQ_BUF_LEN]         = 256;
 134        fiq_buffer[FIQ_MISSED_KEYS]     = 0;
 135        fiq_buffer[FIQ_BUFFER_START]    =
 136                        (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
 137
 138        for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
 139                fiq_buffer[i] = 0;
 140
 141        /*
 142         * FIQ mode r9 always points to the fiq_buffer, because the FIQ isr
 143         * will run in an unpredictable context. The fiq_buffer is the FIQ isr's
 144         * only means of communication with the IRQ level and other kernel
 145         * context code.
 146         */
 147        FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
 148        set_fiq_regs(&FIQ_regs);
 149
 150        pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
 151
 152        /*
 153         * Redirect GPIO interrupts to FIQ
 154         */
 155        offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
 156        val = omap_readl(OMAP_IH1_BASE + offset) | 1;
 157        omap_writel(val, OMAP_IH1_BASE + offset);
 158}
 159