linux/arch/microblaze/pci/pci-common.c
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   1/*
   2 * Contains common pci routines for ALL ppc platform
   3 * (based on pci_32.c and pci_64.c)
   4 *
   5 * Port for PPC64 David Engebretsen, IBM Corp.
   6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   7 *
   8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   9 *   Rework, based on alpha PCI code.
  10 *
  11 * Common pmac/prep/chrp pci routines. -- Cort
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License
  15 * as published by the Free Software Foundation; either version
  16 * 2 of the License, or (at your option) any later version.
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/pci.h>
  21#include <linux/string.h>
  22#include <linux/init.h>
  23#include <linux/bootmem.h>
  24#include <linux/mm.h>
  25#include <linux/shmem_fs.h>
  26#include <linux/list.h>
  27#include <linux/syscalls.h>
  28#include <linux/irq.h>
  29#include <linux/vmalloc.h>
  30#include <linux/slab.h>
  31#include <linux/of.h>
  32#include <linux/of_address.h>
  33#include <linux/of_irq.h>
  34#include <linux/of_pci.h>
  35#include <linux/export.h>
  36
  37#include <asm/processor.h>
  38#include <linux/io.h>
  39#include <asm/pci-bridge.h>
  40#include <asm/byteorder.h>
  41
  42static DEFINE_SPINLOCK(hose_spinlock);
  43LIST_HEAD(hose_list);
  44
  45/* XXX kill that some day ... */
  46static int global_phb_number;           /* Global phb counter */
  47
  48/* ISA Memory physical address */
  49resource_size_t isa_mem_base;
  50
  51unsigned long isa_io_base;
  52EXPORT_SYMBOL(isa_io_base);
  53
  54static int pci_bus_count;
  55
  56struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
  57{
  58        struct pci_controller *phb;
  59
  60        phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
  61        if (!phb)
  62                return NULL;
  63        spin_lock(&hose_spinlock);
  64        phb->global_number = global_phb_number++;
  65        list_add_tail(&phb->list_node, &hose_list);
  66        spin_unlock(&hose_spinlock);
  67        phb->dn = dev;
  68        phb->is_dynamic = mem_init_done;
  69        return phb;
  70}
  71
  72void pcibios_free_controller(struct pci_controller *phb)
  73{
  74        spin_lock(&hose_spinlock);
  75        list_del(&phb->list_node);
  76        spin_unlock(&hose_spinlock);
  77
  78        if (phb->is_dynamic)
  79                kfree(phb);
  80}
  81
  82static resource_size_t pcibios_io_size(const struct pci_controller *hose)
  83{
  84        return resource_size(&hose->io_resource);
  85}
  86
  87int pcibios_vaddr_is_ioport(void __iomem *address)
  88{
  89        int ret = 0;
  90        struct pci_controller *hose;
  91        resource_size_t size;
  92
  93        spin_lock(&hose_spinlock);
  94        list_for_each_entry(hose, &hose_list, list_node) {
  95                size = pcibios_io_size(hose);
  96                if (address >= hose->io_base_virt &&
  97                    address < (hose->io_base_virt + size)) {
  98                        ret = 1;
  99                        break;
 100                }
 101        }
 102        spin_unlock(&hose_spinlock);
 103        return ret;
 104}
 105
 106unsigned long pci_address_to_pio(phys_addr_t address)
 107{
 108        struct pci_controller *hose;
 109        resource_size_t size;
 110        unsigned long ret = ~0;
 111
 112        spin_lock(&hose_spinlock);
 113        list_for_each_entry(hose, &hose_list, list_node) {
 114                size = pcibios_io_size(hose);
 115                if (address >= hose->io_base_phys &&
 116                    address < (hose->io_base_phys + size)) {
 117                        unsigned long base =
 118                                (unsigned long)hose->io_base_virt - _IO_BASE;
 119                        ret = base + (address - hose->io_base_phys);
 120                        break;
 121                }
 122        }
 123        spin_unlock(&hose_spinlock);
 124
 125        return ret;
 126}
 127EXPORT_SYMBOL_GPL(pci_address_to_pio);
 128
 129/* This routine is meant to be used early during boot, when the
 130 * PCI bus numbers have not yet been assigned, and you need to
 131 * issue PCI config cycles to an OF device.
 132 * It could also be used to "fix" RTAS config cycles if you want
 133 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
 134 * config cycles.
 135 */
 136struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
 137{
 138        while (node) {
 139                struct pci_controller *hose, *tmp;
 140                list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
 141                        if (hose->dn == node)
 142                                return hose;
 143                node = node->parent;
 144        }
 145        return NULL;
 146}
 147
 148void pcibios_set_master(struct pci_dev *dev)
 149{
 150        /* No special bus mastering setup handling */
 151}
 152
 153/*
 154 * Platform support for /proc/bus/pci/X/Y mmap()s.
 155 */
 156
 157int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
 158{
 159        struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 160        resource_size_t ioaddr = pci_resource_start(pdev, bar);
 161
 162        if (!hose)
 163                return -EINVAL;         /* should never happen */
 164
 165        /* Convert to an offset within this PCI controller */
 166        ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
 167
 168        vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
 169        return 0;
 170}
 171
 172/*
 173 * This one is used by /dev/mem and fbdev who have no clue about the
 174 * PCI device, it tries to find the PCI device first and calls the
 175 * above routine
 176 */
 177pgprot_t pci_phys_mem_access_prot(struct file *file,
 178                                  unsigned long pfn,
 179                                  unsigned long size,
 180                                  pgprot_t prot)
 181{
 182        struct pci_dev *pdev = NULL;
 183        struct resource *found = NULL;
 184        resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
 185        int i;
 186
 187        if (page_is_ram(pfn))
 188                return prot;
 189
 190        prot = pgprot_noncached(prot);
 191        for_each_pci_dev(pdev) {
 192                for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 193                        struct resource *rp = &pdev->resource[i];
 194                        int flags = rp->flags;
 195
 196                        /* Active and same type? */
 197                        if ((flags & IORESOURCE_MEM) == 0)
 198                                continue;
 199                        /* In the range of this resource? */
 200                        if (offset < (rp->start & PAGE_MASK) ||
 201                            offset > rp->end)
 202                                continue;
 203                        found = rp;
 204                        break;
 205                }
 206                if (found)
 207                        break;
 208        }
 209        if (found) {
 210                if (found->flags & IORESOURCE_PREFETCH)
 211                        prot = pgprot_noncached_wc(prot);
 212                pci_dev_put(pdev);
 213        }
 214
 215        pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
 216                 (unsigned long long)offset, pgprot_val(prot));
 217
 218        return prot;
 219}
 220
 221/* This provides legacy IO read access on a bus */
 222int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
 223{
 224        unsigned long offset;
 225        struct pci_controller *hose = pci_bus_to_host(bus);
 226        struct resource *rp = &hose->io_resource;
 227        void __iomem *addr;
 228
 229        /* Check if port can be supported by that bus. We only check
 230         * the ranges of the PHB though, not the bus itself as the rules
 231         * for forwarding legacy cycles down bridges are not our problem
 232         * here. So if the host bridge supports it, we do it.
 233         */
 234        offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 235        offset += port;
 236
 237        if (!(rp->flags & IORESOURCE_IO))
 238                return -ENXIO;
 239        if (offset < rp->start || (offset + size) > rp->end)
 240                return -ENXIO;
 241        addr = hose->io_base_virt + port;
 242
 243        switch (size) {
 244        case 1:
 245                *((u8 *)val) = in_8(addr);
 246                return 1;
 247        case 2:
 248                if (port & 1)
 249                        return -EINVAL;
 250                *((u16 *)val) = in_le16(addr);
 251                return 2;
 252        case 4:
 253                if (port & 3)
 254                        return -EINVAL;
 255                *((u32 *)val) = in_le32(addr);
 256                return 4;
 257        }
 258        return -EINVAL;
 259}
 260
 261/* This provides legacy IO write access on a bus */
 262int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
 263{
 264        unsigned long offset;
 265        struct pci_controller *hose = pci_bus_to_host(bus);
 266        struct resource *rp = &hose->io_resource;
 267        void __iomem *addr;
 268
 269        /* Check if port can be supported by that bus. We only check
 270         * the ranges of the PHB though, not the bus itself as the rules
 271         * for forwarding legacy cycles down bridges are not our problem
 272         * here. So if the host bridge supports it, we do it.
 273         */
 274        offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 275        offset += port;
 276
 277        if (!(rp->flags & IORESOURCE_IO))
 278                return -ENXIO;
 279        if (offset < rp->start || (offset + size) > rp->end)
 280                return -ENXIO;
 281        addr = hose->io_base_virt + port;
 282
 283        /* WARNING: The generic code is idiotic. It gets passed a pointer
 284         * to what can be a 1, 2 or 4 byte quantity and always reads that
 285         * as a u32, which means that we have to correct the location of
 286         * the data read within those 32 bits for size 1 and 2
 287         */
 288        switch (size) {
 289        case 1:
 290                out_8(addr, val >> 24);
 291                return 1;
 292        case 2:
 293                if (port & 1)
 294                        return -EINVAL;
 295                out_le16(addr, val >> 16);
 296                return 2;
 297        case 4:
 298                if (port & 3)
 299                        return -EINVAL;
 300                out_le32(addr, val);
 301                return 4;
 302        }
 303        return -EINVAL;
 304}
 305
 306/* This provides legacy IO or memory mmap access on a bus */
 307int pci_mmap_legacy_page_range(struct pci_bus *bus,
 308                               struct vm_area_struct *vma,
 309                               enum pci_mmap_state mmap_state)
 310{
 311        struct pci_controller *hose = pci_bus_to_host(bus);
 312        resource_size_t offset =
 313                ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
 314        resource_size_t size = vma->vm_end - vma->vm_start;
 315        struct resource *rp;
 316
 317        pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
 318                 pci_domain_nr(bus), bus->number,
 319                 mmap_state == pci_mmap_mem ? "MEM" : "IO",
 320                 (unsigned long long)offset,
 321                 (unsigned long long)(offset + size - 1));
 322
 323        if (mmap_state == pci_mmap_mem) {
 324                /* Hack alert !
 325                 *
 326                 * Because X is lame and can fail starting if it gets an error
 327                 * trying to mmap legacy_mem (instead of just moving on without
 328                 * legacy memory access) we fake it here by giving it anonymous
 329                 * memory, effectively behaving just like /dev/zero
 330                 */
 331                if ((offset + size) > hose->isa_mem_size) {
 332#ifdef CONFIG_MMU
 333                        pr_debug("Process %s (pid:%d) mapped non-existing PCI",
 334                                current->comm, current->pid);
 335                        pr_debug("legacy memory for 0%04x:%02x\n",
 336                                pci_domain_nr(bus), bus->number);
 337#endif
 338                        if (vma->vm_flags & VM_SHARED)
 339                                return shmem_zero_setup(vma);
 340                        return 0;
 341                }
 342                offset += hose->isa_mem_phys;
 343        } else {
 344                unsigned long io_offset = (unsigned long)hose->io_base_virt -
 345                                                                _IO_BASE;
 346                unsigned long roffset = offset + io_offset;
 347                rp = &hose->io_resource;
 348                if (!(rp->flags & IORESOURCE_IO))
 349                        return -ENXIO;
 350                if (roffset < rp->start || (roffset + size) > rp->end)
 351                        return -ENXIO;
 352                offset += hose->io_base_phys;
 353        }
 354        pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
 355
 356        vma->vm_pgoff = offset >> PAGE_SHIFT;
 357        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 358        return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 359                               vma->vm_end - vma->vm_start,
 360                               vma->vm_page_prot);
 361}
 362
 363void pci_resource_to_user(const struct pci_dev *dev, int bar,
 364                          const struct resource *rsrc,
 365                          resource_size_t *start, resource_size_t *end)
 366{
 367        struct pci_bus_region region;
 368
 369        if (rsrc->flags & IORESOURCE_IO) {
 370                pcibios_resource_to_bus(dev->bus, &region,
 371                                        (struct resource *) rsrc);
 372                *start = region.start;
 373                *end = region.end;
 374                return;
 375        }
 376
 377        /* We pass a CPU physical address to userland for MMIO instead of a
 378         * BAR value because X is lame and expects to be able to use that
 379         * to pass to /dev/mem!
 380         *
 381         * That means we may have 64-bit values where some apps only expect
 382         * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
 383         */
 384        *start = rsrc->start;
 385        *end = rsrc->end;
 386}
 387
 388/**
 389 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
 390 * @hose: newly allocated pci_controller to be setup
 391 * @dev: device node of the host bridge
 392 * @primary: set if primary bus (32 bits only, soon to be deprecated)
 393 *
 394 * This function will parse the "ranges" property of a PCI host bridge device
 395 * node and setup the resource mapping of a pci controller based on its
 396 * content.
 397 *
 398 * Life would be boring if it wasn't for a few issues that we have to deal
 399 * with here:
 400 *
 401 *   - We can only cope with one IO space range and up to 3 Memory space
 402 *     ranges. However, some machines (thanks Apple !) tend to split their
 403 *     space into lots of small contiguous ranges. So we have to coalesce.
 404 *
 405 *   - We can only cope with all memory ranges having the same offset
 406 *     between CPU addresses and PCI addresses. Unfortunately, some bridges
 407 *     are setup for a large 1:1 mapping along with a small "window" which
 408 *     maps PCI address 0 to some arbitrary high address of the CPU space in
 409 *     order to give access to the ISA memory hole.
 410 *     The way out of here that I've chosen for now is to always set the
 411 *     offset based on the first resource found, then override it if we
 412 *     have a different offset and the previous was set by an ISA hole.
 413 *
 414 *   - Some busses have IO space not starting at 0, which causes trouble with
 415 *     the way we do our IO resource renumbering. The code somewhat deals with
 416 *     it for 64 bits but I would expect problems on 32 bits.
 417 *
 418 *   - Some 32 bits platforms such as 4xx can have physical space larger than
 419 *     32 bits so we need to use 64 bits values for the parsing
 420 */
 421void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 422                                  struct device_node *dev, int primary)
 423{
 424        int memno = 0, isa_hole = -1;
 425        unsigned long long isa_mb = 0;
 426        struct resource *res;
 427        struct of_pci_range range;
 428        struct of_pci_range_parser parser;
 429
 430        pr_info("PCI host bridge %pOF %s ranges:\n",
 431               dev, primary ? "(primary)" : "");
 432
 433        /* Check for ranges property */
 434        if (of_pci_range_parser_init(&parser, dev))
 435                return;
 436
 437        pr_debug("Parsing ranges property...\n");
 438        for_each_of_pci_range(&parser, &range) {
 439                /* Read next ranges element */
 440                pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
 441                                range.pci_space, range.pci_addr);
 442                pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
 443                                        range.cpu_addr, range.size);
 444
 445                /* If we failed translation or got a zero-sized region
 446                 * (some FW try to feed us with non sensical zero sized regions
 447                 * such as power3 which look like some kind of attempt
 448                 * at exposing the VGA memory hole)
 449                 */
 450                if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
 451                        continue;
 452
 453                /* Act based on address space type */
 454                res = NULL;
 455                switch (range.flags & IORESOURCE_TYPE_BITS) {
 456                case IORESOURCE_IO:
 457                        pr_info("  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
 458                                range.cpu_addr, range.cpu_addr + range.size - 1,
 459                                range.pci_addr);
 460
 461                        /* We support only one IO range */
 462                        if (hose->pci_io_size) {
 463                                pr_info(" \\--> Skipped (too many) !\n");
 464                                continue;
 465                        }
 466                        /* On 32 bits, limit I/O space to 16MB */
 467                        if (range.size > 0x01000000)
 468                                range.size = 0x01000000;
 469
 470                        /* 32 bits needs to map IOs here */
 471                        hose->io_base_virt = ioremap(range.cpu_addr,
 472                                                range.size);
 473
 474                        /* Expect trouble if pci_addr is not 0 */
 475                        if (primary)
 476                                isa_io_base =
 477                                        (unsigned long)hose->io_base_virt;
 478                        /* pci_io_size and io_base_phys always represent IO
 479                         * space starting at 0 so we factor in pci_addr
 480                         */
 481                        hose->pci_io_size = range.pci_addr + range.size;
 482                        hose->io_base_phys = range.cpu_addr - range.pci_addr;
 483
 484                        /* Build resource */
 485                        res = &hose->io_resource;
 486                        range.cpu_addr = range.pci_addr;
 487
 488                        break;
 489                case IORESOURCE_MEM:
 490                        pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
 491                                range.cpu_addr, range.cpu_addr + range.size - 1,
 492                                range.pci_addr,
 493                                (range.pci_space & 0x40000000) ?
 494                                "Prefetch" : "");
 495
 496                        /* We support only 3 memory ranges */
 497                        if (memno >= 3) {
 498                                pr_info(" \\--> Skipped (too many) !\n");
 499                                continue;
 500                        }
 501                        /* Handles ISA memory hole space here */
 502                        if (range.pci_addr == 0) {
 503                                isa_mb = range.cpu_addr;
 504                                isa_hole = memno;
 505                                if (primary || isa_mem_base == 0)
 506                                        isa_mem_base = range.cpu_addr;
 507                                hose->isa_mem_phys = range.cpu_addr;
 508                                hose->isa_mem_size = range.size;
 509                        }
 510
 511                        /* We get the PCI/Mem offset from the first range or
 512                         * the, current one if the offset came from an ISA
 513                         * hole. If they don't match, bugger.
 514                         */
 515                        if (memno == 0 ||
 516                            (isa_hole >= 0 && range.pci_addr != 0 &&
 517                             hose->pci_mem_offset == isa_mb))
 518                                hose->pci_mem_offset = range.cpu_addr -
 519                                                        range.pci_addr;
 520                        else if (range.pci_addr != 0 &&
 521                                 hose->pci_mem_offset != range.cpu_addr -
 522                                                        range.pci_addr) {
 523                                pr_info(" \\--> Skipped (offset mismatch) !\n");
 524                                continue;
 525                        }
 526
 527                        /* Build resource */
 528                        res = &hose->mem_resources[memno++];
 529                        break;
 530                }
 531                if (res != NULL) {
 532                        res->name = dev->full_name;
 533                        res->flags = range.flags;
 534                        res->start = range.cpu_addr;
 535                        res->end = range.cpu_addr + range.size - 1;
 536                        res->parent = res->child = res->sibling = NULL;
 537                }
 538        }
 539
 540        /* If there's an ISA hole and the pci_mem_offset is -not- matching
 541         * the ISA hole offset, then we need to remove the ISA hole from
 542         * the resource list for that brige
 543         */
 544        if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
 545                unsigned int next = isa_hole + 1;
 546                pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
 547                if (next < memno)
 548                        memmove(&hose->mem_resources[isa_hole],
 549                                &hose->mem_resources[next],
 550                                sizeof(struct resource) * (memno - next));
 551                hose->mem_resources[--memno].flags = 0;
 552        }
 553}
 554
 555/* Display the domain number in /proc */
 556int pci_proc_domain(struct pci_bus *bus)
 557{
 558        return pci_domain_nr(bus);
 559}
 560
 561/* This header fixup will do the resource fixup for all devices as they are
 562 * probed, but not for bridge ranges
 563 */
 564static void pcibios_fixup_resources(struct pci_dev *dev)
 565{
 566        struct pci_controller *hose = pci_bus_to_host(dev->bus);
 567        int i;
 568
 569        if (!hose) {
 570                pr_err("No host bridge for PCI dev %s !\n",
 571                       pci_name(dev));
 572                return;
 573        }
 574        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 575                struct resource *res = dev->resource + i;
 576                if (!res->flags)
 577                        continue;
 578                if (res->start == 0) {
 579                        pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
 580                                 pci_name(dev), i,
 581                                 (unsigned long long)res->start,
 582                                 (unsigned long long)res->end,
 583                                 (unsigned int)res->flags);
 584                        pr_debug("is unassigned\n");
 585                        res->end -= res->start;
 586                        res->start = 0;
 587                        res->flags |= IORESOURCE_UNSET;
 588                        continue;
 589                }
 590
 591                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
 592                         pci_name(dev), i,
 593                         (unsigned long long)res->start,
 594                         (unsigned long long)res->end,
 595                         (unsigned int)res->flags);
 596        }
 597}
 598DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
 599
 600/*
 601 * We need to avoid collisions with `mirrored' VGA ports
 602 * and other strange ISA hardware, so we always want the
 603 * addresses to be allocated in the 0x000-0x0ff region
 604 * modulo 0x400.
 605 *
 606 * Why? Because some silly external IO cards only decode
 607 * the low 10 bits of the IO address. The 0x00-0xff region
 608 * is reserved for motherboard devices that decode all 16
 609 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 610 * but we want to try to avoid allocating at 0x2900-0x2bff
 611 * which might have be mirrored at 0x0100-0x03ff..
 612 */
 613int pcibios_add_device(struct pci_dev *dev)
 614{
 615        dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
 616
 617        return 0;
 618}
 619EXPORT_SYMBOL(pcibios_add_device);
 620
 621/*
 622 * Reparent resource children of pr that conflict with res
 623 * under res, and make res replace those children.
 624 */
 625static int __init reparent_resources(struct resource *parent,
 626                                     struct resource *res)
 627{
 628        struct resource *p, **pp;
 629        struct resource **firstpp = NULL;
 630
 631        for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
 632                if (p->end < res->start)
 633                        continue;
 634                if (res->end < p->start)
 635                        break;
 636                if (p->start < res->start || p->end > res->end)
 637                        return -1;      /* not completely contained */
 638                if (firstpp == NULL)
 639                        firstpp = pp;
 640        }
 641        if (firstpp == NULL)
 642                return -1;      /* didn't find any conflicting entries? */
 643        res->parent = parent;
 644        res->child = *firstpp;
 645        res->sibling = *pp;
 646        *firstpp = res;
 647        *pp = NULL;
 648        for (p = res->child; p != NULL; p = p->sibling) {
 649                p->parent = res;
 650                pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
 651                         p->name,
 652                         (unsigned long long)p->start,
 653                         (unsigned long long)p->end, res->name);
 654        }
 655        return 0;
 656}
 657
 658/*
 659 *  Handle resources of PCI devices.  If the world were perfect, we could
 660 *  just allocate all the resource regions and do nothing more.  It isn't.
 661 *  On the other hand, we cannot just re-allocate all devices, as it would
 662 *  require us to know lots of host bridge internals.  So we attempt to
 663 *  keep as much of the original configuration as possible, but tweak it
 664 *  when it's found to be wrong.
 665 *
 666 *  Known BIOS problems we have to work around:
 667 *      - I/O or memory regions not configured
 668 *      - regions configured, but not enabled in the command register
 669 *      - bogus I/O addresses above 64K used
 670 *      - expansion ROMs left enabled (this may sound harmless, but given
 671 *        the fact the PCI specs explicitly allow address decoders to be
 672 *        shared between expansion ROMs and other resource regions, it's
 673 *        at least dangerous)
 674 *
 675 *  Our solution:
 676 *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
 677 *          This gives us fixed barriers on where we can allocate.
 678 *      (2) Allocate resources for all enabled devices.  If there is
 679 *          a collision, just mark the resource as unallocated. Also
 680 *          disable expansion ROMs during this step.
 681 *      (3) Try to allocate resources for disabled devices.  If the
 682 *          resources were assigned correctly, everything goes well,
 683 *          if they weren't, they won't disturb allocation of other
 684 *          resources.
 685 *      (4) Assign new addresses to resources which were either
 686 *          not configured at all or misconfigured.  If explicitly
 687 *          requested by the user, configure expansion ROM address
 688 *          as well.
 689 */
 690
 691static void pcibios_allocate_bus_resources(struct pci_bus *bus)
 692{
 693        struct pci_bus *b;
 694        int i;
 695        struct resource *res, *pr;
 696
 697        pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
 698                 pci_domain_nr(bus), bus->number);
 699
 700        pci_bus_for_each_resource(bus, res, i) {
 701                if (!res || !res->flags
 702                    || res->start > res->end || res->parent)
 703                        continue;
 704                if (bus->parent == NULL)
 705                        pr = (res->flags & IORESOURCE_IO) ?
 706                                &ioport_resource : &iomem_resource;
 707                else {
 708                        /* Don't bother with non-root busses when
 709                         * re-assigning all resources. We clear the
 710                         * resource flags as if they were colliding
 711                         * and as such ensure proper re-allocation
 712                         * later.
 713                         */
 714                        pr = pci_find_parent_resource(bus->self, res);
 715                        if (pr == res) {
 716                                /* this happens when the generic PCI
 717                                 * code (wrongly) decides that this
 718                                 * bridge is transparent  -- paulus
 719                                 */
 720                                continue;
 721                        }
 722                }
 723
 724                pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
 725                         bus->self ? pci_name(bus->self) : "PHB",
 726                         bus->number, i,
 727                         (unsigned long long)res->start,
 728                         (unsigned long long)res->end);
 729                pr_debug("[0x%x], parent %p (%s)\n",
 730                         (unsigned int)res->flags,
 731                         pr, (pr && pr->name) ? pr->name : "nil");
 732
 733                if (pr && !(pr->flags & IORESOURCE_UNSET)) {
 734                        struct pci_dev *dev = bus->self;
 735
 736                        if (request_resource(pr, res) == 0)
 737                                continue;
 738                        /*
 739                         * Must be a conflict with an existing entry.
 740                         * Move that entry (or entries) under the
 741                         * bridge resource and try again.
 742                         */
 743                        if (reparent_resources(pr, res) == 0)
 744                                continue;
 745
 746                        if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
 747                            pci_claim_bridge_resource(dev,
 748                                                 i + PCI_BRIDGE_RESOURCES) == 0)
 749                                continue;
 750
 751                }
 752                pr_warn("PCI: Cannot allocate resource region ");
 753                pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
 754                res->start = res->end = 0;
 755                res->flags = 0;
 756        }
 757
 758        list_for_each_entry(b, &bus->children, node)
 759                pcibios_allocate_bus_resources(b);
 760}
 761
 762static inline void alloc_resource(struct pci_dev *dev, int idx)
 763{
 764        struct resource *pr, *r = &dev->resource[idx];
 765
 766        pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
 767                 pci_name(dev), idx,
 768                 (unsigned long long)r->start,
 769                 (unsigned long long)r->end,
 770                 (unsigned int)r->flags);
 771
 772        pr = pci_find_parent_resource(dev, r);
 773        if (!pr || (pr->flags & IORESOURCE_UNSET) ||
 774            request_resource(pr, r) < 0) {
 775                pr_warn("PCI: Cannot allocate resource region %d ", idx);
 776                pr_cont("of device %s, will remap\n", pci_name(dev));
 777                if (pr)
 778                        pr_debug("PCI:  parent is %p: %016llx-%016llx [%x]\n",
 779                                 pr,
 780                                 (unsigned long long)pr->start,
 781                                 (unsigned long long)pr->end,
 782                                 (unsigned int)pr->flags);
 783                /* We'll assign a new address later */
 784                r->flags |= IORESOURCE_UNSET;
 785                r->end -= r->start;
 786                r->start = 0;
 787        }
 788}
 789
 790static void __init pcibios_allocate_resources(int pass)
 791{
 792        struct pci_dev *dev = NULL;
 793        int idx, disabled;
 794        u16 command;
 795        struct resource *r;
 796
 797        for_each_pci_dev(dev) {
 798                pci_read_config_word(dev, PCI_COMMAND, &command);
 799                for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
 800                        r = &dev->resource[idx];
 801                        if (r->parent)          /* Already allocated */
 802                                continue;
 803                        if (!r->flags || (r->flags & IORESOURCE_UNSET))
 804                                continue;       /* Not assigned at all */
 805                        /* We only allocate ROMs on pass 1 just in case they
 806                         * have been screwed up by firmware
 807                         */
 808                        if (idx == PCI_ROM_RESOURCE)
 809                                disabled = 1;
 810                        if (r->flags & IORESOURCE_IO)
 811                                disabled = !(command & PCI_COMMAND_IO);
 812                        else
 813                                disabled = !(command & PCI_COMMAND_MEMORY);
 814                        if (pass == disabled)
 815                                alloc_resource(dev, idx);
 816                }
 817                if (pass)
 818                        continue;
 819                r = &dev->resource[PCI_ROM_RESOURCE];
 820                if (r->flags) {
 821                        /* Turn the ROM off, leave the resource region,
 822                         * but keep it unregistered.
 823                         */
 824                        u32 reg;
 825                        pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 826                        if (reg & PCI_ROM_ADDRESS_ENABLE) {
 827                                pr_debug("PCI: Switching off ROM of %s\n",
 828                                         pci_name(dev));
 829                                r->flags &= ~IORESOURCE_ROM_ENABLE;
 830                                pci_write_config_dword(dev, dev->rom_base_reg,
 831                                                reg & ~PCI_ROM_ADDRESS_ENABLE);
 832                        }
 833                }
 834        }
 835}
 836
 837static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
 838{
 839        struct pci_controller *hose = pci_bus_to_host(bus);
 840        resource_size_t offset;
 841        struct resource *res, *pres;
 842        int i;
 843
 844        pr_debug("Reserving legacy ranges for domain %04x\n",
 845                                                        pci_domain_nr(bus));
 846
 847        /* Check for IO */
 848        if (!(hose->io_resource.flags & IORESOURCE_IO))
 849                goto no_io;
 850        offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 851        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
 852        BUG_ON(res == NULL);
 853        res->name = "Legacy IO";
 854        res->flags = IORESOURCE_IO;
 855        res->start = offset;
 856        res->end = (offset + 0xfff) & 0xfffffffful;
 857        pr_debug("Candidate legacy IO: %pR\n", res);
 858        if (request_resource(&hose->io_resource, res)) {
 859                pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
 860                       pci_domain_nr(bus), bus->number, res);
 861                kfree(res);
 862        }
 863
 864 no_io:
 865        /* Check for memory */
 866        offset = hose->pci_mem_offset;
 867        pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
 868        for (i = 0; i < 3; i++) {
 869                pres = &hose->mem_resources[i];
 870                if (!(pres->flags & IORESOURCE_MEM))
 871                        continue;
 872                pr_debug("hose mem res: %pR\n", pres);
 873                if ((pres->start - offset) <= 0xa0000 &&
 874                    (pres->end - offset) >= 0xbffff)
 875                        break;
 876        }
 877        if (i >= 3)
 878                return;
 879        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
 880        BUG_ON(res == NULL);
 881        res->name = "Legacy VGA memory";
 882        res->flags = IORESOURCE_MEM;
 883        res->start = 0xa0000 + offset;
 884        res->end = 0xbffff + offset;
 885        pr_debug("Candidate VGA memory: %pR\n", res);
 886        if (request_resource(pres, res)) {
 887                pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
 888                       pci_domain_nr(bus), bus->number, res);
 889                kfree(res);
 890        }
 891}
 892
 893void __init pcibios_resource_survey(void)
 894{
 895        struct pci_bus *b;
 896
 897        /* Allocate and assign resources. If we re-assign everything, then
 898         * we skip the allocate phase
 899         */
 900        list_for_each_entry(b, &pci_root_buses, node)
 901                pcibios_allocate_bus_resources(b);
 902
 903        pcibios_allocate_resources(0);
 904        pcibios_allocate_resources(1);
 905
 906        /* Before we start assigning unassigned resource, we try to reserve
 907         * the low IO area and the VGA memory area if they intersect the
 908         * bus available resources to avoid allocating things on top of them
 909         */
 910        list_for_each_entry(b, &pci_root_buses, node)
 911                pcibios_reserve_legacy_regions(b);
 912
 913        /* Now proceed to assigning things that were left unassigned */
 914        pr_debug("PCI: Assigning unassigned resources...\n");
 915        pci_assign_unassigned_resources();
 916}
 917
 918static void pcibios_setup_phb_resources(struct pci_controller *hose,
 919                                        struct list_head *resources)
 920{
 921        unsigned long io_offset;
 922        struct resource *res;
 923        int i;
 924
 925        /* Hookup PHB IO resource */
 926        res = &hose->io_resource;
 927
 928        /* Fixup IO space offset */
 929        io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
 930        res->start = (res->start + io_offset) & 0xffffffffu;
 931        res->end = (res->end + io_offset) & 0xffffffffu;
 932
 933        if (!res->flags) {
 934                pr_warn("PCI: I/O resource not set for host ");
 935                pr_cont("bridge %pOF (domain %d)\n",
 936                        hose->dn, hose->global_number);
 937                /* Workaround for lack of IO resource only on 32-bit */
 938                res->start = (unsigned long)hose->io_base_virt - isa_io_base;
 939                res->end = res->start + IO_SPACE_LIMIT;
 940                res->flags = IORESOURCE_IO;
 941        }
 942        pci_add_resource_offset(resources, res,
 943                (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
 944
 945        pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
 946                 (unsigned long long)res->start,
 947                 (unsigned long long)res->end,
 948                 (unsigned long)res->flags);
 949
 950        /* Hookup PHB Memory resources */
 951        for (i = 0; i < 3; ++i) {
 952                res = &hose->mem_resources[i];
 953                if (!res->flags) {
 954                        if (i > 0)
 955                                continue;
 956                        pr_err("PCI: Memory resource 0 not set for ");
 957                        pr_cont("host bridge %pOF (domain %d)\n",
 958                                hose->dn, hose->global_number);
 959
 960                        /* Workaround for lack of MEM resource only on 32-bit */
 961                        res->start = hose->pci_mem_offset;
 962                        res->end = (resource_size_t)-1LL;
 963                        res->flags = IORESOURCE_MEM;
 964
 965                }
 966                pci_add_resource_offset(resources, res, hose->pci_mem_offset);
 967
 968                pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
 969                        i, (unsigned long long)res->start,
 970                        (unsigned long long)res->end,
 971                        (unsigned long)res->flags);
 972        }
 973
 974        pr_debug("PCI: PHB MEM offset     = %016llx\n",
 975                 (unsigned long long)hose->pci_mem_offset);
 976        pr_debug("PCI: PHB IO  offset     = %08lx\n",
 977                 (unsigned long)hose->io_base_virt - _IO_BASE);
 978}
 979
 980static void pcibios_scan_phb(struct pci_controller *hose)
 981{
 982        LIST_HEAD(resources);
 983        struct pci_bus *bus;
 984        struct device_node *node = hose->dn;
 985
 986        pr_debug("PCI: Scanning PHB %pOF\n", node);
 987
 988        pcibios_setup_phb_resources(hose, &resources);
 989
 990        bus = pci_scan_root_bus(hose->parent, hose->first_busno,
 991                                hose->ops, hose, &resources);
 992        if (bus == NULL) {
 993                pr_err("Failed to create bus for PCI domain %04x\n",
 994                       hose->global_number);
 995                pci_free_resource_list(&resources);
 996                return;
 997        }
 998        bus->busn_res.start = hose->first_busno;
 999        hose->bus = bus;
1000
1001        hose->last_busno = bus->busn_res.end;
1002}
1003
1004static int __init pcibios_init(void)
1005{
1006        struct pci_controller *hose, *tmp;
1007        int next_busno = 0;
1008
1009        pr_info("PCI: Probing PCI hardware\n");
1010
1011        /* Scan all of the recorded PCI controllers.  */
1012        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1013                hose->last_busno = 0xff;
1014                pcibios_scan_phb(hose);
1015                if (next_busno <= hose->last_busno)
1016                        next_busno = hose->last_busno + 1;
1017        }
1018        pci_bus_count = next_busno;
1019
1020        /* Call common code to handle resource allocation */
1021        pcibios_resource_survey();
1022        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1023                if (hose->bus)
1024                        pci_bus_add_devices(hose->bus);
1025        }
1026
1027        return 0;
1028}
1029
1030subsys_initcall(pcibios_init);
1031
1032static struct pci_controller *pci_bus_to_hose(int bus)
1033{
1034        struct pci_controller *hose, *tmp;
1035
1036        list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1037                if (bus >= hose->first_busno && bus <= hose->last_busno)
1038                        return hose;
1039        return NULL;
1040}
1041
1042/* Provide information on locations of various I/O regions in physical
1043 * memory.  Do this on a per-card basis so that we choose the right
1044 * root bridge.
1045 * Note that the returned IO or memory base is a physical address
1046 */
1047
1048long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1049{
1050        struct pci_controller *hose;
1051        long result = -EOPNOTSUPP;
1052
1053        hose = pci_bus_to_hose(bus);
1054        if (!hose)
1055                return -ENODEV;
1056
1057        switch (which) {
1058        case IOBASE_BRIDGE_NUMBER:
1059                return (long)hose->first_busno;
1060        case IOBASE_MEMORY:
1061                return (long)hose->pci_mem_offset;
1062        case IOBASE_IO:
1063                return (long)hose->io_base_phys;
1064        case IOBASE_ISA_IO:
1065                return (long)isa_io_base;
1066        case IOBASE_ISA_MEM:
1067                return (long)isa_mem_base;
1068        }
1069
1070        return result;
1071}
1072
1073/*
1074 * Null PCI config access functions, for the case when we can't
1075 * find a hose.
1076 */
1077#define NULL_PCI_OP(rw, size, type)                                     \
1078static int                                                              \
1079null_##rw##_config_##size(struct pci_dev *dev, int offset, type val)    \
1080{                                                                       \
1081        return PCIBIOS_DEVICE_NOT_FOUND;                                \
1082}
1083
1084static int
1085null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1086                 int len, u32 *val)
1087{
1088        return PCIBIOS_DEVICE_NOT_FOUND;
1089}
1090
1091static int
1092null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1093                  int len, u32 val)
1094{
1095        return PCIBIOS_DEVICE_NOT_FOUND;
1096}
1097
1098static struct pci_ops null_pci_ops = {
1099        .read = null_read_config,
1100        .write = null_write_config,
1101};
1102
1103/*
1104 * These functions are used early on before PCI scanning is done
1105 * and all of the pci_dev and pci_bus structures have been created.
1106 */
1107static struct pci_bus *
1108fake_pci_bus(struct pci_controller *hose, int busnr)
1109{
1110        static struct pci_bus bus;
1111
1112        if (!hose)
1113                pr_err("Can't find hose for PCI bus %d!\n", busnr);
1114
1115        bus.number = busnr;
1116        bus.sysdata = hose;
1117        bus.ops = hose ? hose->ops : &null_pci_ops;
1118        return &bus;
1119}
1120
1121#define EARLY_PCI_OP(rw, size, type)                                    \
1122int early_##rw##_config_##size(struct pci_controller *hose, int bus,    \
1123                               int devfn, int offset, type value)       \
1124{                                                                       \
1125        return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus),    \
1126                                            devfn, offset, value);      \
1127}
1128
1129EARLY_PCI_OP(read, byte, u8 *)
1130EARLY_PCI_OP(read, word, u16 *)
1131EARLY_PCI_OP(read, dword, u32 *)
1132EARLY_PCI_OP(write, byte, u8)
1133EARLY_PCI_OP(write, word, u16)
1134EARLY_PCI_OP(write, dword, u32)
1135
1136int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1137                          int cap)
1138{
1139        return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1140}
1141
1142