linux/arch/sparc/kernel/head_32.S
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * head.S: The initial boot code for the Sparc port of Linux.
   4 *
   5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6 * Copyright (C) 1995,1999 Pete Zaitcev   (zaitcev@yahoo.com)
   7 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
   8 * Copyright (C) 1997 Jakub Jelinek   (jj@sunsite.mff.cuni.cz)
   9 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
  10 *
  11 * CompactPCI platform by Eric Brower, 1999.
  12 */
  13
  14#include <linux/version.h>
  15#include <linux/init.h>
  16
  17#include <asm/head.h>
  18#include <asm/asi.h>
  19#include <asm/contregs.h>
  20#include <asm/ptrace.h>
  21#include <asm/psr.h>
  22#include <asm/page.h>
  23#include <asm/kdebug.h>
  24#include <asm/winmacro.h>
  25#include <asm/thread_info.h>    /* TI_UWINMASK */
  26#include <asm/errno.h>
  27#include <asm/pgtsrmmu.h>       /* SRMMU_PGDIR_SHIFT */
  28#include <asm/export.h>
  29
  30        .data
  31/* The following are used with the prom_vector node-ops to figure out
  32 * the cpu-type
  33 */
  34        .align 4
  35        .globl cputypval
  36cputypval:
  37        .asciz "sun4m"
  38        .ascii "     "
  39
  40/* Tested on SS-5, SS-10 */
  41        .align 4
  42cputypvar:
  43        .asciz "compatible"
  44
  45        .align 4
  46
  47notsup:
  48        .asciz  "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
  49        .align 4
  50
  51sun4e_notsup:
  52        .asciz  "Sparc-Linux sun4e support does not exist\n\n"
  53        .align 4
  54
  55/* The trap-table - located in the __HEAD section */
  56#include "ttable_32.S"
  57
  58        .align PAGE_SIZE
  59
  60/* This was the only reasonable way I could think of to properly align
  61 * these page-table data structures.
  62 */
  63        .globl empty_zero_page
  64empty_zero_page:        .skip PAGE_SIZE
  65EXPORT_SYMBOL(empty_zero_page)
  66
  67        .global root_flags
  68        .global ram_flags
  69        .global root_dev
  70        .global sparc_ramdisk_image
  71        .global sparc_ramdisk_size
  72
  73/* This stuff has to be in sync with SILO and other potential boot loaders
  74 * Fields should be kept upward compatible and whenever any change is made,
  75 * HdrS version should be incremented.
  76 */
  77        .ascii  "HdrS"
  78        .word   LINUX_VERSION_CODE
  79        .half   0x0203          /* HdrS version */
  80root_flags:
  81        .half   1
  82root_dev:
  83        .half   0
  84ram_flags:
  85        .half   0
  86sparc_ramdisk_image:
  87        .word   0
  88sparc_ramdisk_size:
  89        .word   0
  90        .word   reboot_command
  91        .word   0, 0, 0
  92        .word   _end
  93
  94/* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
  95 * %g7 and at prom_vector_p. And also quickly check whether we are on
  96 * a v0, v2, or v3 prom.
  97 */
  98gokernel:
  99                /* Ok, it's nice to know, as early as possible, if we
 100                 * are already mapped where we expect to be in virtual
 101                 * memory.  The Solaris /boot elf format bootloader
 102                 * will peek into our elf header and load us where
 103                 * we want to be, otherwise we have to re-map.
 104                 *
 105                 * Some boot loaders don't place the jmp'rs address
 106                 * in %o7, so we do a pc-relative call to a local
 107                 * label, then see what %o7 has.
 108                 */
 109
 110                mov     %o7, %g4                ! Save %o7
 111
 112                /* Jump to it, and pray... */
 113current_pc:
 114                call    1f
 115                 nop
 116
 1171:
 118                mov     %o7, %g3
 119
 120                tst     %o0
 121                be      no_sun4u_here
 122                 mov    %g4, %o7                /* Previous %o7. */
 123
 124                mov     %o0, %l0                ! stash away romvec
 125                mov     %o0, %g7                ! put it here too
 126                mov     %o1, %l1                ! stash away debug_vec too
 127
 128                /* Ok, let's check out our run time program counter. */
 129                set     current_pc, %g5
 130                cmp     %g3, %g5
 131                be      already_mapped
 132                 nop
 133
 134                /* %l6 will hold the offset we have to subtract
 135                 * from absolute symbols in order to access areas
 136                 * in our own image.  If already mapped this is
 137                 * just plain zero, else it is KERNBASE.
 138                 */
 139                set     KERNBASE, %l6
 140                b       copy_prom_lvl14
 141                 nop
 142
 143already_mapped:
 144                mov     0, %l6
 145
 146                /* Copy over the Prom's level 14 clock handler. */
 147copy_prom_lvl14:
 148#if 1
 149                /* DJHR
 150                 * preserve our linked/calculated instructions
 151                 */
 152                set     lvl14_save, %g1
 153                set     t_irq14, %g3
 154                sub     %g1, %l6, %g1           ! translate to physical
 155                sub     %g3, %l6, %g3           ! translate to physical
 156                ldd     [%g3], %g4
 157                std     %g4, [%g1]
 158                ldd     [%g3+8], %g4
 159                std     %g4, [%g1+8]
 160#endif
 161                rd      %tbr, %g1
 162                andn    %g1, 0xfff, %g1         ! proms trap table base
 163                or      %g0, (0x1e<<4), %g2     ! offset to lvl14 intr
 164                or      %g1, %g2, %g2
 165                set     t_irq14, %g3
 166                sub     %g3, %l6, %g3
 167                ldd     [%g2], %g4
 168                std     %g4, [%g3]
 169                ldd     [%g2 + 0x8], %g4
 170                std     %g4, [%g3 + 0x8]        ! Copy proms handler
 171
 172/* DON'T TOUCH %l0 thru %l5 in these remapping routines,
 173 * we need their values afterwards!
 174 */
 175
 176                /* Now check whether we are already mapped, if we
 177                 * are we can skip all this garbage coming up.
 178                 */
 179copy_prom_done:
 180                cmp     %l6, 0
 181                be      go_to_highmem           ! this will be a nop then
 182                 nop
 183
 184                /* Validate that we are in fact running on an
 185                 * SRMMU based cpu.
 186                 */
 187                set     0x4000, %g6
 188                cmp     %g7, %g6
 189                bne     not_a_sun4
 190                 nop
 191
 192halt_notsup:
 193                ld      [%g7 + 0x68], %o1
 194                set     notsup, %o0
 195                sub     %o0, %l6, %o0
 196                call    %o1
 197                 nop
 198                ba      halt_me
 199                 nop
 200
 201not_a_sun4:
 202                /* It looks like this is a machine we support.
 203                 * Now find out what MMU we are dealing with
 204                 * LEON - identified by the psr.impl field
 205                 * Viking - identified by the psr.impl field
 206                 * In all other cases a sun4m srmmu.
 207                 * We check that the MMU is enabled in all cases.
 208                 */
 209
 210                /* Check if this is a LEON CPU */
 211                rd      %psr, %g3
 212                srl     %g3, PSR_IMPL_SHIFT, %g3
 213                and     %g3, PSR_IMPL_SHIFTED_MASK, %g3
 214                cmp     %g3, PSR_IMPL_LEON
 215                be      leon_remap              /* It is a LEON - jump */
 216                 nop
 217
 218                /* Sanity-check, is MMU enabled */
 219                lda     [%g0] ASI_M_MMUREGS, %g1
 220                andcc   %g1, 1, %g0
 221                be      halt_notsup
 222                 nop
 223
 224                /* Check for a viking (TI) module. */
 225                cmp     %g3, PSR_IMPL_TI
 226                bne     srmmu_not_viking
 227                 nop
 228
 229                /* Figure out what kind of viking we are on.
 230                 * We need to know if we have to play with the
 231                 * AC bit and disable traps or not.
 232                 */
 233
 234                /* I've only seen MicroSparc's on SparcClassics with this
 235                 * bit set.
 236                 */
 237                set     0x800, %g2
 238                lda     [%g0] ASI_M_MMUREGS, %g3        ! peek in the control reg
 239                and     %g2, %g3, %g3
 240                subcc   %g3, 0x0, %g0
 241                bnz     srmmu_not_viking                        ! is in mbus mode
 242                 nop
 243
 244                rd      %psr, %g3                       ! DO NOT TOUCH %g3
 245                andn    %g3, PSR_ET, %g2
 246                wr      %g2, 0x0, %psr
 247                WRITE_PAUSE
 248
 249                /* Get context table pointer, then convert to
 250                 * a physical address, which is 36 bits.
 251                 */
 252                set     AC_M_CTPR, %g4
 253                lda     [%g4] ASI_M_MMUREGS, %g4
 254                sll     %g4, 0x4, %g4                   ! We use this below
 255                                                        ! DO NOT TOUCH %g4
 256
 257                /* Set the AC bit in the Viking's MMU control reg. */
 258                lda     [%g0] ASI_M_MMUREGS, %g5        ! DO NOT TOUCH %g5
 259                set     0x8000, %g6                     ! AC bit mask
 260                or      %g5, %g6, %g6                   ! Or it in...
 261                sta     %g6, [%g0] ASI_M_MMUREGS        ! Close your eyes...
 262
 263                /* Grrr, why does it seem like every other load/store
 264                 * on the sun4m is in some ASI space...
 265                 * Fine with me, let's get the pointer to the level 1
 266                 * page table directory and fetch its entry.
 267                 */
 268                lda     [%g4] ASI_M_BYPASS, %o1         ! This is a level 1 ptr
 269                srl     %o1, 0x4, %o1                   ! Clear low 4 bits
 270                sll     %o1, 0x8, %o1                   ! Make physical
 271
 272                /* Ok, pull in the PTD. */
 273                lda     [%o1] ASI_M_BYPASS, %o2         ! This is the 0x0 16MB pgd
 274
 275                /* Calculate to KERNBASE entry. */
 276                add     %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3
 277
 278                /* Poke the entry into the calculated address. */
 279                sta     %o2, [%o3] ASI_M_BYPASS
 280
 281                /* I don't get it Sun, if you engineered all these
 282                 * boot loaders and the PROM (thank you for the debugging
 283                 * features btw) why did you not have them load kernel
 284                 * images up in high address space, since this is necessary
 285                 * for ABI compliance anyways?  Does this low-mapping provide
 286                 * enhanced interoperability?
 287                 *
 288                 * "The PROM is the computer."
 289                 */
 290
 291                /* Ok, restore the MMU control register we saved in %g5 */
 292                sta     %g5, [%g0] ASI_M_MMUREGS        ! POW... ouch
 293
 294                /* Turn traps back on.  We saved it in %g3 earlier. */
 295                wr      %g3, 0x0, %psr                  ! tick tock, tick tock
 296
 297                /* Now we burn precious CPU cycles due to bad engineering. */
 298                WRITE_PAUSE
 299
 300                /* Wow, all that just to move a 32-bit value from one
 301                 * place to another...  Jump to high memory.
 302                 */
 303                b       go_to_highmem
 304                 nop
 305
 306srmmu_not_viking:
 307                /* This works on viking's in Mbus mode and all
 308                 * other MBUS modules.  It is virtually the same as
 309                 * the above madness sans turning traps off and flipping
 310                 * the AC bit.
 311                 */
 312                set     AC_M_CTPR, %g1
 313                lda     [%g1] ASI_M_MMUREGS, %g1        ! get ctx table ptr
 314                sll     %g1, 0x4, %g1                   ! make physical addr
 315                lda     [%g1] ASI_M_BYPASS, %g1         ! ptr to level 1 pg_table
 316                srl     %g1, 0x4, %g1
 317                sll     %g1, 0x8, %g1                   ! make phys addr for l1 tbl
 318
 319                lda     [%g1] ASI_M_BYPASS, %g2         ! get level1 entry for 0x0
 320                add     %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
 321                sta     %g2, [%g3] ASI_M_BYPASS         ! place at KERNBASE entry
 322                b       go_to_highmem
 323                 nop                                    ! wheee....
 324
 325
 326leon_remap:
 327                /* Sanity-check, is MMU enabled */
 328                lda     [%g0] ASI_LEON_MMUREGS, %g1
 329                andcc   %g1, 1, %g0
 330                be      halt_notsup
 331                 nop
 332
 333                /* Same code as in the srmmu_not_viking case,
 334                 * with the LEON ASI for mmuregs
 335                 */
 336                set     AC_M_CTPR, %g1
 337                lda     [%g1] ASI_LEON_MMUREGS, %g1     ! get ctx table ptr
 338                sll     %g1, 0x4, %g1                   ! make physical addr
 339                lda     [%g1] ASI_M_BYPASS, %g1         ! ptr to level 1 pg_table
 340                srl     %g1, 0x4, %g1
 341                sll     %g1, 0x8, %g1                   ! make phys addr for l1 tbl
 342
 343                lda     [%g1] ASI_M_BYPASS, %g2         ! get level1 entry for 0x0
 344                add     %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
 345                sta     %g2, [%g3] ASI_M_BYPASS         ! place at KERNBASE entry
 346                b       go_to_highmem
 347                 nop                                    ! wheee....
 348
 349/* Now do a non-relative jump so that PC is in high-memory */
 350go_to_highmem:
 351                set     execute_in_high_mem, %g1
 352                jmpl    %g1, %g0
 353                 nop
 354
 355/* The code above should be at beginning and we have to take care about
 356 * short jumps, as branching to .init.text section from .text is usually
 357 * impossible */
 358                __INIT
 359/* Acquire boot time privileged register values, this will help debugging.
 360 * I figure out and store nwindows and nwindowsm1 later on.
 361 */
 362execute_in_high_mem:
 363                mov     %l0, %o0                ! put back romvec
 364                mov     %l1, %o1                ! and debug_vec
 365
 366                sethi   %hi(prom_vector_p), %g1
 367                st      %o0, [%g1 + %lo(prom_vector_p)]
 368
 369                sethi   %hi(linux_dbvec), %g1
 370                st      %o1, [%g1 + %lo(linux_dbvec)]
 371
 372                /* Get the machine type via the romvec
 373                 * getprops node operation
 374                 */
 375                add     %g7, 0x1c, %l1
 376                ld      [%l1], %l0
 377                ld      [%l0], %l0
 378                call    %l0
 379                 or     %g0, %g0, %o0           ! next_node(0) = first_node
 380                or      %o0, %g0, %g6
 381
 382                sethi   %hi(cputypvar), %o1     ! First node has cpu-arch
 383                or      %o1, %lo(cputypvar), %o1
 384                sethi   %hi(cputypval), %o2     ! information, the string
 385                or      %o2, %lo(cputypval), %o2
 386                ld      [%l1], %l0              ! 'compatible' tells
 387                ld      [%l0 + 0xc], %l0        ! that we want 'sun4x' where
 388                call    %l0                     ! x is one of 'm', 'd' or 'e'.
 389                 nop                            ! %o2 holds pointer
 390                                                ! to a buf where above string
 391                                                ! will get stored by the prom.
 392
 393
 394                /* Check value of "compatible" property.
 395                 * "value" => "model"
 396                 * leon => sparc_leon
 397                 * sun4m => sun4m
 398                 * sun4s => sun4m
 399                 * sun4d => sun4d
 400                 * sun4e => "no_sun4e_here"
 401                 * '*'   => "no_sun4u_here"
 402                 * Check single letters only
 403                 */
 404
 405                set     cputypval, %o2
 406                /* If cputypval[0] == 'l' (lower case letter L) this is leon */
 407                ldub    [%o2], %l1
 408                cmp     %l1, 'l'
 409                be      leon_init
 410                 nop
 411
 412                /* Check cputypval[4] to find the sun model */
 413                ldub    [%o2 + 0x4], %l1
 414
 415                cmp     %l1, 'm'
 416                be      sun4m_init
 417                 cmp    %l1, 's'
 418                be      sun4m_init
 419                 cmp    %l1, 'd'
 420                be      sun4d_init
 421                 cmp    %l1, 'e'
 422                be      no_sun4e_here           ! Could be a sun4e.
 423                 nop
 424                b       no_sun4u_here           ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
 425                 nop
 426
 427leon_init:
 428                /* LEON CPU - set boot_cpu_id */
 429                sethi   %hi(boot_cpu_id), %g2   ! boot-cpu index
 430
 431#ifdef CONFIG_SMP
 432                ldub    [%g2 + %lo(boot_cpu_id)], %g1
 433                cmp     %g1, 0xff               ! unset means first CPU
 434                bne     leon_smp_cpu_startup    ! continue only with master
 435                 nop
 436#endif
 437                /* Get CPU-ID from most significant 4-bit of ASR17 */
 438                rd     %asr17, %g1
 439                srl    %g1, 28, %g1
 440
 441                /* Update boot_cpu_id only on boot cpu */
 442                stub    %g1, [%g2 + %lo(boot_cpu_id)]
 443
 444                ba continue_boot
 445                 nop
 446
 447/* CPUID in bootbus can be found at PA 0xff0140000 */
 448#define SUN4D_BOOTBUS_CPUID     0xf0140000
 449
 450sun4d_init:
 451        /* Need to patch call to handler_irq */
 452        set     patch_handler_irq, %g4
 453        set     sun4d_handler_irq, %g5
 454        sethi   %hi(0x40000000), %g3            ! call
 455        sub     %g5, %g4, %g5
 456        srl     %g5, 2, %g5
 457        or      %g5, %g3, %g5
 458        st      %g5, [%g4]
 459
 460#ifdef CONFIG_SMP
 461        /* Get our CPU id out of bootbus */
 462        set     SUN4D_BOOTBUS_CPUID, %g3
 463        lduba   [%g3] ASI_M_CTL, %g3
 464        and     %g3, 0xf8, %g3
 465        srl     %g3, 3, %g4
 466        sta     %g4, [%g0] ASI_M_VIKING_TMP1
 467        sethi   %hi(boot_cpu_id), %g5
 468        stb     %g4, [%g5 + %lo(boot_cpu_id)]
 469#endif
 470
 471        /* Fall through to sun4m_init */
 472
 473sun4m_init:
 474/* Ok, the PROM could have done funny things and apple cider could still
 475 * be sitting in the fault status/address registers.  Read them all to
 476 * clear them so we don't get magic faults later on.
 477 */
 478/* This sucks, apparently this makes Vikings call prom panic, will fix later */
 4792:
 480                rd      %psr, %o1
 481                srl     %o1, PSR_IMPL_SHIFT, %o1        ! Get a type of the CPU
 482
 483                subcc   %o1, PSR_IMPL_TI, %g0           ! TI: Viking or MicroSPARC
 484                be      continue_boot
 485                 nop
 486
 487                set     AC_M_SFSR, %o0
 488                lda     [%o0] ASI_M_MMUREGS, %g0
 489                set     AC_M_SFAR, %o0
 490                lda     [%o0] ASI_M_MMUREGS, %g0
 491
 492                /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
 493                subcc   %o1, 0, %g0
 494                be      continue_boot
 495                 nop
 496
 497                set     AC_M_AFSR, %o0
 498                lda     [%o0] ASI_M_MMUREGS, %g0
 499                set     AC_M_AFAR, %o0
 500                lda     [%o0] ASI_M_MMUREGS, %g0
 501                 nop
 502
 503
 504continue_boot:
 505
 506/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
 507 * show-time!
 508 */
 509                /* Turn on Supervisor, EnableFloating, and all the PIL bits.
 510                 * Also puts us in register window zero with traps off.
 511                 */
 512                set     (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
 513                wr      %g2, 0x0, %psr
 514                WRITE_PAUSE
 515
 516                /* I want a kernel stack NOW! */
 517                set     init_thread_union, %g1
 518                set     (THREAD_SIZE - STACKFRAME_SZ), %g2
 519                add     %g1, %g2, %sp
 520                mov     0, %fp                  /* And for good luck */
 521
 522                /* Zero out our BSS section. */
 523                set     __bss_start , %o0       ! First address of BSS
 524                set     _end , %o1              ! Last address of BSS
 525                add     %o0, 0x1, %o0
 5261:
 527                stb     %g0, [%o0]
 528                subcc   %o0, %o1, %g0
 529                bl      1b
 530                 add    %o0, 0x1, %o0
 531
 532                /* If boot_cpu_id has not been setup by machine specific
 533                 * init-code above we default it to zero.
 534                 */
 535                sethi   %hi(boot_cpu_id), %g2
 536                ldub    [%g2 + %lo(boot_cpu_id)], %g3
 537                cmp     %g3, 0xff
 538                bne     1f
 539                 nop
 540                mov     %g0, %g3
 541                stub    %g3, [%g2 + %lo(boot_cpu_id)]
 542
 5431:              sll     %g3, 2, %g3
 544
 545                /* Initialize the uwinmask value for init task just in case.
 546                 * But first make current_set[boot_cpu_id] point to something useful.
 547                 */
 548                set     init_thread_union, %g6
 549                set     current_set, %g2
 550#ifdef CONFIG_SMP
 551                st      %g6, [%g2]
 552                add     %g2, %g3, %g2
 553#endif
 554                st      %g6, [%g2]
 555
 556                st      %g0, [%g6 + TI_UWINMASK]
 557
 558/* Compute NWINDOWS and stash it away. Now uses %wim trick explained
 559 * in the V8 manual. Ok, this method seems to work, Sparc is cool...
 560 * No, it doesn't work, have to play the save/readCWP/restore trick.
 561 */
 562
 563                wr      %g0, 0x0, %wim                  ! so we do not get a trap
 564                WRITE_PAUSE
 565
 566                save
 567
 568                rd      %psr, %g3
 569
 570                restore
 571
 572                and     %g3, 0x1f, %g3
 573                add     %g3, 0x1, %g3
 574
 575                mov     2, %g1
 576                wr      %g1, 0x0, %wim                  ! make window 1 invalid
 577                WRITE_PAUSE
 578
 579                cmp     %g3, 0x7
 580                bne     2f
 581                 nop
 582
 583                /* Adjust our window handling routines to
 584                 * do things correctly on 7 window Sparcs.
 585                 */
 586
 587#define         PATCH_INSN(src, dest) \
 588                set     src, %g5; \
 589                set     dest, %g2; \
 590                ld      [%g5], %g4; \
 591                st      %g4, [%g2];
 592
 593                /* Patch for window spills... */
 594                PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
 595                PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
 596                PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
 597
 598                /* Patch for window fills... */
 599                PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
 600                PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
 601
 602                /* Patch for trap entry setup... */
 603                PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
 604                PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
 605                PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
 606                PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
 607                PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
 608                PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
 609
 610                /* Patch for returning from traps... */
 611                PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
 612                PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
 613                PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
 614                PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
 615                PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
 616
 617                /* Patch for killing user windows from the register file. */
 618                PATCH_INSN(kuw_patch1_7win, kuw_patch1)
 619
 620                /* Now patch the kernel window flush sequences.
 621                 * This saves 2 traps on every switch and fork.
 622                 */
 623                set     0x01000000, %g4
 624                set     flush_patch_one, %g5
 625                st      %g4, [%g5 + 0x18]
 626                st      %g4, [%g5 + 0x1c]
 627                set     flush_patch_two, %g5
 628                st      %g4, [%g5 + 0x18]
 629                st      %g4, [%g5 + 0x1c]
 630                set     flush_patch_three, %g5
 631                st      %g4, [%g5 + 0x18]
 632                st      %g4, [%g5 + 0x1c]
 633                set     flush_patch_four, %g5
 634                st      %g4, [%g5 + 0x18]
 635                st      %g4, [%g5 + 0x1c]
 636                set     flush_patch_exception, %g5
 637                st      %g4, [%g5 + 0x18]
 638                st      %g4, [%g5 + 0x1c]
 639                set     flush_patch_switch, %g5
 640                st      %g4, [%g5 + 0x18]
 641                st      %g4, [%g5 + 0x1c]
 642
 6432:
 644                sethi   %hi(nwindows), %g4
 645                st      %g3, [%g4 + %lo(nwindows)]      ! store final value
 646                sub     %g3, 0x1, %g3
 647                sethi   %hi(nwindowsm1), %g4
 648                st      %g3, [%g4 + %lo(nwindowsm1)]
 649
 650                /* Here we go, start using Linux's trap table... */
 651                set     trapbase, %g3
 652                wr      %g3, 0x0, %tbr
 653                WRITE_PAUSE
 654
 655                /* Finally, turn on traps so that we can call c-code. */
 656                rd      %psr, %g3
 657                wr      %g3, 0x0, %psr
 658                WRITE_PAUSE
 659
 660                wr      %g3, PSR_ET, %psr
 661                WRITE_PAUSE
 662
 663                /* Call sparc32_start_kernel(struct linux_romvec *rp) */
 664                sethi   %hi(prom_vector_p), %g5
 665                ld      [%g5 + %lo(prom_vector_p)], %o0
 666                call    sparc32_start_kernel
 667                 nop
 668
 669                /* We should not get here. */
 670                call    halt_me
 671                 nop
 672
 673no_sun4e_here:
 674                ld      [%g7 + 0x68], %o1
 675                set     sun4e_notsup, %o0
 676                call    %o1
 677                 nop
 678                b       halt_me
 679                 nop
 680
 681                __INITDATA
 682
 683sun4u_1:
 684                .asciz "finddevice"
 685                .align  4
 686sun4u_2:
 687                .asciz "/chosen"
 688                .align  4
 689sun4u_3:
 690                .asciz "getprop"
 691                .align  4
 692sun4u_4:
 693                .asciz "stdout"
 694                .align  4
 695sun4u_5:
 696                .asciz "write"
 697                .align  4
 698sun4u_6:
 699                .asciz  "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r"
 700sun4u_6e:
 701                .align  4
 702sun4u_7:
 703                .asciz "exit"
 704                .align  8
 705sun4u_a1:
 706                .word   0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
 707sun4u_r1:
 708                .word   0
 709sun4u_a2:
 710                .word   0, sun4u_3, 0, 4, 0, 1, 0
 711sun4u_i2:
 712                .word   0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
 713sun4u_r2:
 714                .word   0
 715sun4u_a3:
 716                .word   0, sun4u_5, 0, 3, 0, 1, 0
 717sun4u_i3:
 718                .word   0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
 719sun4u_r3:
 720                .word   0
 721sun4u_a4:
 722                .word   0, sun4u_7, 0, 0, 0, 0
 723sun4u_r4:
 724
 725                __INIT
 726no_sun4u_here:
 727                set     sun4u_a1, %o0
 728                set     current_pc, %l2
 729                cmp     %l2, %g3
 730                be      1f
 731                 mov    %o4, %l0
 732                sub     %g3, %l2, %l6
 733                add     %o0, %l6, %o0
 734                mov     %o0, %l4
 735                mov     sun4u_r4 - sun4u_a1, %l3
 736                ld      [%l4], %l5
 7372:
 738                add     %l4, 4, %l4
 739                cmp     %l5, %l2
 740                add     %l5, %l6, %l5
 741                bgeu,a  3f
 742                 st     %l5, [%l4 - 4]
 7433:
 744                subcc   %l3, 4, %l3
 745                bne     2b
 746                 ld     [%l4], %l5
 7471:
 748                call    %l0
 749                 mov    %o0, %l1
 750
 751                ld      [%l1 + (sun4u_r1 - sun4u_a1)], %o1
 752                add     %l1, (sun4u_a2 - sun4u_a1), %o0
 753                call    %l0
 754                 st     %o1, [%o0 + (sun4u_i2 - sun4u_a2)]
 755
 756                ld      [%l1 + (sun4u_1 - sun4u_a1)], %o1
 757                add     %l1, (sun4u_a3 - sun4u_a1), %o0
 758                call    %l0
 759                st      %o1, [%o0 + (sun4u_i3 - sun4u_a3)]
 760
 761                call    %l0
 762                 add    %l1, (sun4u_a4 - sun4u_a1), %o0
 763
 764                /* Not reached */
 765halt_me:
 766                ld      [%g7 + 0x74], %o0
 767                call    %o0                     ! Get us out of here...
 768                 nop                            ! Apparently Solaris is better.
 769
 770/* Ok, now we continue in the .data/.text sections */
 771
 772        .data
 773        .align 4
 774
 775/*
 776 * Fill up the prom vector, note in particular the kind first element,
 777 * no joke. I don't need all of them in here as the entire prom vector
 778 * gets initialized in c-code so all routines can use it.
 779 */
 780
 781prom_vector_p:
 782                .word 0
 783
 784/* We calculate the following at boot time, window fills/spills and trap entry
 785 * code uses these to keep track of the register windows.
 786 */
 787
 788        .align 4
 789        .globl  nwindows
 790        .globl  nwindowsm1
 791nwindows:
 792        .word   8
 793nwindowsm1:
 794        .word   7
 795
 796/* Boot time debugger vector value.  We need this later on. */
 797
 798        .align 4
 799        .globl  linux_dbvec
 800linux_dbvec:
 801        .word   0
 802        .word   0
 803
 804        .align 8
 805
 806        .globl  lvl14_save
 807lvl14_save:
 808        .word   0
 809        .word   0
 810        .word   0
 811        .word   0
 812        .word   t_irq14
 813