LXR linux/arch/xtensa/include/asm/pgtable.h

   1/*
   2 * include/asm-xtensa/pgtable.h
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * Copyright (C) 2001 - 2013 Tensilica Inc.
   9 */
  10
  11#ifndef _XTENSA_PGTABLE_H
  12#define _XTENSA_PGTABLE_H
  13
  14#define __ARCH_USE_5LEVEL_HACK
  15#include <asm/page.h>
  16#include <asm/kmem_layout.h>
  17#include <asm-generic/pgtable-nopmd.h>
  18
  19/*
  20 * We only use two ring levels, user and kernel space.
  21 */
  22
  23#ifdef CONFIG_MMU
  24#define USER_RING               1       /* user ring level */
  25#else
  26#define USER_RING               0
  27#endif
  28#define KERNEL_RING             0       /* kernel ring level */
  29
  30/*
  31 * The Xtensa architecture port of Linux has a two-level page table system,
  32 * i.e. the logical three-level Linux page table layout is folded.
  33 * Each task has the following memory page tables:
  34 *
  35 *   PGD table (page directory), ie. 3rd-level page table:
  36 *      One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
  37 *      (Architectures that don't have the PMD folded point to the PMD tables)
  38 *
  39 *      The pointer to the PGD table for a given task can be retrieved from
  40 *      the task structure (struct task_struct*) t, e.g. current():
  41 *        (t->mm ? t->mm : t->active_mm)->pgd
  42 *
  43 *   PMD tables (page middle-directory), ie. 2nd-level page tables:
  44 *      Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
  45 *
  46 *   PTE tables (page table entry), ie. 1st-level page tables:
  47 *      One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
  48 *      invalid_pte_table for absent mappings.
  49 *
  50 * The individual pages are 4 kB big with special pages for the empty_zero_page.
  51 */
  52
  53#define PGDIR_SHIFT     22
  54#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  55#define PGDIR_MASK      (~(PGDIR_SIZE-1))
  56
  57/*
  58 * Entries per page directory level: we use two-level, so
  59 * we don't really have any PMD directory physically.
  60 */
  61#define PTRS_PER_PTE            1024
  62#define PTRS_PER_PTE_SHIFT      10
  63#define PTRS_PER_PGD            1024
  64#define PGD_ORDER               0
  65#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  66#define FIRST_USER_ADDRESS      0UL
  67#define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
  68
  69/*
  70 * Virtual memory area. We keep a distance to other memory regions to be
  71 * on the safe side. We also use this area for cache aliasing.
  72 */
  73#define VMALLOC_START           (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
  74#define VMALLOC_END             (VMALLOC_START + 0x07FEFFFF)
  75#define TLBTEMP_BASE_1          (VMALLOC_END + 1)
  76#define TLBTEMP_BASE_2          (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
  77#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
  78#define TLBTEMP_SIZE            (2 * DCACHE_WAY_SIZE)
  79#else
  80#define TLBTEMP_SIZE            ICACHE_WAY_SIZE
  81#endif
  82
  83/*
  84 * For the Xtensa architecture, the PTE layout is as follows:
  85 *
  86 *              31------12  11  10-9   8-6  5-4  3-2  1-0
  87 *              +-----------------------------------------+
  88 *              |           |   Software   |   HARDWARE   |
  89 *              |    PPN    |          ADW | RI |Attribute|
  90 *              +-----------------------------------------+
  91 *   pte_none   |             MBZ          | 01 | 11 | 00 |
  92 *              +-----------------------------------------+
  93 *   present    |    PPN    | 0 | 00 | ADW | RI | CA | wx |
  94 *              +- - - - - - - - - - - - - - - - - - - - -+
  95 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 11 | 11 |
  96 *              +-----------------------------------------+
  97 *   swap       |     index     |   type   | 01 | 11 | 00 |
  98 *              +-----------------------------------------+
  99 *
 100 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
 101 *              +-----------------------------------------+
 102 *   present    |    PPN    | 0 | 00 | ADW | RI | CA | w1 |
 103 *              +-----------------------------------------+
 104 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 01 | 00 |
 105 *              +-----------------------------------------+
 106 *
 107 *  Legend:
 108 *   PPN        Physical Page Number
 109 *   ADW        software: accessed (young) / dirty / writable
 110 *   RI         ring (0=privileged, 1=user, 2 and 3 are unused)
 111 *   CA         cache attribute: 00 bypass, 01 writeback, 10 writethrough
 112 *              (11 is invalid and used to mark pages that are not present)
 113 *   w          page is writable (hw)
 114 *   x          page is executable (hw)
 115 *   index      swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
 116 *              (note that the index is always non-zero)
 117 *   type       swap type (5 bits -> 32 types)
 118 *
 119 *  Notes:
 120 *   - (PROT_NONE) is a special case of 'present' but causes an exception for
 121 *     any access (read, write, and execute).
 122 *   - 'multihit-exception' has the highest priority of all MMU exceptions,
 123 *     so the ring must be set to 'RING_USER' even for 'non-present' pages.
 124 *   - on older hardware, the exectuable flag was not supported and
 125 *     used as a 'valid' flag, so it needs to be always set.
 126 *   - we need to keep track of certain flags in software (dirty and young)
 127 *     to do this, we use write exceptions and have a separate software w-flag.
 128 *   - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
 129 */
 130
 131#define _PAGE_ATTRIB_MASK       0xf
 132
 133#define _PAGE_HW_EXEC           (1<<0)  /* hardware: page is executable */
 134#define _PAGE_HW_WRITE          (1<<1)  /* hardware: page is writable */
 135
 136#define _PAGE_CA_BYPASS         (0<<2)  /* bypass, non-speculative */
 137#define _PAGE_CA_WB             (1<<2)  /* write-back */
 138#define _PAGE_CA_WT             (2<<2)  /* write-through */
 139#define _PAGE_CA_MASK           (3<<2)
 140#define _PAGE_CA_INVALID        (3<<2)
 141
 142/* We use invalid attribute values to distinguish special pte entries */
 143#if XCHAL_HW_VERSION_MAJOR < 2000
 144#define _PAGE_HW_VALID          0x01    /* older HW needed this bit set */
 145#define _PAGE_NONE              0x04
 146#else
 147#define _PAGE_HW_VALID          0x00
 148#define _PAGE_NONE              0x0f
 149#endif
 150
 151#define _PAGE_USER              (1<<4)  /* user access (ring=1) */
 152
 153/* Software */
 154#define _PAGE_WRITABLE_BIT      6
 155#define _PAGE_WRITABLE          (1<<6)  /* software: page writable */
 156#define _PAGE_DIRTY             (1<<7)  /* software: page dirty */
 157#define _PAGE_ACCESSED          (1<<8)  /* software: page accessed (read) */
 158
 159#ifdef CONFIG_MMU
 160
 161#define _PAGE_CHG_MASK     (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 162#define _PAGE_PRESENT      (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
 163
 164#define PAGE_NONE          __pgprot(_PAGE_NONE | _PAGE_USER)
 165#define PAGE_COPY          __pgprot(_PAGE_PRESENT | _PAGE_USER)
 166#define PAGE_COPY_EXEC     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 167#define PAGE_READONLY      __pgprot(_PAGE_PRESENT | _PAGE_USER)
 168#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 169#define PAGE_SHARED        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
 170#define PAGE_SHARED_EXEC \
 171        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
 172#define PAGE_KERNEL        __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
 173#define PAGE_KERNEL_RO     __pgprot(_PAGE_PRESENT)
 174#define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
 175
 176#if (DCACHE_WAY_SIZE > PAGE_SIZE)
 177# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
 178#else
 179# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
 180#endif
 181
 182#else /* no mmu */
 183
 184# define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 185# define PAGE_NONE       __pgprot(0)
 186# define PAGE_SHARED     __pgprot(0)
 187# define PAGE_COPY       __pgprot(0)
 188# define PAGE_READONLY   __pgprot(0)
 189# define PAGE_KERNEL     __pgprot(0)
 190
 191#endif
 192
 193/*
 194 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 195 * the MMU can't do page protection for execute, and considers that the same as
 196 * read.  Also, write permissions may imply read permissions.
 197 * What follows is the closest we can get by reasonable means..
 198 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 199 */
 200#define __P000  PAGE_NONE               /* private --- */
 201#define __P001  PAGE_READONLY           /* private --r */
 202#define __P010  PAGE_COPY               /* private -w- */
 203#define __P011  PAGE_COPY               /* private -wr */
 204#define __P100  PAGE_READONLY_EXEC      /* private x-- */
 205#define __P101  PAGE_READONLY_EXEC      /* private x-r */
 206#define __P110  PAGE_COPY_EXEC          /* private xw- */
 207#define __P111  PAGE_COPY_EXEC          /* private xwr */
 208
 209#define __S000  PAGE_NONE               /* shared  --- */
 210#define __S001  PAGE_READONLY           /* shared  --r */
 211#define __S010  PAGE_SHARED             /* shared  -w- */
 212#define __S011  PAGE_SHARED             /* shared  -wr */
 213#define __S100  PAGE_READONLY_EXEC      /* shared  x-- */
 214#define __S101  PAGE_READONLY_EXEC      /* shared  x-r */
 215#define __S110  PAGE_SHARED_EXEC        /* shared  xw- */
 216#define __S111  PAGE_SHARED_EXEC        /* shared  xwr */
 217
 218#ifndef __ASSEMBLY__
 219
 220#define pte_ERROR(e) \
 221        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 222#define pgd_ERROR(e) \
 223        printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 224
 225extern unsigned long empty_zero_page[1024];
 226
 227#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 228
 229#ifdef CONFIG_MMU
 230extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
 231extern void paging_init(void);
 232#else
 233# define swapper_pg_dir NULL
 234static inline void paging_init(void) { }
 235#endif
 236static inline void pgtable_cache_init(void) { }
 237
 238/*
 239 * The pmd contains the kernel virtual address of the pte page.
 240 */
 241#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
 242#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
 243
 244/*
 245 * pte status.
 246 */
 247# define pte_none(pte)   (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
 248#if XCHAL_HW_VERSION_MAJOR < 2000
 249# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
 250#else
 251# define pte_present(pte)                                               \
 252        (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)           \
 253         || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
 254#endif
 255#define pte_clear(mm,addr,ptep)                                         \
 256        do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
 257
 258#define pmd_none(pmd)    (!pmd_val(pmd))
 259#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
 260#define pmd_bad(pmd)     (pmd_val(pmd) & ~PAGE_MASK)
 261#define pmd_clear(pmdp)  do { set_pmd(pmdp, __pmd(0)); } while (0)
 262
 263static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
 264static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
 265static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
 266static inline int pte_special(pte_t pte) { return 0; }
 267
 268static inline pte_t pte_wrprotect(pte_t pte)    
 269        { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
 270static inline pte_t pte_mkclean(pte_t pte)
 271        { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
 272static inline pte_t pte_mkold(pte_t pte)
 273        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 274static inline pte_t pte_mkdirty(pte_t pte)
 275        { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 276static inline pte_t pte_mkyoung(pte_t pte)
 277        { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 278static inline pte_t pte_mkwrite(pte_t pte)
 279        { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
 280static inline pte_t pte_mkspecial(pte_t pte)
 281        { return pte; }
 282
 283#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))
 284
 285/*
 286 * Conversion functions: convert a page and protection to a page entry,
 287 * and a page entry and page directory to the page they refer to.
 288 */
 289
 290#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 291#define pte_same(a,b)           (pte_val(a) == pte_val(b))
 292#define pte_page(x)             pfn_to_page(pte_pfn(x))
 293#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 294#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 295
 296static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 297{
 298        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 299}
 300
 301/*
 302 * Certain architectures need to do special things when pte's
 303 * within a page table are directly modified.  Thus, the following
 304 * hook is made available.
 305 */
 306static inline void update_pte(pte_t *ptep, pte_t pteval)
 307{
 308        *ptep = pteval;
 309#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 310        __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
 311#endif
 312
 313}
 314
 315struct mm_struct;
 316
 317static inline void
 318set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
 319{
 320        update_pte(ptep, pteval);
 321}
 322
 323static inline void set_pte(pte_t *ptep, pte_t pteval)
 324{
 325        update_pte(ptep, pteval);
 326}
 327
 328static inline void
 329set_pmd(pmd_t *pmdp, pmd_t pmdval)
 330{
 331        *pmdp = pmdval;
 332}
 333
 334struct vm_area_struct;
 335
 336static inline int
 337ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
 338                          pte_t *ptep)
 339{
 340        pte_t pte = *ptep;
 341        if (!pte_young(pte))
 342                return 0;
 343        update_pte(ptep, pte_mkold(pte));
 344        return 1;
 345}
 346
 347static inline pte_t
 348ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 349{
 350        pte_t pte = *ptep;
 351        pte_clear(mm, addr, ptep);
 352        return pte;
 353}
 354
 355static inline void
 356ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 357{
 358        pte_t pte = *ptep;
 359        update_pte(ptep, pte_wrprotect(pte));
 360}
 361
 362/* to find an entry in a kernel page-table-directory */
 363#define pgd_offset_k(address)   pgd_offset(&init_mm, address)
 364
 365/* to find an entry in a page-table-directory */
 366#define pgd_offset(mm,address)  ((mm)->pgd + pgd_index(address))
 367
 368#define pgd_index(address)      ((address) >> PGDIR_SHIFT)
 369
 370/* Find an entry in the second-level page table.. */
 371#define pmd_offset(dir,address) ((pmd_t*)(dir))
 372
 373/* Find an entry in the third-level page table.. */
 374#define pte_index(address)      (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 375#define pte_offset_kernel(dir,addr)                                     \
 376        ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
 377#define pte_offset_map(dir,addr)        pte_offset_kernel((dir),(addr))
 378#define pte_unmap(pte)          do { } while (0)
 379
 380
 381/*
 382 * Encode and decode a swap and file entry.
 383 */
 384#define SWP_TYPE_BITS           5
 385#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
 386
 387#define __swp_type(entry)       (((entry).val >> 6) & 0x1f)
 388#define __swp_offset(entry)     ((entry).val >> 11)
 389#define __swp_entry(type,offs)  \
 390        ((swp_entry_t){((type) << 6) | ((offs) << 11) | \
 391         _PAGE_CA_INVALID | _PAGE_USER})
 392#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 393#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 394
 395#endif /*  !defined (__ASSEMBLY__) */
 396
 397
 398#ifdef __ASSEMBLY__
 399
 400/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 401 *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 402 *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 403 *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 404 *
 405 * Note: We require an additional temporary register which can be the same as
 406 *       the register that holds the address.
 407 *
 408 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 409 *
 410 */
 411#define _PGD_INDEX(rt,rs)       extui   rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
 412#define _PTE_INDEX(rt,rs)       extui   rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
 413
 414#define _PGD_OFFSET(mm,adr,tmp)         l32i    mm, mm, MM_PGD;         \
 415                                        _PGD_INDEX(tmp, adr);           \
 416                                        addx4   mm, tmp, mm
 417
 418#define _PTE_OFFSET(pmd,adr,tmp)        _PTE_INDEX(tmp, adr);           \
 419                                        srli    pmd, pmd, PAGE_SHIFT;   \
 420                                        slli    pmd, pmd, PAGE_SHIFT;   \
 421                                        addx4   pmd, tmp, pmd
 422
 423#else
 424
 425#define kern_addr_valid(addr)   (1)
 426
 427extern  void update_mmu_cache(struct vm_area_struct * vma,
 428                              unsigned long address, pte_t *ptep);
 429
 430typedef pte_t *pte_addr_t;
 431
 432#endif /* !defined (__ASSEMBLY__) */
 433
 434#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 435#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 436#define __HAVE_ARCH_PTEP_SET_WRPROTECT
 437#define __HAVE_ARCH_PTEP_MKDIRTY
 438#define __HAVE_ARCH_PTE_SAME
 439/* We provide our own get_unmapped_area to cope with
 440 * SHM area cache aliasing for userland.
 441 */
 442#define HAVE_ARCH_UNMAPPED_AREA
 443
 444#include <asm-generic/pgtable.h>
 445
 446#endif /* _XTENSA_PGTABLE_H */
 447