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20#include <dt-bindings/clock/histb-clock.h>
21#include <linux/clk-provider.h>
22#include <linux/module.h>
23#include <linux/of_device.h>
24#include <linux/platform_device.h>
25#include "clk.h"
26#include "crg.h"
27#include "reset.h"
28
29
30#define HI3798CV200_INNER_CLK_OFFSET 64
31#define HI3798CV200_FIXED_24M 65
32#define HI3798CV200_FIXED_25M 66
33#define HI3798CV200_FIXED_50M 67
34#define HI3798CV200_FIXED_75M 68
35#define HI3798CV200_FIXED_100M 69
36#define HI3798CV200_FIXED_150M 70
37#define HI3798CV200_FIXED_200M 71
38#define HI3798CV200_FIXED_250M 72
39#define HI3798CV200_FIXED_300M 73
40#define HI3798CV200_FIXED_400M 74
41#define HI3798CV200_MMC_MUX 75
42#define HI3798CV200_ETH_PUB_CLK 76
43#define HI3798CV200_ETH_BUS_CLK 77
44#define HI3798CV200_ETH_BUS0_CLK 78
45#define HI3798CV200_ETH_BUS1_CLK 79
46#define HI3798CV200_COMBPHY1_MUX 80
47#define HI3798CV200_FIXED_12M 81
48#define HI3798CV200_FIXED_48M 82
49#define HI3798CV200_FIXED_60M 83
50#define HI3798CV200_FIXED_166P5M 84
51#define HI3798CV200_SDIO0_MUX 85
52#define HI3798CV200_COMBPHY0_MUX 86
53
54#define HI3798CV200_CRG_NR_CLKS 128
55
56static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
57 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
58 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
59 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
60 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
61 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
62 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
63 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
64 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
65 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
66 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
67 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
68 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
69 { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
70 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
71 { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
72};
73
74static const char *const mmc_mux_p[] = {
75 "100m", "50m", "25m", "200m", "150m" };
76static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
77
78static const char *const comphy_mux_p[] = {
79 "100m", "25m"};
80static u32 comphy_mux_table[] = {2, 3};
81
82static const char *const sdio_mux_p[] = {
83 "100m", "50m", "150m", "166p5m" };
84static u32 sdio_mux_table[] = {0, 1, 2, 3};
85
86static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
87 { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
88 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
89 { HI3798CV200_COMBPHY0_MUX, "combphy0_mux",
90 comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
91 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
92 { HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
93 comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
94 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
95 { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
96 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
97 0x9c, 8, 2, 0, sdio_mux_table, },
98};
99
100static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
101static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315};
102
103static struct hisi_phase_clock hi3798cv200_phase_clks[] = {
104 { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu",
105 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
106 mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
107 { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu",
108 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
109 mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
110};
111
112static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
113
114 { HISTB_UART2_CLK, "clk_uart2", "75m",
115 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
116
117 { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
118 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
119 { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
120 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
121 { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
122 CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
123 { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb",
124 CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
125 { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb",
126 CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
127
128 { HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
129 CLK_SET_RATE_PARENT, 0x70, 0, 0, },
130
131 { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
132 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
133 { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",
134 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
135
136 { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
137 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
138 { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
139 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
140
141 { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
142 CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
143 { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
144 CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
145 { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
146 CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
147 { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
148 CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
149
150 { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
151 CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
152 { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
153 CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
154 { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
155 CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
156 { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
157 CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
158 { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
159 CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
160 { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0",
161 CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
162 { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1",
163 CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
164 { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
165 CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
166
167 { HISTB_COMBPHY0_CLK, "clk_combphy0", "combphy0_mux",
168 CLK_SET_RATE_PARENT, 0x188, 0, 0, },
169
170 { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
171 CLK_SET_RATE_PARENT, 0x188, 8, 0, },
172
173 { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
174 CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
175 { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
176 CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
177 { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
178 CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
179 { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
180 CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
181 { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
182 CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
183 { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",
184 CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
185 { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
186 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
187 { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
188 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
189
190 { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
191 CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
192 { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
193 CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
194 { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
195 CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
196 { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
197 CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
198 { HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,
199 CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
200 { HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,
201 CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
202 { HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,
203 CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
204 { HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,
205 CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
206};
207
208static struct hisi_clock_data *hi3798cv200_clk_register(
209 struct platform_device *pdev)
210{
211 struct hisi_clock_data *clk_data;
212 int ret;
213
214 clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
215 if (!clk_data)
216 return ERR_PTR(-ENOMEM);
217
218
219 ret = hisi_clk_register_phase(&pdev->dev,
220 hi3798cv200_phase_clks,
221 ARRAY_SIZE(hi3798cv200_phase_clks),
222 clk_data);
223 if (ret)
224 return ERR_PTR(ret);
225
226 ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
227 ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
228 clk_data);
229 if (ret)
230 return ERR_PTR(ret);
231
232 ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
233 ARRAY_SIZE(hi3798cv200_mux_clks),
234 clk_data);
235 if (ret)
236 goto unregister_fixed_rate;
237
238 ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
239 ARRAY_SIZE(hi3798cv200_gate_clks),
240 clk_data);
241 if (ret)
242 goto unregister_mux;
243
244 ret = of_clk_add_provider(pdev->dev.of_node,
245 of_clk_src_onecell_get, &clk_data->clk_data);
246 if (ret)
247 goto unregister_gate;
248
249 return clk_data;
250
251unregister_gate:
252 hisi_clk_unregister_gate(hi3798cv200_gate_clks,
253 ARRAY_SIZE(hi3798cv200_gate_clks),
254 clk_data);
255unregister_mux:
256 hisi_clk_unregister_mux(hi3798cv200_mux_clks,
257 ARRAY_SIZE(hi3798cv200_mux_clks),
258 clk_data);
259unregister_fixed_rate:
260 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
261 ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
262 clk_data);
263 return ERR_PTR(ret);
264}
265
266static void hi3798cv200_clk_unregister(struct platform_device *pdev)
267{
268 struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
269
270 of_clk_del_provider(pdev->dev.of_node);
271
272 hisi_clk_unregister_gate(hi3798cv200_gate_clks,
273 ARRAY_SIZE(hi3798cv200_gate_clks),
274 crg->clk_data);
275 hisi_clk_unregister_mux(hi3798cv200_mux_clks,
276 ARRAY_SIZE(hi3798cv200_mux_clks),
277 crg->clk_data);
278 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
279 ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
280 crg->clk_data);
281}
282
283static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
284 .register_clks = hi3798cv200_clk_register,
285 .unregister_clks = hi3798cv200_clk_unregister,
286};
287
288
289
290#define HI3798CV200_SYSCTRL_NR_CLKS 16
291
292static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
293 { HISTB_IR_CLK, "clk_ir", "24m",
294 CLK_SET_RATE_PARENT, 0x48, 4, 0, },
295 { HISTB_TIMER01_CLK, "clk_timer01", "24m",
296 CLK_SET_RATE_PARENT, 0x48, 6, 0, },
297 { HISTB_UART0_CLK, "clk_uart0", "75m",
298 CLK_SET_RATE_PARENT, 0x48, 10, 0, },
299};
300
301static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
302 struct platform_device *pdev)
303{
304 struct hisi_clock_data *clk_data;
305 int ret;
306
307 clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
308 if (!clk_data)
309 return ERR_PTR(-ENOMEM);
310
311 ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
312 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
313 clk_data);
314 if (ret)
315 return ERR_PTR(ret);
316
317 ret = of_clk_add_provider(pdev->dev.of_node,
318 of_clk_src_onecell_get, &clk_data->clk_data);
319 if (ret)
320 goto unregister_gate;
321
322 return clk_data;
323
324unregister_gate:
325 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
326 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
327 clk_data);
328 return ERR_PTR(ret);
329}
330
331static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
332{
333 struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
334
335 of_clk_del_provider(pdev->dev.of_node);
336
337 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
338 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
339 crg->clk_data);
340}
341
342static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
343 .register_clks = hi3798cv200_sysctrl_clk_register,
344 .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
345};
346
347static const struct of_device_id hi3798cv200_crg_match_table[] = {
348 { .compatible = "hisilicon,hi3798cv200-crg",
349 .data = &hi3798cv200_crg_funcs },
350 { .compatible = "hisilicon,hi3798cv200-sysctrl",
351 .data = &hi3798cv200_sysctrl_funcs },
352 { }
353};
354MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
355
356static int hi3798cv200_crg_probe(struct platform_device *pdev)
357{
358 struct hisi_crg_dev *crg;
359
360 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
361 if (!crg)
362 return -ENOMEM;
363
364 crg->funcs = of_device_get_match_data(&pdev->dev);
365 if (!crg->funcs)
366 return -ENOENT;
367
368 crg->rstc = hisi_reset_init(pdev);
369 if (!crg->rstc)
370 return -ENOMEM;
371
372 crg->clk_data = crg->funcs->register_clks(pdev);
373 if (IS_ERR(crg->clk_data)) {
374 hisi_reset_exit(crg->rstc);
375 return PTR_ERR(crg->clk_data);
376 }
377
378 platform_set_drvdata(pdev, crg);
379 return 0;
380}
381
382static int hi3798cv200_crg_remove(struct platform_device *pdev)
383{
384 struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
385
386 hisi_reset_exit(crg->rstc);
387 crg->funcs->unregister_clks(pdev);
388 return 0;
389}
390
391static struct platform_driver hi3798cv200_crg_driver = {
392 .probe = hi3798cv200_crg_probe,
393 .remove = hi3798cv200_crg_remove,
394 .driver = {
395 .name = "hi3798cv200-crg",
396 .of_match_table = hi3798cv200_crg_match_table,
397 },
398};
399
400static int __init hi3798cv200_crg_init(void)
401{
402 return platform_driver_register(&hi3798cv200_crg_driver);
403}
404core_initcall(hi3798cv200_crg_init);
405
406static void __exit hi3798cv200_crg_exit(void)
407{
408 platform_driver_unregister(&hi3798cv200_crg_driver);
409}
410module_exit(hi3798cv200_crg_exit);
411
412MODULE_LICENSE("GPL v2");
413MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
414
