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26#include <linux/module.h>
27#include <linux/slab.h>
28#include <linux/pm_runtime.h>
29
30#include <drm/drmP.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/amdgpu_drm.h>
34#include "amdgpu.h"
35#include "cikd.h"
36
37#include <drm/drm_fb_helper.h>
38
39#include <linux/vga_switcheroo.h>
40
41#include "amdgpu_display.h"
42
43
44
45
46
47
48static int
49amdgpufb_open(struct fb_info *info, int user)
50{
51 struct amdgpu_fbdev *rfbdev = info->par;
52 struct amdgpu_device *adev = rfbdev->adev;
53 int ret = pm_runtime_get_sync(adev->ddev->dev);
54 if (ret < 0 && ret != -EACCES) {
55 pm_runtime_mark_last_busy(adev->ddev->dev);
56 pm_runtime_put_autosuspend(adev->ddev->dev);
57 return ret;
58 }
59 return 0;
60}
61
62static int
63amdgpufb_release(struct fb_info *info, int user)
64{
65 struct amdgpu_fbdev *rfbdev = info->par;
66 struct amdgpu_device *adev = rfbdev->adev;
67
68 pm_runtime_mark_last_busy(adev->ddev->dev);
69 pm_runtime_put_autosuspend(adev->ddev->dev);
70 return 0;
71}
72
73static struct fb_ops amdgpufb_ops = {
74 .owner = THIS_MODULE,
75 DRM_FB_HELPER_DEFAULT_OPS,
76 .fb_open = amdgpufb_open,
77 .fb_release = amdgpufb_release,
78 .fb_fillrect = drm_fb_helper_cfb_fillrect,
79 .fb_copyarea = drm_fb_helper_cfb_copyarea,
80 .fb_imageblit = drm_fb_helper_cfb_imageblit,
81};
82
83
84int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
85{
86 int aligned = width;
87 int pitch_mask = 0;
88
89 switch (cpp) {
90 case 1:
91 pitch_mask = 255;
92 break;
93 case 2:
94 pitch_mask = 127;
95 break;
96 case 3:
97 case 4:
98 pitch_mask = 63;
99 break;
100 }
101
102 aligned += pitch_mask;
103 aligned &= ~pitch_mask;
104 return aligned * cpp;
105}
106
107static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
108{
109 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
110 int ret;
111
112 ret = amdgpu_bo_reserve(abo, true);
113 if (likely(ret == 0)) {
114 amdgpu_bo_kunmap(abo);
115 amdgpu_bo_unpin(abo);
116 amdgpu_bo_unreserve(abo);
117 }
118 drm_gem_object_put_unlocked(gobj);
119}
120
121static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
122 struct drm_mode_fb_cmd2 *mode_cmd,
123 struct drm_gem_object **gobj_p)
124{
125 struct amdgpu_device *adev = rfbdev->adev;
126 struct drm_gem_object *gobj = NULL;
127 struct amdgpu_bo *abo = NULL;
128 bool fb_tiled = false;
129 u32 tiling_flags = 0, domain;
130 int ret;
131 int aligned_size, size;
132 int height = mode_cmd->height;
133 u32 cpp;
134
135 cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
136
137
138 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
139 fb_tiled);
140 domain = amdgpu_display_supported_domains(adev);
141
142 height = ALIGN(mode_cmd->height, 8);
143 size = mode_cmd->pitches[0] * height;
144 aligned_size = ALIGN(size, PAGE_SIZE);
145 ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
146 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
147 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
148 AMDGPU_GEM_CREATE_VRAM_CLEARED,
149 true, NULL, &gobj);
150 if (ret) {
151 pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
152 return -ENOMEM;
153 }
154 abo = gem_to_amdgpu_bo(gobj);
155
156 if (fb_tiled)
157 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
158
159 ret = amdgpu_bo_reserve(abo, false);
160 if (unlikely(ret != 0))
161 goto out_unref;
162
163 if (tiling_flags) {
164 ret = amdgpu_bo_set_tiling_flags(abo,
165 tiling_flags);
166 if (ret)
167 dev_err(adev->dev, "FB failed to set tiling flags\n");
168 }
169
170
171 ret = amdgpu_bo_pin(abo, domain, NULL);
172 if (ret) {
173 amdgpu_bo_unreserve(abo);
174 goto out_unref;
175 }
176 ret = amdgpu_bo_kmap(abo, NULL);
177 amdgpu_bo_unreserve(abo);
178 if (ret) {
179 goto out_unref;
180 }
181
182 *gobj_p = gobj;
183 return 0;
184out_unref:
185 amdgpufb_destroy_pinned_object(gobj);
186 *gobj_p = NULL;
187 return ret;
188}
189
190static int amdgpufb_create(struct drm_fb_helper *helper,
191 struct drm_fb_helper_surface_size *sizes)
192{
193 struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
194 struct amdgpu_device *adev = rfbdev->adev;
195 struct fb_info *info;
196 struct drm_framebuffer *fb = NULL;
197 struct drm_mode_fb_cmd2 mode_cmd;
198 struct drm_gem_object *gobj = NULL;
199 struct amdgpu_bo *abo = NULL;
200 int ret;
201 unsigned long tmp;
202
203 mode_cmd.width = sizes->surface_width;
204 mode_cmd.height = sizes->surface_height;
205
206 if (sizes->surface_bpp == 24)
207 sizes->surface_bpp = 32;
208
209 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
210 sizes->surface_depth);
211
212 ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
213 if (ret) {
214 DRM_ERROR("failed to create fbcon object %d\n", ret);
215 return ret;
216 }
217
218 abo = gem_to_amdgpu_bo(gobj);
219
220
221 info = drm_fb_helper_alloc_fbi(helper);
222 if (IS_ERR(info)) {
223 ret = PTR_ERR(info);
224 goto out;
225 }
226
227 info->par = rfbdev;
228 info->skip_vt_switch = true;
229
230 ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
231 &mode_cmd, gobj);
232 if (ret) {
233 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
234 goto out;
235 }
236
237 fb = &rfbdev->rfb.base;
238
239
240 rfbdev->helper.fb = fb;
241
242 strcpy(info->fix.id, "amdgpudrmfb");
243
244 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
245
246 info->fbops = &amdgpufb_ops;
247
248 tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
249 info->fix.smem_start = adev->gmc.aper_base + tmp;
250 info->fix.smem_len = amdgpu_bo_size(abo);
251 info->screen_base = amdgpu_bo_kptr(abo);
252 info->screen_size = amdgpu_bo_size(abo);
253
254 drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
255
256
257 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
258 info->apertures->ranges[0].size = adev->gmc.aper_size;
259
260
261
262 if (info->screen_base == NULL) {
263 ret = -ENOSPC;
264 goto out;
265 }
266
267 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
268 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
269 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
270 DRM_INFO("fb depth is %d\n", fb->format->depth);
271 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
272
273 vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
274 return 0;
275
276out:
277 if (abo) {
278
279 }
280 if (fb && ret) {
281 drm_gem_object_put_unlocked(gobj);
282 drm_framebuffer_unregister_private(fb);
283 drm_framebuffer_cleanup(fb);
284 kfree(fb);
285 }
286 return ret;
287}
288
289static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
290{
291 struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
292
293 drm_fb_helper_unregister_fbi(&rfbdev->helper);
294
295 if (rfb->base.obj[0]) {
296 amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
297 rfb->base.obj[0] = NULL;
298 drm_framebuffer_unregister_private(&rfb->base);
299 drm_framebuffer_cleanup(&rfb->base);
300 }
301 drm_fb_helper_fini(&rfbdev->helper);
302
303 return 0;
304}
305
306static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
307 .fb_probe = amdgpufb_create,
308};
309
310int amdgpu_fbdev_init(struct amdgpu_device *adev)
311{
312 struct amdgpu_fbdev *rfbdev;
313 int bpp_sel = 32;
314 int ret;
315
316
317 if (!adev->mode_info.mode_config_initialized)
318 return 0;
319
320
321 if (list_empty(&adev->ddev->mode_config.connector_list))
322 return 0;
323
324
325 if (adev->gmc.real_vram_size <= (32*1024*1024))
326 bpp_sel = 8;
327
328 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
329 if (!rfbdev)
330 return -ENOMEM;
331
332 rfbdev->adev = adev;
333 adev->mode_info.rfbdev = rfbdev;
334
335 drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
336 &amdgpu_fb_helper_funcs);
337
338 ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
339 AMDGPUFB_CONN_LIMIT);
340 if (ret) {
341 kfree(rfbdev);
342 return ret;
343 }
344
345 drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
346
347
348 if (!amdgpu_device_has_dc_support(adev))
349 drm_helper_disable_unused_functions(adev->ddev);
350
351 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
352 return 0;
353}
354
355void amdgpu_fbdev_fini(struct amdgpu_device *adev)
356{
357 if (!adev->mode_info.rfbdev)
358 return;
359
360 amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
361 kfree(adev->mode_info.rfbdev);
362 adev->mode_info.rfbdev = NULL;
363}
364
365void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
366{
367 if (adev->mode_info.rfbdev)
368 drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
369 state);
370}
371
372int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
373{
374 struct amdgpu_bo *robj;
375 int size = 0;
376
377 if (!adev->mode_info.rfbdev)
378 return 0;
379
380 robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
381 size += amdgpu_bo_size(robj);
382 return size;
383}
384
385bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
386{
387 if (!adev->mode_info.rfbdev)
388 return false;
389 if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
390 return true;
391 return false;
392}
393
