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26#include "dm_services.h"
27#include "dc.h"
28
29#include "resource.h"
30#include "include/irq_service_interface.h"
31#include "dcn10/dcn10_resource.h"
32
33#include "dcn10/dcn10_ipp.h"
34#include "dcn10/dcn10_mpc.h"
35#include "irq/dcn10/irq_service_dcn10.h"
36#include "dcn10/dcn10_dpp.h"
37#include "dcn10_optc.h"
38#include "dcn10/dcn10_hw_sequencer.h"
39#include "dce110/dce110_hw_sequencer.h"
40#include "dcn10/dcn10_opp.h"
41#include "dcn10/dcn10_link_encoder.h"
42#include "dcn10/dcn10_stream_encoder.h"
43#include "dce/dce_clocks.h"
44#include "dce/dce_clock_source.h"
45#include "dce/dce_audio.h"
46#include "dce/dce_hwseq.h"
47#include "../virtual/virtual_stream_encoder.h"
48#include "dce110/dce110_resource.h"
49#include "dce112/dce112_resource.h"
50#include "dcn10_hubp.h"
51#include "dcn10_hubbub.h"
52
53#include "soc15_hw_ip.h"
54#include "vega10_ip_offset.h"
55
56#include "dcn/dcn_1_0_offset.h"
57#include "dcn/dcn_1_0_sh_mask.h"
58
59#include "nbio/nbio_7_0_offset.h"
60
61#include "mmhub/mmhub_9_1_offset.h"
62#include "mmhub/mmhub_9_1_sh_mask.h"
63
64#include "reg_helper.h"
65#include "dce/dce_abm.h"
66#include "dce/dce_dmcu.h"
67
68#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
69 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
70 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
72 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
73 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
74 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
75 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
76 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
78 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
80 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
82 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83#endif
84
85
86enum dcn10_clk_src_array_id {
87 DCN10_CLK_SRC_PLL0,
88 DCN10_CLK_SRC_PLL1,
89 DCN10_CLK_SRC_PLL2,
90 DCN10_CLK_SRC_PLL3,
91 DCN10_CLK_SRC_TOTAL
92};
93
94
95
96
97
98#define BASE_INNER(seg) \
99 DCE_BASE__INST0_SEG ## seg
100
101#define BASE(seg) \
102 BASE_INNER(seg)
103
104#define SR(reg_name)\
105 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
106 mm ## reg_name
107
108#define SRI(reg_name, block, id)\
109 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
110 mm ## block ## id ## _ ## reg_name
111
112
113#define SRII(reg_name, block, id)\
114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
115 mm ## block ## id ## _ ## reg_name
116
117
118#define NBIO_BASE_INNER(seg) \
119 NBIF_BASE__INST0_SEG ## seg
120
121#define NBIO_BASE(seg) \
122 NBIO_BASE_INNER(seg)
123
124#define NBIO_SR(reg_name)\
125 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
126 mm ## reg_name
127
128
129#define MMHUB_BASE_INNER(seg) \
130 MMHUB_BASE__INST0_SEG ## seg
131
132#define MMHUB_BASE(seg) \
133 MMHUB_BASE_INNER(seg)
134
135#define MMHUB_SR(reg_name)\
136 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
137 mm ## reg_name
138
139
140
141
142
143static const struct dce_dmcu_registers dmcu_regs = {
144 DMCU_DCN10_REG_LIST()
145};
146
147static const struct dce_dmcu_shift dmcu_shift = {
148 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
149};
150
151static const struct dce_dmcu_mask dmcu_mask = {
152 DMCU_MASK_SH_LIST_DCN10(_MASK)
153};
154
155static const struct dce_abm_registers abm_regs = {
156 ABM_DCN10_REG_LIST(0)
157};
158
159static const struct dce_abm_shift abm_shift = {
160 ABM_MASK_SH_LIST_DCN10(__SHIFT)
161};
162
163static const struct dce_abm_mask abm_mask = {
164 ABM_MASK_SH_LIST_DCN10(_MASK)
165};
166
167#define stream_enc_regs(id)\
168[id] = {\
169 SE_DCN_REG_LIST(id)\
170}
171
172static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
173 stream_enc_regs(0),
174 stream_enc_regs(1),
175 stream_enc_regs(2),
176 stream_enc_regs(3),
177};
178
179static const struct dcn10_stream_encoder_shift se_shift = {
180 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
181};
182
183static const struct dcn10_stream_encoder_mask se_mask = {
184 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
185};
186
187#define audio_regs(id)\
188[id] = {\
189 AUD_COMMON_REG_LIST(id)\
190}
191
192static const struct dce_audio_registers audio_regs[] = {
193 audio_regs(0),
194 audio_regs(1),
195 audio_regs(2),
196 audio_regs(3),
197};
198
199#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
200 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
201 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
202 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
203
204static const struct dce_audio_shift audio_shift = {
205 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
206};
207
208static const struct dce_aduio_mask audio_mask = {
209 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
210};
211
212#define aux_regs(id)\
213[id] = {\
214 AUX_REG_LIST(id)\
215}
216
217static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
218 aux_regs(0),
219 aux_regs(1),
220 aux_regs(2),
221 aux_regs(3)
222};
223
224#define hpd_regs(id)\
225[id] = {\
226 HPD_REG_LIST(id)\
227}
228
229static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
230 hpd_regs(0),
231 hpd_regs(1),
232 hpd_regs(2),
233 hpd_regs(3)
234};
235
236#define link_regs(id)\
237[id] = {\
238 LE_DCN10_REG_LIST(id), \
239 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
240}
241
242static const struct dcn10_link_enc_registers link_enc_regs[] = {
243 link_regs(0),
244 link_regs(1),
245 link_regs(2),
246 link_regs(3)
247};
248
249static const struct dcn10_link_enc_shift le_shift = {
250 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
251};
252
253static const struct dcn10_link_enc_mask le_mask = {
254 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
255};
256
257#define ipp_regs(id)\
258[id] = {\
259 IPP_REG_LIST_DCN10(id),\
260}
261
262static const struct dcn10_ipp_registers ipp_regs[] = {
263 ipp_regs(0),
264 ipp_regs(1),
265 ipp_regs(2),
266 ipp_regs(3),
267};
268
269static const struct dcn10_ipp_shift ipp_shift = {
270 IPP_MASK_SH_LIST_DCN10(__SHIFT)
271};
272
273static const struct dcn10_ipp_mask ipp_mask = {
274 IPP_MASK_SH_LIST_DCN10(_MASK),
275};
276
277#define opp_regs(id)\
278[id] = {\
279 OPP_REG_LIST_DCN10(id),\
280}
281
282static const struct dcn10_opp_registers opp_regs[] = {
283 opp_regs(0),
284 opp_regs(1),
285 opp_regs(2),
286 opp_regs(3),
287};
288
289static const struct dcn10_opp_shift opp_shift = {
290 OPP_MASK_SH_LIST_DCN10(__SHIFT)
291};
292
293static const struct dcn10_opp_mask opp_mask = {
294 OPP_MASK_SH_LIST_DCN10(_MASK),
295};
296
297#define tf_regs(id)\
298[id] = {\
299 TF_REG_LIST_DCN10(id),\
300}
301
302static const struct dcn_dpp_registers tf_regs[] = {
303 tf_regs(0),
304 tf_regs(1),
305 tf_regs(2),
306 tf_regs(3),
307};
308
309static const struct dcn_dpp_shift tf_shift = {
310 TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
311 TF_DEBUG_REG_LIST_SH_DCN10
312
313};
314
315static const struct dcn_dpp_mask tf_mask = {
316 TF_REG_LIST_SH_MASK_DCN10(_MASK),
317 TF_DEBUG_REG_LIST_MASK_DCN10
318};
319
320static const struct dcn_mpc_registers mpc_regs = {
321 MPC_COMMON_REG_LIST_DCN1_0(0),
322 MPC_COMMON_REG_LIST_DCN1_0(1),
323 MPC_COMMON_REG_LIST_DCN1_0(2),
324 MPC_COMMON_REG_LIST_DCN1_0(3),
325 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
326 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
327 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
328 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
329};
330
331static const struct dcn_mpc_shift mpc_shift = {
332 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
333};
334
335static const struct dcn_mpc_mask mpc_mask = {
336 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
337};
338
339#define tg_regs(id)\
340[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
341
342static const struct dcn_optc_registers tg_regs[] = {
343 tg_regs(0),
344 tg_regs(1),
345 tg_regs(2),
346 tg_regs(3),
347};
348
349static const struct dcn_optc_shift tg_shift = {
350 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
351};
352
353static const struct dcn_optc_mask tg_mask = {
354 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
355};
356
357
358static const struct bios_registers bios_regs = {
359 NBIO_SR(BIOS_SCRATCH_3),
360 NBIO_SR(BIOS_SCRATCH_6)
361};
362
363#define hubp_regs(id)\
364[id] = {\
365 HUBP_REG_LIST_DCN10(id)\
366}
367
368
369static const struct dcn_mi_registers hubp_regs[] = {
370 hubp_regs(0),
371 hubp_regs(1),
372 hubp_regs(2),
373 hubp_regs(3),
374};
375
376static const struct dcn_mi_shift hubp_shift = {
377 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
378};
379
380static const struct dcn_mi_mask hubp_mask = {
381 HUBP_MASK_SH_LIST_DCN10(_MASK)
382};
383
384
385static const struct dcn_hubbub_registers hubbub_reg = {
386 HUBBUB_REG_LIST_DCN10(0)
387};
388
389static const struct dcn_hubbub_shift hubbub_shift = {
390 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
391};
392
393static const struct dcn_hubbub_mask hubbub_mask = {
394 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
395};
396
397#define clk_src_regs(index, pllid)\
398[index] = {\
399 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
400}
401
402static const struct dce110_clk_src_regs clk_src_regs[] = {
403 clk_src_regs(0, A),
404 clk_src_regs(1, B),
405 clk_src_regs(2, C),
406 clk_src_regs(3, D)
407};
408
409static const struct dce110_clk_src_shift cs_shift = {
410 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
411};
412
413static const struct dce110_clk_src_mask cs_mask = {
414 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
415};
416
417
418static const struct resource_caps res_cap = {
419 .num_timing_generator = 4,
420 .num_video_plane = 4,
421 .num_audio = 4,
422 .num_stream_encoder = 4,
423 .num_pll = 4,
424};
425
426static const struct dc_debug debug_defaults_drv = {
427 .sanity_checks = true,
428 .disable_dmcu = true,
429 .force_abm_enable = false,
430 .timing_trace = false,
431 .clock_trace = true,
432
433
434
435
436
437 .min_disp_clk_khz = 100000,
438
439 .disable_pplib_clock_request = true,
440 .disable_pplib_wm_range = false,
441 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
442 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
443 .force_single_disp_pipe_split = true,
444 .disable_dcc = DCC_ENABLE,
445 .voltage_align_fclk = true,
446 .disable_stereo_support = true,
447 .vsr_support = true,
448 .performance_trace = false,
449 .az_endpoint_mute_only = true,
450 .recovery_enabled = false,
451 .max_downscale_src_width = 3840,
452};
453
454static const struct dc_debug debug_defaults_diags = {
455 .disable_dmcu = true,
456 .force_abm_enable = false,
457 .timing_trace = true,
458 .clock_trace = true,
459 .disable_stutter = true,
460 .disable_pplib_clock_request = true,
461 .disable_pplib_wm_range = true
462};
463
464static void dcn10_dpp_destroy(struct dpp **dpp)
465{
466 kfree(TO_DCN10_DPP(*dpp));
467 *dpp = NULL;
468}
469
470static struct dpp *dcn10_dpp_create(
471 struct dc_context *ctx,
472 uint32_t inst)
473{
474 struct dcn10_dpp *dpp =
475 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
476
477 if (!dpp)
478 return NULL;
479
480 dpp1_construct(dpp, ctx, inst,
481 &tf_regs[inst], &tf_shift, &tf_mask);
482 return &dpp->base;
483}
484
485static struct input_pixel_processor *dcn10_ipp_create(
486 struct dc_context *ctx, uint32_t inst)
487{
488 struct dcn10_ipp *ipp =
489 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
490
491 if (!ipp) {
492 BREAK_TO_DEBUGGER();
493 return NULL;
494 }
495
496 dcn10_ipp_construct(ipp, ctx, inst,
497 &ipp_regs[inst], &ipp_shift, &ipp_mask);
498 return &ipp->base;
499}
500
501
502static struct output_pixel_processor *dcn10_opp_create(
503 struct dc_context *ctx, uint32_t inst)
504{
505 struct dcn10_opp *opp =
506 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
507
508 if (!opp) {
509 BREAK_TO_DEBUGGER();
510 return NULL;
511 }
512
513 dcn10_opp_construct(opp, ctx, inst,
514 &opp_regs[inst], &opp_shift, &opp_mask);
515 return &opp->base;
516}
517
518static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
519{
520 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
521 GFP_KERNEL);
522
523 if (!mpc10)
524 return NULL;
525
526 dcn10_mpc_construct(mpc10, ctx,
527 &mpc_regs,
528 &mpc_shift,
529 &mpc_mask,
530 4);
531
532 return &mpc10->base;
533}
534
535static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
536{
537 struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
538 GFP_KERNEL);
539
540 if (!hubbub)
541 return NULL;
542
543 hubbub1_construct(hubbub, ctx,
544 &hubbub_reg,
545 &hubbub_shift,
546 &hubbub_mask);
547
548 return hubbub;
549}
550
551static struct timing_generator *dcn10_timing_generator_create(
552 struct dc_context *ctx,
553 uint32_t instance)
554{
555 struct optc *tgn10 =
556 kzalloc(sizeof(struct optc), GFP_KERNEL);
557
558 if (!tgn10)
559 return NULL;
560
561 tgn10->base.inst = instance;
562 tgn10->base.ctx = ctx;
563
564 tgn10->tg_regs = &tg_regs[instance];
565 tgn10->tg_shift = &tg_shift;
566 tgn10->tg_mask = &tg_mask;
567
568 dcn10_timing_generator_init(tgn10);
569
570 return &tgn10->base;
571}
572
573static const struct encoder_feature_support link_enc_feature = {
574 .max_hdmi_deep_color = COLOR_DEPTH_121212,
575 .max_hdmi_pixel_clock = 600000,
576 .ycbcr420_supported = true,
577 .flags.bits.IS_HBR2_CAPABLE = true,
578 .flags.bits.IS_HBR3_CAPABLE = true,
579 .flags.bits.IS_TPS3_CAPABLE = true,
580 .flags.bits.IS_TPS4_CAPABLE = true,
581 .flags.bits.IS_YCBCR_CAPABLE = true
582};
583
584struct link_encoder *dcn10_link_encoder_create(
585 const struct encoder_init_data *enc_init_data)
586{
587 struct dcn10_link_encoder *enc10 =
588 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
589
590 if (!enc10)
591 return NULL;
592
593 dcn10_link_encoder_construct(enc10,
594 enc_init_data,
595 &link_enc_feature,
596 &link_enc_regs[enc_init_data->transmitter],
597 &link_enc_aux_regs[enc_init_data->channel - 1],
598 &link_enc_hpd_regs[enc_init_data->hpd_source],
599 &le_shift,
600 &le_mask);
601
602 return &enc10->base;
603}
604
605struct clock_source *dcn10_clock_source_create(
606 struct dc_context *ctx,
607 struct dc_bios *bios,
608 enum clock_source_id id,
609 const struct dce110_clk_src_regs *regs,
610 bool dp_clk_src)
611{
612 struct dce110_clk_src *clk_src =
613 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
614
615 if (!clk_src)
616 return NULL;
617
618 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
619 regs, &cs_shift, &cs_mask)) {
620 clk_src->base.dp_clk_src = dp_clk_src;
621 return &clk_src->base;
622 }
623
624 BREAK_TO_DEBUGGER();
625 return NULL;
626}
627
628static void read_dce_straps(
629 struct dc_context *ctx,
630 struct resource_straps *straps)
631{
632 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
633 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
634}
635
636static struct audio *create_audio(
637 struct dc_context *ctx, unsigned int inst)
638{
639 return dce_audio_create(ctx, inst,
640 &audio_regs[inst], &audio_shift, &audio_mask);
641}
642
643static struct stream_encoder *dcn10_stream_encoder_create(
644 enum engine_id eng_id,
645 struct dc_context *ctx)
646{
647 struct dcn10_stream_encoder *enc1 =
648 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
649
650 if (!enc1)
651 return NULL;
652
653 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
654 &stream_enc_regs[eng_id],
655 &se_shift, &se_mask);
656 return &enc1->base;
657}
658
659static const struct dce_hwseq_registers hwseq_reg = {
660 HWSEQ_DCN1_REG_LIST()
661};
662
663static const struct dce_hwseq_shift hwseq_shift = {
664 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
665};
666
667static const struct dce_hwseq_mask hwseq_mask = {
668 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
669};
670
671static struct dce_hwseq *dcn10_hwseq_create(
672 struct dc_context *ctx)
673{
674 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
675
676 if (hws) {
677 hws->ctx = ctx;
678 hws->regs = &hwseq_reg;
679 hws->shifts = &hwseq_shift;
680 hws->masks = &hwseq_mask;
681 hws->wa.DEGVIDCN10_253 = true;
682 hws->wa.false_optc_underflow = true;
683 }
684 return hws;
685}
686
687static const struct resource_create_funcs res_create_funcs = {
688 .read_dce_straps = read_dce_straps,
689 .create_audio = create_audio,
690 .create_stream_encoder = dcn10_stream_encoder_create,
691 .create_hwseq = dcn10_hwseq_create,
692};
693
694static const struct resource_create_funcs res_create_maximus_funcs = {
695 .read_dce_straps = NULL,
696 .create_audio = NULL,
697 .create_stream_encoder = NULL,
698 .create_hwseq = dcn10_hwseq_create,
699};
700
701void dcn10_clock_source_destroy(struct clock_source **clk_src)
702{
703 kfree(TO_DCE110_CLK_SRC(*clk_src));
704 *clk_src = NULL;
705}
706
707static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx)
708{
709 struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
710
711 if (!pp_smu)
712 return pp_smu;
713
714 dm_pp_get_funcs_rv(ctx, pp_smu);
715 return pp_smu;
716}
717
718static void destruct(struct dcn10_resource_pool *pool)
719{
720 unsigned int i;
721
722 for (i = 0; i < pool->base.stream_enc_count; i++) {
723 if (pool->base.stream_enc[i] != NULL) {
724
725
726
727 kfree(pool->base.stream_enc[i]);
728 pool->base.stream_enc[i] = NULL;
729 }
730 }
731
732 if (pool->base.mpc != NULL) {
733 kfree(TO_DCN10_MPC(pool->base.mpc));
734 pool->base.mpc = NULL;
735 }
736
737 if (pool->base.hubbub != NULL) {
738 kfree(pool->base.hubbub);
739 pool->base.hubbub = NULL;
740 }
741
742 for (i = 0; i < pool->base.pipe_count; i++) {
743 if (pool->base.opps[i] != NULL)
744 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
745
746 if (pool->base.dpps[i] != NULL)
747 dcn10_dpp_destroy(&pool->base.dpps[i]);
748
749 if (pool->base.ipps[i] != NULL)
750 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
751
752 if (pool->base.hubps[i] != NULL) {
753 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
754 pool->base.hubps[i] = NULL;
755 }
756
757 if (pool->base.irqs != NULL) {
758 dal_irq_service_destroy(&pool->base.irqs);
759 }
760
761 if (pool->base.timing_generators[i] != NULL) {
762 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
763 pool->base.timing_generators[i] = NULL;
764 }
765 }
766
767 for (i = 0; i < pool->base.stream_enc_count; i++)
768 kfree(pool->base.stream_enc[i]);
769
770 for (i = 0; i < pool->base.audio_count; i++) {
771 if (pool->base.audios[i])
772 dce_aud_destroy(&pool->base.audios[i]);
773 }
774
775 for (i = 0; i < pool->base.clk_src_count; i++) {
776 if (pool->base.clock_sources[i] != NULL) {
777 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
778 pool->base.clock_sources[i] = NULL;
779 }
780 }
781
782 if (pool->base.dp_clock_source != NULL) {
783 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
784 pool->base.dp_clock_source = NULL;
785 }
786
787 if (pool->base.abm != NULL)
788 dce_abm_destroy(&pool->base.abm);
789
790 if (pool->base.dmcu != NULL)
791 dce_dmcu_destroy(&pool->base.dmcu);
792
793 if (pool->base.display_clock != NULL)
794 dce_disp_clk_destroy(&pool->base.display_clock);
795
796 kfree(pool->base.pp_smu);
797}
798
799static struct hubp *dcn10_hubp_create(
800 struct dc_context *ctx,
801 uint32_t inst)
802{
803 struct dcn10_hubp *hubp1 =
804 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
805
806 if (!hubp1)
807 return NULL;
808
809 dcn10_hubp_construct(hubp1, ctx, inst,
810 &hubp_regs[inst], &hubp_shift, &hubp_mask);
811 return &hubp1->base;
812}
813
814static void get_pixel_clock_parameters(
815 const struct pipe_ctx *pipe_ctx,
816 struct pixel_clk_params *pixel_clk_params)
817{
818 const struct dc_stream_state *stream = pipe_ctx->stream;
819 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
820 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
821 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
822 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
823
824 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
825 LINK_RATE_REF_FREQ_IN_KHZ;
826 pixel_clk_params->flags.ENABLE_SS = 0;
827 pixel_clk_params->color_depth =
828 stream->timing.display_color_depth;
829 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
830 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
831
832 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
833 pixel_clk_params->color_depth = COLOR_DEPTH_888;
834
835 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
836 pixel_clk_params->requested_pix_clk /= 2;
837
838}
839
840static void build_clamping_params(struct dc_stream_state *stream)
841{
842 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
843 stream->clamping.c_depth = stream->timing.display_color_depth;
844 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
845}
846
847static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
848{
849
850 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
851
852 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
853 pipe_ctx->clock_source,
854 &pipe_ctx->stream_res.pix_clk_params,
855 &pipe_ctx->pll_settings);
856
857 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
858
859 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
860 &pipe_ctx->stream->bit_depth_params);
861 build_clamping_params(pipe_ctx->stream);
862}
863
864static enum dc_status build_mapped_resource(
865 const struct dc *dc,
866 struct dc_state *context,
867 struct dc_stream_state *stream)
868{
869 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889 if (!pipe_ctx)
890 return DC_ERROR_UNEXPECTED;
891
892 build_pipe_hw_param(pipe_ctx);
893 return DC_OK;
894}
895
896enum dc_status dcn10_add_stream_to_ctx(
897 struct dc *dc,
898 struct dc_state *new_ctx,
899 struct dc_stream_state *dc_stream)
900{
901 enum dc_status result = DC_ERROR_UNEXPECTED;
902
903 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
904
905 if (result == DC_OK)
906 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
907
908
909 if (result == DC_OK)
910 result = build_mapped_resource(dc, new_ctx, dc_stream);
911
912 return result;
913}
914
915static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
916 struct dc_state *context,
917 const struct resource_pool *pool,
918 struct dc_stream_state *stream)
919{
920 struct resource_context *res_ctx = &context->res_ctx;
921 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
922 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
923
924 if (!head_pipe) {
925 ASSERT(0);
926 return NULL;
927 }
928
929 if (!idle_pipe)
930 return NULL;
931
932 idle_pipe->stream = head_pipe->stream;
933 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
934 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
935 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
936
937 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
938 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
939 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
940 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
941
942 return idle_pipe;
943}
944
945static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
946 const struct dc_dcc_surface_param *input,
947 struct dc_surface_dcc_cap *output)
948{
949 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
950 dc->res_pool->hubbub,
951 input,
952 output);
953}
954
955static void dcn10_destroy_resource_pool(struct resource_pool **pool)
956{
957 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
958
959 destruct(dcn10_pool);
960 kfree(dcn10_pool);
961 *pool = NULL;
962}
963
964static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
965{
966 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
967 && caps->max_video_width != 0
968 && plane_state->src_rect.width > caps->max_video_width)
969 return DC_FAIL_SURFACE_VALIDATE;
970
971 return DC_OK;
972}
973
974static struct dc_cap_funcs cap_funcs = {
975 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
976};
977
978static struct resource_funcs dcn10_res_pool_funcs = {
979 .destroy = dcn10_destroy_resource_pool,
980 .link_enc_create = dcn10_link_encoder_create,
981 .validate_bandwidth = dcn_validate_bandwidth,
982 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
983 .validate_plane = dcn10_validate_plane,
984 .add_stream_to_ctx = dcn10_add_stream_to_ctx
985};
986
987static uint32_t read_pipe_fuses(struct dc_context *ctx)
988{
989 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
990
991 value = value & 0xf;
992 return value;
993}
994
995static bool construct(
996 uint8_t num_virtual_links,
997 struct dc *dc,
998 struct dcn10_resource_pool *pool)
999{
1000 int i;
1001 int j;
1002 struct dc_context *ctx = dc->ctx;
1003 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1004
1005 ctx->dc_bios->regs = &bios_regs;
1006
1007 pool->base.res_cap = &res_cap;
1008 pool->base.funcs = &dcn10_res_pool_funcs;
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1019
1020
1021 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1022
1023 dc->caps.max_video_width = 3840;
1024 dc->caps.max_downscale_ratio = 200;
1025 dc->caps.i2c_speed_in_khz = 100;
1026 dc->caps.max_cursor_size = 256;
1027 dc->caps.max_slave_planes = 1;
1028 dc->caps.is_apu = true;
1029 dc->caps.post_blend_color_processing = false;
1030
1031 dc->caps.force_dp_tps4_for_cp2520 = true;
1032
1033 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1034 dc->debug = debug_defaults_drv;
1035 else
1036 dc->debug = debug_defaults_diags;
1037
1038
1039
1040
1041
1042 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1043 dcn10_clock_source_create(ctx, ctx->dc_bios,
1044 CLOCK_SOURCE_COMBO_PHY_PLL0,
1045 &clk_src_regs[0], false);
1046 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1047 dcn10_clock_source_create(ctx, ctx->dc_bios,
1048 CLOCK_SOURCE_COMBO_PHY_PLL1,
1049 &clk_src_regs[1], false);
1050 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1051 dcn10_clock_source_create(ctx, ctx->dc_bios,
1052 CLOCK_SOURCE_COMBO_PHY_PLL2,
1053 &clk_src_regs[2], false);
1054 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1055 dcn10_clock_source_create(ctx, ctx->dc_bios,
1056 CLOCK_SOURCE_COMBO_PHY_PLL3,
1057 &clk_src_regs[3], false);
1058
1059 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1060
1061 pool->base.dp_clock_source =
1062 dcn10_clock_source_create(ctx, ctx->dc_bios,
1063 CLOCK_SOURCE_ID_DP_DTO,
1064
1065 &clk_src_regs[0], true);
1066
1067 for (i = 0; i < pool->base.clk_src_count; i++) {
1068 if (pool->base.clock_sources[i] == NULL) {
1069 dm_error("DC: failed to create clock sources!\n");
1070 BREAK_TO_DEBUGGER();
1071 goto fail;
1072 }
1073 }
1074
1075 pool->base.display_clock = dce120_disp_clk_create(ctx);
1076 if (pool->base.display_clock == NULL) {
1077 dm_error("DC: failed to create display clock!\n");
1078 BREAK_TO_DEBUGGER();
1079 goto fail;
1080 }
1081
1082 pool->base.dmcu = dcn10_dmcu_create(ctx,
1083 &dmcu_regs,
1084 &dmcu_shift,
1085 &dmcu_mask);
1086 if (pool->base.dmcu == NULL) {
1087 dm_error("DC: failed to create dmcu!\n");
1088 BREAK_TO_DEBUGGER();
1089 goto fail;
1090 }
1091
1092 pool->base.abm = dce_abm_create(ctx,
1093 &abm_regs,
1094 &abm_shift,
1095 &abm_mask);
1096 if (pool->base.abm == NULL) {
1097 dm_error("DC: failed to create abm!\n");
1098 BREAK_TO_DEBUGGER();
1099 goto fail;
1100 }
1101
1102 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
1103 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1104 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1105
1106 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1107 dc->dcn_soc->urgent_latency = 3;
1108 dc->debug.disable_dmcu = true;
1109 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1110 }
1111
1112
1113 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1114 ASSERT(dc->dcn_soc->number_of_channels < 3);
1115 if (dc->dcn_soc->number_of_channels == 0)
1116 dc->dcn_soc->number_of_channels = 2;
1117
1118 if (dc->dcn_soc->number_of_channels == 1) {
1119 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1120 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1121 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1122 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1123 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1124 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1125 }
1126 }
1127
1128 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1129
1130 if (!dc->debug.disable_pplib_clock_request)
1131 dcn_bw_update_from_pplib(dc);
1132 dcn_bw_sync_calcs_and_dml(dc);
1133 if (!dc->debug.disable_pplib_wm_range) {
1134 dc->res_pool = &pool->base;
1135 dcn_bw_notify_pplib_of_wm_ranges(dc);
1136 }
1137
1138 {
1139 struct irq_service_init_data init_data;
1140 init_data.ctx = dc->ctx;
1141 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1142 if (!pool->base.irqs)
1143 goto fail;
1144 }
1145
1146
1147 j = 0;
1148
1149 for (i = 0; i < pool->base.pipe_count; i++) {
1150
1151
1152
1153 if ((pipe_fuses & (1 << i)) != 0)
1154 continue;
1155
1156 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1157 if (pool->base.hubps[j] == NULL) {
1158 BREAK_TO_DEBUGGER();
1159 dm_error(
1160 "DC: failed to create memory input!\n");
1161 goto fail;
1162 }
1163
1164 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1165 if (pool->base.ipps[j] == NULL) {
1166 BREAK_TO_DEBUGGER();
1167 dm_error(
1168 "DC: failed to create input pixel processor!\n");
1169 goto fail;
1170 }
1171
1172 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1173 if (pool->base.dpps[j] == NULL) {
1174 BREAK_TO_DEBUGGER();
1175 dm_error(
1176 "DC: failed to create dpp!\n");
1177 goto fail;
1178 }
1179
1180 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1181 if (pool->base.opps[j] == NULL) {
1182 BREAK_TO_DEBUGGER();
1183 dm_error(
1184 "DC: failed to create output pixel processor!\n");
1185 goto fail;
1186 }
1187
1188 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1189 ctx, i);
1190 if (pool->base.timing_generators[j] == NULL) {
1191 BREAK_TO_DEBUGGER();
1192 dm_error("DC: failed to create tg!\n");
1193 goto fail;
1194 }
1195
1196
1197 j++;
1198 }
1199
1200
1201 pool->base.pipe_count = j;
1202 pool->base.timing_generator_count = j;
1203
1204
1205
1206
1207 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1208 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1209
1210 pool->base.mpc = dcn10_mpc_create(ctx);
1211 if (pool->base.mpc == NULL) {
1212 BREAK_TO_DEBUGGER();
1213 dm_error("DC: failed to create mpc!\n");
1214 goto fail;
1215 }
1216
1217 pool->base.hubbub = dcn10_hubbub_create(ctx);
1218 if (pool->base.hubbub == NULL) {
1219 BREAK_TO_DEBUGGER();
1220 dm_error("DC: failed to create hubbub!\n");
1221 goto fail;
1222 }
1223
1224 if (!resource_construct(num_virtual_links, dc, &pool->base,
1225 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1226 &res_create_funcs : &res_create_maximus_funcs)))
1227 goto fail;
1228
1229 dcn10_hw_sequencer_construct(dc);
1230 dc->caps.max_planes = pool->base.pipe_count;
1231
1232 dc->cap_funcs = cap_funcs;
1233
1234 return true;
1235
1236fail:
1237
1238 destruct(pool);
1239
1240 return false;
1241}
1242
1243struct resource_pool *dcn10_create_resource_pool(
1244 uint8_t num_virtual_links,
1245 struct dc *dc)
1246{
1247 struct dcn10_resource_pool *pool =
1248 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1249
1250 if (!pool)
1251 return NULL;
1252
1253 if (construct(num_virtual_links, dc, pool))
1254 return &pool->base;
1255
1256 BREAK_TO_DEBUGGER();
1257 return NULL;
1258}
1259