1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25#ifndef __DISPLAY_MODE_STRUCTS_H__ 26#define __DISPLAY_MODE_STRUCTS_H__ 27 28typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 29typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 30typedef struct _vcs_dpi_ip_params_st ip_params_st; 31typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 32typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 33typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st; 34typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 35typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 36typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 37typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 38typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 39typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 40typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st; 41typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st; 42typedef struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_watermarks_st; 43typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st; 44typedef struct _vcs_dpi_vratio_pre_st vratio_pre_st; 45typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 46typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 47typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 48typedef struct _vcs_dpi_display_cur_rq_dlg_params_st display_cur_rq_dlg_params_st; 49typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 50typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 51typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 52typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 53typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 54typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 55typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 56typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 57typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 58typedef struct _vcs_dpi_display_dlg_prefetch_param_st display_dlg_prefetch_param_st; 59typedef struct _vcs_dpi_display_pipe_clock_st display_pipe_clock_st; 60typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 61 62struct _vcs_dpi_voltage_scaling_st { 63 int state; 64 double dscclk_mhz; 65 double dcfclk_mhz; 66 double socclk_mhz; 67 double dram_speed_mhz; 68 double fabricclk_mhz; 69 double dispclk_mhz; 70 double dram_bw_per_chan_gbps; 71 double phyclk_mhz; 72 double dppclk_mhz; 73}; 74 75struct _vcs_dpi_soc_bounding_box_st { 76 double sr_exit_time_us; 77 double sr_enter_plus_exit_time_us; 78 double urgent_latency_us; 79 double urgent_latency_pixel_data_only_us; 80 double urgent_latency_pixel_mixed_with_vm_data_us; 81 double urgent_latency_vm_data_only_us; 82 double writeback_latency_us; 83 double ideal_dram_bw_after_urgent_percent; 84 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 85 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 86 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 87 double max_avg_sdp_bw_use_normal_percent; 88 double max_avg_dram_bw_use_normal_percent; 89 unsigned int max_request_size_bytes; 90 double downspread_percent; 91 double dram_page_open_time_ns; 92 double dram_rw_turnaround_time_ns; 93 double dram_return_buffer_per_channel_bytes; 94 double dram_channel_width_bytes; 95 double fabric_datapath_to_dcn_data_return_bytes; 96 double dcn_downspread_percent; 97 double dispclk_dppclk_vco_speed_mhz; 98 double dfs_vco_period_ps; 99 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 100 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 101 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 102 unsigned int round_trip_ping_latency_dcfclk_cycles; 103 unsigned int urgent_out_of_order_return_per_channel_bytes; 104 unsigned int channel_interleave_bytes; 105 unsigned int num_banks; 106 unsigned int num_chans; 107 unsigned int vmm_page_size_bytes; 108 double dram_clock_change_latency_us; 109 double writeback_dram_clock_change_latency_us; 110 unsigned int return_bus_width_bytes; 111 unsigned int voltage_override; 112 double xfc_bus_transport_time_us; 113 double xfc_xbuf_latency_tolerance_us; 114 int use_urgent_burst_bw; 115 struct _vcs_dpi_voltage_scaling_st clock_limits[7]; 116}; 117 118struct _vcs_dpi_ip_params_st { 119 bool gpuvm_enable; 120 bool hostvm_enable; 121 unsigned int gpuvm_max_page_table_levels; 122 unsigned int hostvm_max_page_table_levels; 123 unsigned int hostvm_cached_page_table_levels; 124 unsigned int pte_group_size_bytes; 125 unsigned int max_inter_dcn_tile_repeaters; 126 unsigned int num_dsc; 127 unsigned int odm_capable; 128 unsigned int rob_buffer_size_kbytes; 129 unsigned int det_buffer_size_kbytes; 130 unsigned int dpte_buffer_size_in_pte_reqs; 131 unsigned int pde_proc_buffer_size_64k_reqs; 132 unsigned int dpp_output_buffer_pixels; 133 unsigned int opp_output_buffer_lines; 134 unsigned int pixel_chunk_size_kbytes; 135 unsigned char pte_enable; 136 unsigned int pte_chunk_size_kbytes; 137 unsigned int meta_chunk_size_kbytes; 138 unsigned int writeback_chunk_size_kbytes; 139 unsigned int line_buffer_size_bits; 140 unsigned int max_line_buffer_lines; 141 unsigned int writeback_luma_buffer_size_kbytes; 142 unsigned int writeback_chroma_buffer_size_kbytes; 143 unsigned int writeback_chroma_line_buffer_width_pixels; 144 unsigned int max_page_table_levels; 145 unsigned int max_num_dpp; 146 unsigned int max_num_otg; 147 unsigned int cursor_chunk_size; 148 unsigned int cursor_buffer_size; 149 unsigned int max_num_wb; 150 unsigned int max_dchub_pscl_bw_pix_per_clk; 151 unsigned int max_pscl_lb_bw_pix_per_clk; 152 unsigned int max_lb_vscl_bw_pix_per_clk; 153 unsigned int max_vscl_hscl_bw_pix_per_clk; 154 double max_hscl_ratio; 155 double max_vscl_ratio; 156 unsigned int hscl_mults; 157 unsigned int vscl_mults; 158 unsigned int max_hscl_taps; 159 unsigned int max_vscl_taps; 160 unsigned int xfc_supported; 161 unsigned int xfc_fill_constant_bytes; 162 double dispclk_ramp_margin_percent; 163 double xfc_fill_bw_overhead_percent; 164 double underscan_factor; 165 unsigned int min_vblank_lines; 166 unsigned int dppclk_delay_subtotal; 167 unsigned int dispclk_delay_subtotal; 168 unsigned int dcfclk_cstate_latency; 169 unsigned int dppclk_delay_scl; 170 unsigned int dppclk_delay_scl_lb_only; 171 unsigned int dppclk_delay_cnvc_formatter; 172 unsigned int dppclk_delay_cnvc_cursor; 173 unsigned int is_line_buffer_bpp_fixed; 174 unsigned int line_buffer_fixed_bpp; 175 unsigned int dcc_supported; 176 177 unsigned int IsLineBufferBppFixed; 178 unsigned int LineBufferFixedBpp; 179 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 180 unsigned int bug_forcing_LC_req_same_size_fixed; 181}; 182 183struct _vcs_dpi_display_xfc_params_st { 184 double xfc_tslv_vready_offset_us; 185 double xfc_tslv_vupdate_width_us; 186 double xfc_tslv_vupdate_offset_us; 187 int xfc_slv_chunk_size_bytes; 188}; 189 190struct _vcs_dpi_display_pipe_source_params_st { 191 int source_format; 192 unsigned char dcc; 193 unsigned int dcc_override; 194 unsigned int dcc_rate; 195 unsigned char dcc_use_global; 196 unsigned char vm; 197 bool gpuvm; // gpuvm enabled 198 bool hostvm; // hostvm enabled 199 bool gpuvm_levels_force_en; 200 unsigned int gpuvm_levels_force; 201 bool hostvm_levels_force_en; 202 unsigned int hostvm_levels_force; 203 int source_scan; 204 int sw_mode; 205 int macro_tile_size; 206 unsigned char is_display_sw; 207 unsigned int viewport_width; 208 unsigned int viewport_height; 209 unsigned int viewport_y_y; 210 unsigned int viewport_y_c; 211 unsigned int viewport_width_c; 212 unsigned int viewport_height_c; 213 unsigned int data_pitch; 214 unsigned int data_pitch_c; 215 unsigned int meta_pitch; 216 unsigned int meta_pitch_c; 217 unsigned int cur0_src_width; 218 int cur0_bpp; 219 unsigned int cur1_src_width; 220 int cur1_bpp; 221 int num_cursors; 222 unsigned char is_hsplit; 223 unsigned char dynamic_metadata_enable; 224 unsigned int dynamic_metadata_lines_before_active; 225 unsigned int dynamic_metadata_xmit_bytes; 226 unsigned int hsplit_grp; 227 unsigned char xfc_enable; 228 unsigned char xfc_slave; 229 struct _vcs_dpi_display_xfc_params_st xfc_params; 230}; 231struct writeback_st { 232 int wb_src_height; 233 int wb_dst_width; 234 int wb_dst_height; 235 int wb_pixel_format; 236 int wb_htaps_luma; 237 int wb_vtaps_luma; 238 int wb_htaps_chroma; 239 int wb_vtaps_chroma; 240 double wb_hratio; 241 double wb_vratio; 242}; 243 244struct _vcs_dpi_display_output_params_st { 245 int dp_lanes; 246 int output_bpp; 247 int dsc_enable; 248 int wb_enable; 249 int num_active_wb; 250 int output_bpc; 251 int output_type; 252 int output_format; 253 int output_standard; 254 int dsc_slices; 255 struct writeback_st wb; 256}; 257 258struct _vcs_dpi_display_bandwidth_st { 259 double total_bw_consumed_gbps; 260 double guaranteed_urgent_return_bw_gbps; 261}; 262 263struct _vcs_dpi_scaler_ratio_depth_st { 264 double hscl_ratio; 265 double vscl_ratio; 266 double hscl_ratio_c; 267 double vscl_ratio_c; 268 double vinit; 269 double vinit_c; 270 double vinit_bot; 271 double vinit_bot_c; 272 int lb_depth; 273 int scl_enable; 274}; 275 276struct _vcs_dpi_scaler_taps_st { 277 unsigned int htaps; 278 unsigned int vtaps; 279 unsigned int htaps_c; 280 unsigned int vtaps_c; 281}; 282 283struct _vcs_dpi_display_pipe_dest_params_st { 284 unsigned int recout_width; 285 unsigned int recout_height; 286 unsigned int full_recout_width; 287 unsigned int full_recout_height; 288 unsigned int hblank_start; 289 unsigned int hblank_end; 290 unsigned int vblank_start; 291 unsigned int vblank_end; 292 unsigned int htotal; 293 unsigned int vtotal; 294 unsigned int vactive; 295 unsigned int hactive; 296 unsigned int vstartup_start; 297 unsigned int vupdate_offset; 298 unsigned int vupdate_width; 299 unsigned int vready_offset; 300 unsigned char interlaced; 301 unsigned char underscan; 302 double pixel_rate_mhz; 303 unsigned char synchronized_vblank_all_planes; 304 unsigned char otg_inst; 305 unsigned char odm_split_cnt; 306 unsigned char odm_combine; 307}; 308 309struct _vcs_dpi_display_pipe_params_st { 310 display_pipe_source_params_st src; 311 display_pipe_dest_params_st dest; 312 scaler_ratio_depth_st scale_ratio_depth; 313 scaler_taps_st scale_taps; 314}; 315 316struct _vcs_dpi_display_clocks_and_cfg_st { 317 int voltage; 318 double dppclk_mhz; 319 double refclk_mhz; 320 double dispclk_mhz; 321 double dcfclk_mhz; 322 double socclk_mhz; 323}; 324 325struct _vcs_dpi_display_e2e_pipe_params_st { 326 display_pipe_params_st pipe; 327 display_output_params_st dout; 328 display_clocks_and_cfg_st clks_cfg; 329}; 330 331struct _vcs_dpi_dchub_buffer_sizing_st { 332 unsigned int swath_width_y; 333 unsigned int swath_height_y; 334 unsigned int swath_height_c; 335 unsigned int detail_buffer_size_y; 336}; 337 338struct _vcs_dpi_watermarks_perf_st { 339 double stutter_eff_in_active_region_percent; 340 double urgent_latency_supported_us; 341 double non_urgent_latency_supported_us; 342 double dram_clock_change_margin_us; 343 double dram_access_eff_percent; 344}; 345 346struct _vcs_dpi_cstate_pstate_watermarks_st { 347 double cstate_exit_us; 348 double cstate_enter_plus_exit_us; 349 double pstate_change_us; 350}; 351 352struct _vcs_dpi_wm_calc_pipe_params_st { 353 unsigned int num_dpp; 354 int voltage; 355 int output_type; 356 double dcfclk_mhz; 357 double socclk_mhz; 358 double dppclk_mhz; 359 double pixclk_mhz; 360 unsigned char interlace_en; 361 unsigned char pte_enable; 362 unsigned char dcc_enable; 363 double dcc_rate; 364 double bytes_per_pixel_c; 365 double bytes_per_pixel_y; 366 unsigned int swath_width_y; 367 unsigned int swath_height_y; 368 unsigned int swath_height_c; 369 unsigned int det_buffer_size_y; 370 double h_ratio; 371 double v_ratio; 372 unsigned int h_taps; 373 unsigned int h_total; 374 unsigned int v_total; 375 unsigned int v_active; 376 unsigned int e2e_index; 377 double display_pipe_line_delivery_time; 378 double read_bw; 379 unsigned int lines_in_det_y; 380 unsigned int lines_in_det_y_rounded_down_to_swath; 381 double full_det_buffering_time; 382 double dcfclk_deepsleep_mhz_per_plane; 383}; 384 385struct _vcs_dpi_vratio_pre_st { 386 double vratio_pre_l; 387 double vratio_pre_c; 388}; 389 390struct _vcs_dpi_display_data_rq_misc_params_st { 391 unsigned int full_swath_bytes; 392 unsigned int stored_swath_bytes; 393 unsigned int blk256_height; 394 unsigned int blk256_width; 395 unsigned int req_height; 396 unsigned int req_width; 397}; 398 399struct _vcs_dpi_display_data_rq_sizing_params_st { 400 unsigned int chunk_bytes; 401 unsigned int min_chunk_bytes; 402 unsigned int meta_chunk_bytes; 403 unsigned int min_meta_chunk_bytes; 404 unsigned int mpte_group_bytes; 405 unsigned int dpte_group_bytes; 406}; 407 408struct _vcs_dpi_display_data_rq_dlg_params_st { 409 unsigned int swath_width_ub; 410 unsigned int swath_height; 411 unsigned int req_per_swath_ub; 412 unsigned int meta_pte_bytes_per_frame_ub; 413 unsigned int dpte_req_per_row_ub; 414 unsigned int dpte_groups_per_row_ub; 415 unsigned int dpte_row_height; 416 unsigned int dpte_bytes_per_row_ub; 417 unsigned int meta_chunks_per_row_ub; 418 unsigned int meta_req_per_row_ub; 419 unsigned int meta_row_height; 420 unsigned int meta_bytes_per_row_ub; 421}; 422 423struct _vcs_dpi_display_cur_rq_dlg_params_st { 424 unsigned char enable; 425 unsigned int swath_height; 426 unsigned int req_per_line; 427}; 428 429struct _vcs_dpi_display_rq_dlg_params_st { 430 display_data_rq_dlg_params_st rq_l; 431 display_data_rq_dlg_params_st rq_c; 432 display_cur_rq_dlg_params_st rq_cur0; 433}; 434 435struct _vcs_dpi_display_rq_sizing_params_st { 436 display_data_rq_sizing_params_st rq_l; 437 display_data_rq_sizing_params_st rq_c; 438}; 439 440struct _vcs_dpi_display_rq_misc_params_st { 441 display_data_rq_misc_params_st rq_l; 442 display_data_rq_misc_params_st rq_c; 443}; 444 445struct _vcs_dpi_display_rq_params_st { 446 unsigned char yuv420; 447 unsigned char yuv420_10bpc; 448 display_rq_misc_params_st misc; 449 display_rq_sizing_params_st sizing; 450 display_rq_dlg_params_st dlg; 451}; 452 453struct _vcs_dpi_display_dlg_regs_st { 454 unsigned int refcyc_h_blank_end; 455 unsigned int dlg_vblank_end; 456 unsigned int min_dst_y_next_start; 457 unsigned int refcyc_per_htotal; 458 unsigned int refcyc_x_after_scaler; 459 unsigned int dst_y_after_scaler; 460 unsigned int dst_y_prefetch; 461 unsigned int dst_y_per_vm_vblank; 462 unsigned int dst_y_per_row_vblank; 463 unsigned int dst_y_per_vm_flip; 464 unsigned int dst_y_per_row_flip; 465 unsigned int ref_freq_to_pix_freq; 466 unsigned int vratio_prefetch; 467 unsigned int vratio_prefetch_c; 468 unsigned int refcyc_per_pte_group_vblank_l; 469 unsigned int refcyc_per_pte_group_vblank_c; 470 unsigned int refcyc_per_meta_chunk_vblank_l; 471 unsigned int refcyc_per_meta_chunk_vblank_c; 472 unsigned int refcyc_per_pte_group_flip_l; 473 unsigned int refcyc_per_pte_group_flip_c; 474 unsigned int refcyc_per_meta_chunk_flip_l; 475 unsigned int refcyc_per_meta_chunk_flip_c; 476 unsigned int dst_y_per_pte_row_nom_l; 477 unsigned int dst_y_per_pte_row_nom_c; 478 unsigned int refcyc_per_pte_group_nom_l; 479 unsigned int refcyc_per_pte_group_nom_c; 480 unsigned int dst_y_per_meta_row_nom_l; 481 unsigned int dst_y_per_meta_row_nom_c; 482 unsigned int refcyc_per_meta_chunk_nom_l; 483 unsigned int refcyc_per_meta_chunk_nom_c; 484 unsigned int refcyc_per_line_delivery_pre_l; 485 unsigned int refcyc_per_line_delivery_pre_c; 486 unsigned int refcyc_per_line_delivery_l; 487 unsigned int refcyc_per_line_delivery_c; 488 unsigned int chunk_hdl_adjust_cur0; 489 unsigned int chunk_hdl_adjust_cur1; 490 unsigned int vready_after_vcount0; 491 unsigned int dst_y_offset_cur0; 492 unsigned int dst_y_offset_cur1; 493 unsigned int xfc_reg_transfer_delay; 494 unsigned int xfc_reg_precharge_delay; 495 unsigned int xfc_reg_remote_surface_flip_latency; 496 unsigned int xfc_reg_prefetch_margin; 497 unsigned int dst_y_delta_drq_limit; 498}; 499 500struct _vcs_dpi_display_ttu_regs_st { 501 unsigned int qos_level_low_wm; 502 unsigned int qos_level_high_wm; 503 unsigned int min_ttu_vblank; 504 unsigned int qos_level_flip; 505 unsigned int refcyc_per_req_delivery_l; 506 unsigned int refcyc_per_req_delivery_c; 507 unsigned int refcyc_per_req_delivery_cur0; 508 unsigned int refcyc_per_req_delivery_cur1; 509 unsigned int refcyc_per_req_delivery_pre_l; 510 unsigned int refcyc_per_req_delivery_pre_c; 511 unsigned int refcyc_per_req_delivery_pre_cur0; 512 unsigned int refcyc_per_req_delivery_pre_cur1; 513 unsigned int qos_level_fixed_l; 514 unsigned int qos_level_fixed_c; 515 unsigned int qos_level_fixed_cur0; 516 unsigned int qos_level_fixed_cur1; 517 unsigned int qos_ramp_disable_l; 518 unsigned int qos_ramp_disable_c; 519 unsigned int qos_ramp_disable_cur0; 520 unsigned int qos_ramp_disable_cur1; 521}; 522 523struct _vcs_dpi_display_data_rq_regs_st { 524 unsigned int chunk_size; 525 unsigned int min_chunk_size; 526 unsigned int meta_chunk_size; 527 unsigned int min_meta_chunk_size; 528 unsigned int dpte_group_size; 529 unsigned int mpte_group_size; 530 unsigned int swath_height; 531 unsigned int pte_row_height_linear; 532}; 533 534struct _vcs_dpi_display_rq_regs_st { 535 display_data_rq_regs_st rq_regs_l; 536 display_data_rq_regs_st rq_regs_c; 537 unsigned int drq_expansion_mode; 538 unsigned int prq_expansion_mode; 539 unsigned int mrq_expansion_mode; 540 unsigned int crq_expansion_mode; 541 unsigned int plane1_base_address; 542}; 543 544struct _vcs_dpi_display_dlg_sys_params_st { 545 double t_mclk_wm_us; 546 double t_urg_wm_us; 547 double t_sr_wm_us; 548 double t_extra_us; 549 double mem_trip_us; 550 double t_srx_delay_us; 551 double deepsleep_dcfclk_mhz; 552 double total_flip_bw; 553 unsigned int total_flip_bytes; 554}; 555 556struct _vcs_dpi_display_dlg_prefetch_param_st { 557 double prefetch_bw; 558 unsigned int flip_bytes; 559}; 560 561struct _vcs_dpi_display_pipe_clock_st { 562 double dcfclk_mhz; 563 double dispclk_mhz; 564 double socclk_mhz; 565 double dscclk_mhz[6]; 566 double dppclk_mhz[6]; 567}; 568 569struct _vcs_dpi_display_arb_params_st { 570 int max_req_outstanding; 571 int min_req_outstanding; 572 int sat_level_us; 573}; 574 575#endif /*__DISPLAY_MODE_STRUCTS_H__*/ 576