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26#ifndef __DAL_BIOS_PARSER_TYPES_H__
27
28#define __DAL_BIOS_PARSER_TYPES_H__
29
30#include "dm_services.h"
31#include "include/signal_types.h"
32#include "include/grph_object_ctrl_defs.h"
33#include "include/gpio_types.h"
34#include "include/link_service_types.h"
35
36
37enum as_signal_type {
38 AS_SIGNAL_TYPE_NONE = 0L,
39 AS_SIGNAL_TYPE_DVI,
40 AS_SIGNAL_TYPE_HDMI,
41 AS_SIGNAL_TYPE_LVDS,
42 AS_SIGNAL_TYPE_DISPLAY_PORT,
43 AS_SIGNAL_TYPE_GPU_PLL,
44 AS_SIGNAL_TYPE_UNKNOWN
45};
46
47enum bp_result {
48 BP_RESULT_OK = 0,
49 BP_RESULT_BADINPUT,
50 BP_RESULT_BADBIOSTABLE,
51 BP_RESULT_UNSUPPORTED,
52 BP_RESULT_NORECORD,
53 BP_RESULT_FAILURE
54};
55
56enum bp_encoder_control_action {
57
58 ENCODER_CONTROL_DISABLE = 0,
59 ENCODER_CONTROL_ENABLE,
60 ENCODER_CONTROL_SETUP,
61 ENCODER_CONTROL_INIT
62};
63
64enum bp_transmitter_control_action {
65
66 TRANSMITTER_CONTROL_DISABLE = 0,
67 TRANSMITTER_CONTROL_ENABLE,
68 TRANSMITTER_CONTROL_BACKLIGHT_OFF,
69 TRANSMITTER_CONTROL_BACKLIGHT_ON,
70 TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
71 TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
72 TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
73 TRANSMITTER_CONTROL_INIT,
74 TRANSMITTER_CONTROL_DEACTIVATE,
75 TRANSMITTER_CONTROL_ACTIAVATE,
76 TRANSMITTER_CONTROL_SETUP,
77 TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
78
79
80
81 TRANSMITTER_CONTROL_POWER_ON,
82
83
84
85 TRANSMITTER_CONTROL_POWER_OFF
86};
87
88enum bp_external_encoder_control_action {
89 EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
90 EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
91 EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
92 EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
93 EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
94 EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
95};
96
97enum bp_pipe_control_action {
98 ASIC_PIPE_DISABLE = 0,
99 ASIC_PIPE_ENABLE,
100 ASIC_PIPE_INIT
101};
102
103struct bp_encoder_control {
104 enum bp_encoder_control_action action;
105 enum engine_id engine_id;
106 enum transmitter transmitter;
107 enum signal_type signal;
108 enum dc_lane_count lanes_number;
109 enum dc_color_depth color_depth;
110 bool enable_dp_audio;
111 uint32_t pixel_clock;
112};
113
114struct bp_external_encoder_control {
115 enum bp_external_encoder_control_action action;
116 enum engine_id engine_id;
117 enum dc_link_rate link_rate;
118 enum dc_lane_count lanes_number;
119 enum signal_type signal;
120 enum dc_color_depth color_depth;
121 bool coherent;
122 struct graphics_object_id encoder_id;
123 struct graphics_object_id connector_obj_id;
124 uint32_t pixel_clock;
125};
126
127struct bp_crtc_source_select {
128 enum engine_id engine_id;
129 enum controller_id controller_id;
130
131 enum signal_type signal;
132
133 enum signal_type sink_signal;
134 enum display_output_bit_depth display_output_bit_depth;
135 bool enable_dp_audio;
136};
137
138struct bp_transmitter_control {
139 enum bp_transmitter_control_action action;
140 enum engine_id engine_id;
141 enum transmitter transmitter;
142 enum dc_lane_count lanes_number;
143 enum clock_source_id pll_id;
144 enum signal_type signal;
145 enum dc_color_depth color_depth;
146 enum hpd_source_id hpd_sel;
147 struct graphics_object_id connector_obj_id;
148
149
150
151 uint32_t pixel_clock;
152 uint32_t lane_select;
153 uint32_t lane_settings;
154 bool coherent;
155 bool multi_path;
156 bool single_pll_mode;
157};
158
159struct bp_hw_crtc_timing_parameters {
160 enum controller_id controller_id;
161
162 uint32_t h_total;
163 uint32_t h_addressable;
164 uint32_t h_overscan_left;
165 uint32_t h_overscan_right;
166 uint32_t h_sync_start;
167 uint32_t h_sync_width;
168
169
170 uint32_t v_total;
171 uint32_t v_addressable;
172 uint32_t v_overscan_top;
173 uint32_t v_overscan_bottom;
174 uint32_t v_sync_start;
175 uint32_t v_sync_width;
176
177 struct timing_flags {
178 uint32_t INTERLACE:1;
179 uint32_t PIXEL_REPETITION:4;
180 uint32_t HSYNC_POSITIVE_POLARITY:1;
181 uint32_t VSYNC_POSITIVE_POLARITY:1;
182 uint32_t HORZ_COUNT_BY_TWO:1;
183 } flags;
184};
185
186struct bp_adjust_pixel_clock_parameters {
187
188 enum signal_type signal_type;
189
190 struct graphics_object_id encoder_object_id;
191
192
193
194 uint32_t pixel_clock;
195
196 uint32_t adjusted_pixel_clock;
197
198
199 uint32_t reference_divider;
200
201
202 uint32_t pixel_clock_post_divider;
203
204 bool ss_enable;
205};
206
207struct bp_pixel_clock_parameters {
208 enum controller_id controller_id;
209 enum clock_source_id pll_id;
210
211 enum signal_type signal_type;
212
213
214 uint32_t target_pixel_clock;
215
216 uint32_t reference_divider;
217
218 uint32_t feedback_divider;
219
220 uint32_t fractional_feedback_divider;
221
222 uint32_t pixel_clock_post_divider;
223 struct graphics_object_id encoder_object_id;
224
225
226 uint32_t dfs_bypass_display_clock;
227
228 enum transmitter_color_depth color_depth;
229
230 struct program_pixel_clock_flags {
231 uint32_t FORCE_PROGRAMMING_OF_PLL:1;
232
233
234 uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
235
236 uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
237
238 uint32_t PROGRAM_PHY_PLL_ONLY:1;
239
240 uint32_t SUPPORT_YUV_420:1;
241
242 uint32_t SET_XTALIN_REF_SRC:1;
243
244 uint32_t SET_GENLOCK_REF_DIV_SRC:1;
245 } flags;
246};
247
248enum bp_dce_clock_type {
249 DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
250 DCECLOCK_TYPE_DPREFCLK = 1
251};
252
253
254struct bp_set_dce_clock_parameters {
255 enum clock_source_id pll_id;
256
257 uint32_t target_clock_frequency;
258
259 enum bp_dce_clock_type clock_type;
260
261 struct set_dce_clock_flags {
262 uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
263
264 uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
265
266 uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
267
268 uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
269 } flags;
270};
271
272struct spread_spectrum_flags {
273
274 uint32_t CENTER_SPREAD:1;
275
276 uint32_t EXTERNAL_SS:1;
277
278 uint32_t DS_TYPE:1;
279};
280
281struct bp_spread_spectrum_parameters {
282 enum clock_source_id pll_id;
283 uint32_t percentage;
284 uint32_t ds_frac_amount;
285
286 union {
287 struct {
288 uint32_t step;
289 uint32_t delay;
290 uint32_t range;
291 } ver1;
292 struct {
293 uint32_t feedback_amount;
294 uint32_t nfrac_amount;
295 uint32_t ds_frac_size;
296 } ds;
297 };
298
299 struct spread_spectrum_flags flags;
300};
301
302struct bp_encoder_cap_info {
303 uint32_t DP_HBR2_CAP:1;
304 uint32_t DP_HBR2_EN:1;
305 uint32_t DP_HBR3_EN:1;
306 uint32_t HDMI_6GB_EN:1;
307 uint32_t RESERVED:30;
308};
309
310#endif
311