1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _nbif_6_1_OFFSET_HEADER 22#define _nbif_6_1_OFFSET_HEADER 23 24 25// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp 26// base address: 0x0 27#define cfgVENDOR_ID 0x0000 // duplicate 28#define cfgDEVICE_ID 0x0002 // duplicate 29#define cfgCOMMAND 0x0004 // duplicate 30#define cfgSTATUS 0x0006 // duplicate 31#define cfgREVISION_ID 0x0008 // duplicate 32#define cfgPROG_INTERFACE 0x0009 // duplicate 33#define cfgSUB_CLASS 0x000a // duplicate 34#define cfgBASE_CLASS 0x000b // duplicate 35#define cfgCACHE_LINE 0x000c // duplicate 36#define cfgLATENCY 0x000d // duplicate 37#define cfgHEADER 0x000e // duplicate 38#define cfgBIST 0x000f // duplicate 39#define cfgBASE_ADDR_1 0x0010 // duplicate 40#define cfgBASE_ADDR_2 0x0014 // duplicate 41#define cfgBASE_ADDR_3 0x0018 // duplicate 42#define cfgBASE_ADDR_4 0x001c // duplicate 43#define cfgBASE_ADDR_5 0x0020 // duplicate 44#define cfgBASE_ADDR_6 0x0024 // duplicate 45#define cfgADAPTER_ID 0x002c // duplicate 46#define cfgROM_BASE_ADDR 0x0030 // duplicate 47#define cfgCAP_PTR 0x0034 // duplicate 48#define cfgINTERRUPT_LINE 0x003c // duplicate 49#define cfgINTERRUPT_PIN 0x003d // duplicate 50#define cfgMIN_GRANT 0x003e // duplicate 51#define cfgMAX_LATENCY 0x003f // duplicate 52#define cfgVENDOR_CAP_LIST 0x0048 // duplicate 53#define cfgADAPTER_ID_W 0x004c // duplicate 54#define cfgPMI_CAP_LIST 0x0050 // duplicate 55#define cfgPMI_CAP 0x0052 // duplicate 56#define cfgPMI_STATUS_CNTL 0x0054 // duplicate 57#define cfgPCIE_CAP_LIST 0x0064 // duplicate 58#define cfgPCIE_CAP 0x0066 // duplicate 59#define cfgDEVICE_CAP 0x0068 // duplicate 60#define cfgDEVICE_CNTL 0x006c // duplicate 61#define cfgDEVICE_STATUS 0x006e // duplicate 62#define cfgLINK_CAP 0x0070 // duplicate 63#define cfgLINK_CNTL 0x0074 // duplicate 64#define cfgLINK_STATUS 0x0076 // duplicate 65#define cfgDEVICE_CAP2 0x0088 // duplicate 66#define cfgDEVICE_CNTL2 0x008c // duplicate 67#define cfgDEVICE_STATUS2 0x008e // duplicate 68#define cfgLINK_CAP2 0x0090 // duplicate 69#define cfgLINK_CNTL2 0x0094 // duplicate 70#define cfgLINK_STATUS2 0x0096 // duplicate 71#define cfgSLOT_CAP2 0x0098 // duplicate 72#define cfgSLOT_CNTL2 0x009c // duplicate 73#define cfgSLOT_STATUS2 0x009e // duplicate 74#define cfgMSI_CAP_LIST 0x00a0 // duplicate 75#define cfgMSI_MSG_CNTL 0x00a2 // duplicate 76#define cfgMSI_MSG_ADDR_LO 0x00a4 // duplicate 77#define cfgMSI_MSG_ADDR_HI 0x00a8 // duplicate 78#define cfgMSI_MSG_DATA 0x00a8 // duplicate 79#define cfgMSI_MSG_DATA_64 0x00ac // duplicate 80#define cfgMSI_MASK 0x00ac // duplicate 81#define cfgMSI_PENDING 0x00b0 // duplicate 82#define cfgMSI_MASK_64 0x00b0 // duplicate 83#define cfgMSI_PENDING_64 0x00b4 // duplicate 84#define cfgMSIX_CAP_LIST 0x00c0 // duplicate 85#define cfgMSIX_MSG_CNTL 0x00c2 // duplicate 86#define cfgMSIX_TABLE 0x00c4 // duplicate 87#define cfgMSIX_PBA 0x00c8 // duplicate 88#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 // duplicate 89#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 // duplicate 90#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 // duplicate 91#define cfgPCIE_VENDOR_SPECIFIC2 0x010c // duplicate 92#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 // duplicate 93#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 // duplicate 94#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 // duplicate 95#define cfgPCIE_PORT_VC_CNTL 0x011c // duplicate 96#define cfgPCIE_PORT_VC_STATUS 0x011e // duplicate 97#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 // duplicate 98#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 // duplicate 99#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a // duplicate 100#define cfgPCIE_VC1_RESOURCE_CAP 0x012c // duplicate 101#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 // duplicate 102#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 // duplicate 103#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 // duplicate 104#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 // duplicate 105#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 // duplicate 106#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 // duplicate 107#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 // duplicate 108#define cfgPCIE_UNCORR_ERR_MASK 0x0158 // duplicate 109#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c // duplicate 110#define cfgPCIE_CORR_ERR_STATUS 0x0160 // duplicate 111#define cfgPCIE_CORR_ERR_MASK 0x0164 // duplicate 112#define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 // duplicate 113#define cfgPCIE_HDR_LOG0 0x016c // duplicate 114#define cfgPCIE_HDR_LOG1 0x0170 // duplicate 115#define cfgPCIE_HDR_LOG2 0x0174 // duplicate 116#define cfgPCIE_HDR_LOG3 0x0178 // duplicate 117#define cfgPCIE_ROOT_ERR_CMD 0x017c // duplicate 118#define cfgPCIE_ROOT_ERR_STATUS 0x0180 // duplicate 119#define cfgPCIE_ERR_SRC_ID 0x0184 // duplicate 120#define cfgPCIE_TLP_PREFIX_LOG0 0x0188 // duplicate 121#define cfgPCIE_TLP_PREFIX_LOG1 0x018c // duplicate 122#define cfgPCIE_TLP_PREFIX_LOG2 0x0190 // duplicate 123#define cfgPCIE_TLP_PREFIX_LOG3 0x0194 // duplicate 124#define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 // duplicate 125#define cfgPCIE_BAR1_CAP 0x0204 // duplicate 126#define cfgPCIE_BAR1_CNTL 0x0208 // duplicate 127#define cfgPCIE_BAR2_CAP 0x020c // duplicate 128#define cfgPCIE_BAR2_CNTL 0x0210 // duplicate 129#define cfgPCIE_BAR3_CAP 0x0214 // duplicate 130#define cfgPCIE_BAR3_CNTL 0x0218 // duplicate 131#define cfgPCIE_BAR4_CAP 0x021c // duplicate 132#define cfgPCIE_BAR4_CNTL 0x0220 // duplicate 133#define cfgPCIE_BAR5_CAP 0x0224 // duplicate 134#define cfgPCIE_BAR5_CNTL 0x0228 // duplicate 135#define cfgPCIE_BAR6_CAP 0x022c // duplicate 136#define cfgPCIE_BAR6_CNTL 0x0230 // duplicate 137#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 // duplicate 138#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 // duplicate 139#define cfgPCIE_PWR_BUDGET_DATA 0x0248 // duplicate 140#define cfgPCIE_PWR_BUDGET_CAP 0x024c // duplicate 141#define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 // duplicate 142#define cfgPCIE_DPA_CAP 0x0254 // duplicate 143#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 // duplicate 144#define cfgPCIE_DPA_STATUS 0x025c // duplicate 145#define cfgPCIE_DPA_CNTL 0x025e // duplicate 146#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 // duplicate 147#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 // duplicate 148#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 // duplicate 149#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 // duplicate 150#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 // duplicate 151#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 // duplicate 152#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 // duplicate 153#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 // duplicate 154#define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 // duplicate 155#define cfgPCIE_LINK_CNTL3 0x0274 // duplicate 156#define cfgPCIE_LANE_ERROR_STATUS 0x0278 // duplicate 157#define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c // duplicate 158#define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e // duplicate 159#define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 // duplicate 160#define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 // duplicate 161#define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 // duplicate 162#define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 // duplicate 163#define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 // duplicate 164#define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a // duplicate 165#define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c // duplicate 166#define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e // duplicate 167#define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 // duplicate 168#define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 // duplicate 169#define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 // duplicate 170#define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 // duplicate 171#define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 // duplicate 172#define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a // duplicate 173#define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 // duplicate 174#define cfgPCIE_ACS_CAP 0x02a4 // duplicate 175#define cfgPCIE_ACS_CNTL 0x02a6 // duplicate 176#define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 // duplicate 177#define cfgPCIE_ATS_CAP 0x02b4 // duplicate 178#define cfgPCIE_ATS_CNTL 0x02b6 // duplicate 179#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 // duplicate 180#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 // duplicate 181#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 // duplicate 182#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 // duplicate 183#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc // duplicate 184#define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 // duplicate 185#define cfgPCIE_PASID_CAP 0x02d4 // duplicate 186#define cfgPCIE_PASID_CNTL 0x02d6 // duplicate 187#define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 // duplicate 188#define cfgPCIE_TPH_REQR_CAP 0x02e4 // duplicate 189#define cfgPCIE_TPH_REQR_CNTL 0x02e8 // duplicate 190#define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 // duplicate 191#define cfgPCIE_MC_CAP 0x02f4 // duplicate 192#define cfgPCIE_MC_CNTL 0x02f6 // duplicate 193#define cfgPCIE_MC_ADDR0 0x02f8 // duplicate 194#define cfgPCIE_MC_ADDR1 0x02fc // duplicate 195#define cfgPCIE_MC_RCV0 0x0300 // duplicate 196#define cfgPCIE_MC_RCV1 0x0304 // duplicate 197#define cfgPCIE_MC_BLOCK_ALL0 0x0308 // duplicate 198#define cfgPCIE_MC_BLOCK_ALL1 0x030c // duplicate 199#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 // duplicate 200#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 // duplicate 201#define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 // duplicate 202#define cfgPCIE_LTR_CAP 0x0324 // duplicate 203#define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 // duplicate 204#define cfgPCIE_ARI_CAP 0x032c // duplicate 205#define cfgPCIE_ARI_CNTL 0x032e // duplicate 206#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 // duplicate 207#define cfgPCIE_SRIOV_CAP 0x0334 // duplicate 208#define cfgPCIE_SRIOV_CONTROL 0x0338 // duplicate 209#define cfgPCIE_SRIOV_STATUS 0x033a // duplicate 210#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c // duplicate 211#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e // duplicate 212#define cfgPCIE_SRIOV_NUM_VFS 0x0340 // duplicate 213#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 // duplicate 214#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 // duplicate 215#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 // duplicate 216#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a // duplicate 217#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c // duplicate 218#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 // duplicate 219#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 // duplicate 220#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 // duplicate 221#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c // duplicate 222#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 // duplicate 223#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 // duplicate 224#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 // duplicate 225#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c // duplicate 226#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 // duplicate 227#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 // duplicate 228#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 // duplicate 229#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c // duplicate 230#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 // duplicate 231#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 // duplicate 232#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 // duplicate 233#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c // duplicate 234#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 // duplicate 235#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 // duplicate 236#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 // duplicate 237#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c // duplicate 238#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 // duplicate 239#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 // duplicate 240#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 // duplicate 241#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c // duplicate 242#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 // duplicate 243#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 // duplicate 244#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 // duplicate 245#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c // duplicate 246#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 // duplicate 247#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 // duplicate 248#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 // duplicate 249#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c // duplicate 250#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 // duplicate 251#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 // duplicate 252#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 // duplicate 253#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c // duplicate 254#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 // duplicate 255#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 // duplicate 256#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 // duplicate 257#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c // duplicate 258#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 // duplicate 259#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 // duplicate 260#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 // duplicate 261#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c // duplicate 262#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x0490 // duplicate 263#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x0494 // duplicate 264#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x0498 // duplicate 265#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x049c // duplicate 266#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04a0 // duplicate 267#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04a4 // duplicate 268#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04a8 // duplicate 269#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04ac // duplicate 270#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04b0 // duplicate 271#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04b4 // duplicate 272#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04b8 // duplicate 273#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04bc // duplicate 274#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04c0 // duplicate 275#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04c4 // duplicate 276#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04c8 // duplicate 277#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04cc // duplicate 278 279 280// addressBlock: bif_cfg_dev0_swds_bifcfgdecp 281// base address: 0x0 282#define mmSUB_BUS_NUMBER_LATENCY 0x0006 // duplicate 283#define mmSUB_BUS_NUMBER_LATENCY_BASE_IDX 0 284#define mmIO_BASE_LIMIT 0x0007 // duplicate 285#define mmIO_BASE_LIMIT_BASE_IDX 0 286#define mmSECONDARY_STATUS 0x0007 // duplicate 287#define mmSECONDARY_STATUS_BASE_IDX 0 288#define mmMEM_BASE_LIMIT 0x0008 // duplicate 289#define mmMEM_BASE_LIMIT_BASE_IDX 0 290#define mmPREF_BASE_LIMIT 0x0009 // duplicate 291#define mmPREF_BASE_LIMIT_BASE_IDX 0 292#define mmPREF_BASE_UPPER 0x000a // duplicate 293#define mmPREF_BASE_UPPER_BASE_IDX 0 294#define mmPREF_LIMIT_UPPER 0x000b // duplicate 295#define mmPREF_LIMIT_UPPER_BASE_IDX 0 296#define mmIO_BASE_LIMIT_HI 0x000c // duplicate 297#define mmIO_BASE_LIMIT_HI_BASE_IDX 0 298#define mmIRQ_BRIDGE_CNTL 0x000f // duplicate 299#define mmIRQ_BRIDGE_CNTL_BASE_IDX 0 300#define mmSLOT_CAP 0x001b // duplicate 301#define mmSLOT_CAP_BASE_IDX 0 302#define mmSLOT_CNTL 0x001c // duplicate 303#define mmSLOT_CNTL_BASE_IDX 0 304#define mmSLOT_STATUS 0x001c // duplicate 305#define mmSLOT_STATUS_BASE_IDX 0 306#define mmSSID_CAP_LIST 0x0030 // duplicate 307#define mmSSID_CAP_LIST_BASE_IDX 0 308#define mmSSID_CAP 0x0031 // duplicate 309#define mmSSID_CAP_BASE_IDX 0 310 311 312// addressBlock: rcc_shadow_reg_shadowdec 313// base address: 0x0 314#define ixSHADOW_COMMAND 0x0004 // duplicate 315#define ixSHADOW_BASE_ADDR_1 0x0010 // duplicate 316#define ixSHADOW_BASE_ADDR_2 0x0014 // duplicate 317#define ixSHADOW_SUB_BUS_NUMBER_LATENCY 0x0018 // duplicate 318#define ixSHADOW_IO_BASE_LIMIT 0x001c // duplicate 319#define ixSHADOW_MEM_BASE_LIMIT 0x0020 // duplicate 320#define ixSHADOW_PREF_BASE_LIMIT 0x0024 // duplicate 321#define ixSHADOW_PREF_BASE_UPPER 0x0028 // duplicate 322#define ixSHADOW_PREF_LIMIT_UPPER 0x002c // duplicate 323#define ixSHADOW_IO_BASE_LIMIT_HI 0x0030 // duplicate 324#define ixSHADOW_IRQ_BRIDGE_CNTL 0x003e // duplicate 325#define ixSUC_INDEX 0x00e0 // duplicate 326#define ixSUC_DATA 0x00e4 // duplicate 327 328 329// addressBlock: bif_bx_pf_SUMDEC 330// base address: 0x0 331#define ixSUM_INDEX 0x00e0 // duplicate 332#define ixSUM_DATA 0x00e4 // duplicate 333 334 335// addressBlock: gdc_GDCDEC 336// base address: 0x1400000 337#define mmA2S_CNTL_CL0 0x4f0ab0 // duplicate 338#define mmA2S_CNTL_CL0_BASE_IDX 3 339#define mmA2S_CNTL_CL1 0x4f0ab1 // duplicate 340#define mmA2S_CNTL_CL1_BASE_IDX 3 341#define mmA2S_CNTL_CL2 0x4f0ab2 // duplicate 342#define mmA2S_CNTL_CL2_BASE_IDX 3 343#define mmA2S_CNTL_CL3 0x4f0ab3 // duplicate 344#define mmA2S_CNTL_CL3_BASE_IDX 3 345#define mmA2S_CNTL_CL4 0x4f0ab4 // duplicate 346#define mmA2S_CNTL_CL4_BASE_IDX 3 347#define mmA2S_CNTL_SW0 0x4f0ad0 // duplicate 348#define mmA2S_CNTL_SW0_BASE_IDX 3 349#define mmA2S_CNTL_SW1 0x4f0ad1 // duplicate 350#define mmA2S_CNTL_SW1_BASE_IDX 3 351#define mmA2S_CNTL_SW2 0x4f0ad2 // duplicate 352#define mmA2S_CNTL_SW2_BASE_IDX 3 353#define mmNGDC_MGCG_CTRL 0x4f0ae0 // duplicate 354#define mmNGDC_MGCG_CTRL_BASE_IDX 3 355#define mmA2S_MISC_CNTL 0x4f0ae1 // duplicate 356#define mmA2S_MISC_CNTL_BASE_IDX 3 357#define mmNGDC_SDP_PORT_CTRL 0x4f0ae2 // duplicate 358#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 3 359#define mmNGDC_RESERVED_0 0x4f0aeb // duplicate 360#define mmNGDC_RESERVED_0_BASE_IDX 3 361#define mmNGDC_RESERVED_1 0x4f0aec // duplicate 362#define mmNGDC_RESERVED_1_BASE_IDX 3 363#define mmBIF_SDMA0_DOORBELL_RANGE 0x4f0af0 // duplicate 364#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 3 365#define mmBIF_SDMA1_DOORBELL_RANGE 0x4f0af1 // duplicate 366#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 3 367#define mmBIF_IH_DOORBELL_RANGE 0x4f0af2 // duplicate 368#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 3 369#define mmBIF_MMSCH0_DOORBELL_RANGE 0x4f0af3 // duplicate 370#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 3 371#define mmBIF_DOORBELL_FENCE_CNTL 0x4f0afe // duplicate 372#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 3 373#define mmS2A_MISC_CNTL 0x4f0aff // duplicate 374#define mmS2A_MISC_CNTL_BASE_IDX 3 375#define mmA2S_CNTL2_SEC_CL0 0x4f0b00 // duplicate 376#define mmA2S_CNTL2_SEC_CL0_BASE_IDX 3 377#define mmA2S_CNTL2_SEC_CL1 0x4f0b01 // duplicate 378#define mmA2S_CNTL2_SEC_CL1_BASE_IDX 3 379#define mmA2S_CNTL2_SEC_CL2 0x4f0b02 // duplicate 380#define mmA2S_CNTL2_SEC_CL2_BASE_IDX 3 381#define mmA2S_CNTL2_SEC_CL3 0x4f0b03 // duplicate 382#define mmA2S_CNTL2_SEC_CL3_BASE_IDX 3 383#define mmA2S_CNTL2_SEC_CL4 0x4f0b04 // duplicate 384#define mmA2S_CNTL2_SEC_CL4_BASE_IDX 3 385 386 387// addressBlock: nbif_sion_SIONDEC 388// base address: 0x1400000 389#define ixSION_CL0_RdRsp_BurstTarget_REG0 0x1e000 390#define ixSION_CL0_RdRsp_BurstTarget_REG1 0x1e004 391#define ixSION_CL0_RdRsp_TimeSlot_REG0 0x1e008 392#define ixSION_CL0_RdRsp_TimeSlot_REG1 0x1e00c 393#define ixSION_CL0_WrRsp_BurstTarget_REG0 0x1e010 394#define ixSION_CL0_WrRsp_BurstTarget_REG1 0x1e014 395#define ixSION_CL0_WrRsp_TimeSlot_REG0 0x1e018 396#define ixSION_CL0_WrRsp_TimeSlot_REG1 0x1e01c 397#define ixSION_CL0_Req_BurstTarget_REG0 0x1e020 398#define ixSION_CL0_Req_BurstTarget_REG1 0x1e024 399#define ixSION_CL0_Req_TimeSlot_REG0 0x1e028 400#define ixSION_CL0_Req_TimeSlot_REG1 0x1e02c 401#define ixSION_CL0_ReqPoolCredit_Alloc_REG0 0x1e030 402#define ixSION_CL0_ReqPoolCredit_Alloc_REG1 0x1e034 403#define ixSION_CL0_DataPoolCredit_Alloc_REG0 0x1e038 404#define ixSION_CL0_DataPoolCredit_Alloc_REG1 0x1e03c 405#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0 0x1e040 406#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1 0x1e044 407#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0 0x1e048 408#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1 0x1e04c 409#define ixSION_CL1_RdRsp_BurstTarget_REG0 0x1e050 410#define ixSION_CL1_RdRsp_BurstTarget_REG1 0x1e054 411#define ixSION_CL1_RdRsp_TimeSlot_REG0 0x1e058 412#define ixSION_CL1_RdRsp_TimeSlot_REG1 0x1e05c 413#define ixSION_CL1_WrRsp_BurstTarget_REG0 0x1e060 414#define ixSION_CL1_WrRsp_BurstTarget_REG1 0x1e064 415#define ixSION_CL1_WrRsp_TimeSlot_REG0 0x1e068 416#define ixSION_CL1_WrRsp_TimeSlot_REG1 0x1e06c 417#define ixSION_CL1_Req_BurstTarget_REG0 0x1e070 418#define ixSION_CL1_Req_BurstTarget_REG1 0x1e074 419#define ixSION_CL1_Req_TimeSlot_REG0 0x1e078 420#define ixSION_CL1_Req_TimeSlot_REG1 0x1e07c 421#define ixSION_CL1_ReqPoolCredit_Alloc_REG0 0x1e080 422#define ixSION_CL1_ReqPoolCredit_Alloc_REG1 0x1e084 423#define ixSION_CL1_DataPoolCredit_Alloc_REG0 0x1e088 424#define ixSION_CL1_DataPoolCredit_Alloc_REG1 0x1e08c 425#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0 0x1e090 426#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1 0x1e094 427#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0 0x1e098 428#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1 0x1e09c 429#define ixSION_CL2_RdRsp_BurstTarget_REG0 0x1e0a0 430#define ixSION_CL2_RdRsp_BurstTarget_REG1 0x1e0a4 431#define ixSION_CL2_RdRsp_TimeSlot_REG0 0x1e0a8 432#define ixSION_CL2_RdRsp_TimeSlot_REG1 0x1e0ac 433#define ixSION_CL2_WrRsp_BurstTarget_REG0 0x1e0b0 434#define ixSION_CL2_WrRsp_BurstTarget_REG1 0x1e0b4 435#define ixSION_CL2_WrRsp_TimeSlot_REG0 0x1e0b8 436#define ixSION_CL2_WrRsp_TimeSlot_REG1 0x1e0bc 437#define ixSION_CL2_Req_BurstTarget_REG0 0x1e0c0 438#define ixSION_CL2_Req_BurstTarget_REG1 0x1e0c4 439#define ixSION_CL2_Req_TimeSlot_REG0 0x1e0c8 440#define ixSION_CL2_Req_TimeSlot_REG1 0x1e0cc 441#define ixSION_CL2_ReqPoolCredit_Alloc_REG0 0x1e0d0 442#define ixSION_CL2_ReqPoolCredit_Alloc_REG1 0x1e0d4 443#define ixSION_CL2_DataPoolCredit_Alloc_REG0 0x1e0d8 444#define ixSION_CL2_DataPoolCredit_Alloc_REG1 0x1e0dc 445#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0 0x1e0e0 446#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1 0x1e0e4 447#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0 0x1e0e8 448#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1 0x1e0ec 449#define ixSION_CL3_RdRsp_BurstTarget_REG0 0x1e0f0 450#define ixSION_CL3_RdRsp_BurstTarget_REG1 0x1e0f4 451#define ixSION_CL3_RdRsp_TimeSlot_REG0 0x1e0f8 452#define ixSION_CL3_RdRsp_TimeSlot_REG1 0x1e0fc 453#define ixSION_CL3_WrRsp_BurstTarget_REG0 0x1e100 454#define ixSION_CL3_WrRsp_BurstTarget_REG1 0x1e104 455#define ixSION_CL3_WrRsp_TimeSlot_REG0 0x1e108 456#define ixSION_CL3_WrRsp_TimeSlot_REG1 0x1e10c 457#define ixSION_CL3_Req_BurstTarget_REG0 0x1e110 458#define ixSION_CL3_Req_BurstTarget_REG1 0x1e114 459#define ixSION_CL3_Req_TimeSlot_REG0 0x1e118 460#define ixSION_CL3_Req_TimeSlot_REG1 0x1e11c 461#define ixSION_CL3_ReqPoolCredit_Alloc_REG0 0x1e120 462#define ixSION_CL3_ReqPoolCredit_Alloc_REG1 0x1e124 463#define ixSION_CL3_DataPoolCredit_Alloc_REG0 0x1e128 464#define ixSION_CL3_DataPoolCredit_Alloc_REG1 0x1e12c 465#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0 0x1e130 466#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1 0x1e134 467#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0 0x1e138 468#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1 0x1e13c 469#define ixSION_CL4_RdRsp_BurstTarget_REG0 0x1e140 470#define ixSION_CL4_RdRsp_BurstTarget_REG1 0x1e144 471#define ixSION_CL4_RdRsp_TimeSlot_REG0 0x1e148 472#define ixSION_CL4_RdRsp_TimeSlot_REG1 0x1e14c 473#define ixSION_CL4_WrRsp_BurstTarget_REG0 0x1e150 474#define ixSION_CL4_WrRsp_BurstTarget_REG1 0x1e154 475#define ixSION_CL4_WrRsp_TimeSlot_REG0 0x1e158 476#define ixSION_CL4_WrRsp_TimeSlot_REG1 0x1e15c 477#define ixSION_CL4_Req_BurstTarget_REG0 0x1e160 478#define ixSION_CL4_Req_BurstTarget_REG1 0x1e164 479#define ixSION_CL4_Req_TimeSlot_REG0 0x1e168 480#define ixSION_CL4_Req_TimeSlot_REG1 0x1e16c 481#define ixSION_CL4_ReqPoolCredit_Alloc_REG0 0x1e170 482#define ixSION_CL4_ReqPoolCredit_Alloc_REG1 0x1e174 483#define ixSION_CL4_DataPoolCredit_Alloc_REG0 0x1e178 484#define ixSION_CL4_DataPoolCredit_Alloc_REG1 0x1e17c 485#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0 0x1e180 486#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1 0x1e184 487#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0 0x1e188 488#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1 0x1e18c 489#define ixSION_CL5_RdRsp_BurstTarget_REG0 0x1e190 490#define ixSION_CL5_RdRsp_BurstTarget_REG1 0x1e194 491#define ixSION_CL5_RdRsp_TimeSlot_REG0 0x1e198 492#define ixSION_CL5_RdRsp_TimeSlot_REG1 0x1e19c 493#define ixSION_CL5_WrRsp_BurstTarget_REG0 0x1e1a0 494#define ixSION_CL5_WrRsp_BurstTarget_REG1 0x1e1a4 495#define ixSION_CL5_WrRsp_TimeSlot_REG0 0x1e1a8 496#define ixSION_CL5_WrRsp_TimeSlot_REG1 0x1e1ac 497#define ixSION_CL5_Req_BurstTarget_REG0 0x1e1b0 498#define ixSION_CL5_Req_BurstTarget_REG1 0x1e1b4 499#define ixSION_CL5_Req_TimeSlot_REG0 0x1e1b8 500#define ixSION_CL5_Req_TimeSlot_REG1 0x1e1bc 501#define ixSION_CL5_ReqPoolCredit_Alloc_REG0 0x1e1c0 502#define ixSION_CL5_ReqPoolCredit_Alloc_REG1 0x1e1c4 503#define ixSION_CL5_DataPoolCredit_Alloc_REG0 0x1e1c8 504#define ixSION_CL5_DataPoolCredit_Alloc_REG1 0x1e1cc 505#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0 0x1e1d0 506#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1 0x1e1d4 507#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0 0x1e1d8 508#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1 0x1e1dc 509#define ixSION_CNTL_REG0 0x1e1e0 510#define ixSION_CNTL_REG1 0x1e1e4 511 512 513// addressBlock: syshub_mmreg_direct_syshubdirect 514// base address: 0x1400000 515#define ixSYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate 516#define ixSYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate 517#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate 518#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate 519#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate 520#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate 521#define ixDMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate 522#define ixDMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate 523#define ixDMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate 524#define ixDMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate 525#define ixDMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate 526#define ixDMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate 527#define ixDMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate 528#define ixDMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate 529#define ixSYSHUB_CG_CNTL 0x10300 // duplicate 530#define ixSYSHUB_TRANS_IDLE 0x10308 // duplicate 531#define ixSYSHUB_HP_TIMER 0x1030c // duplicate 532#define ixSYSHUB_SCRATCH 0x10f00 // duplicate 533#define ixSYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate 534#define ixSYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate 535#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate 536#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate 537#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate 538#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate 539#define ixDMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate 540#define ixDMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate 541#define ixDMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate 542#define ixDMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate 543#define ixDMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate 544#define ixDMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate 545#define ixDMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate 546#define ixDMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate 547#define ixDMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate 548#define ixDMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate 549 550 551// addressBlock: gdc_ras_gdc_ras_regblk 552// base address: 0x1400000 553#define ixGDC_RAS_LEAF0_CTRL 0x1f800 554#define ixGDC_RAS_LEAF1_CTRL 0x1f804 555#define ixGDC_RAS_LEAF2_CTRL 0x1f808 556#define ixGDC_RAS_LEAF3_CTRL 0x1f80c 557#define ixGDC_RAS_LEAF4_CTRL 0x1f810 558#define ixGDC_RAS_LEAF5_CTRL 0x1f814 559 560 561// addressBlock: gdc_rst_GDCRST_DEC 562// base address: 0x1400000 563#define ixSHUB_PF_FLR_RST 0x1f000 564#define ixSHUB_GFX_DRV_MODE1_RST 0x1f004 565#define ixSHUB_LINK_RESET 0x1f008 566#define ixSHUB_PF0_VF_FLR_RST 0x1f020 567#define ixSHUB_HARD_RST_CTRL 0x1f040 568#define ixSHUB_SOFT_RST_CTRL 0x1f044 569#define ixSHUB_SDP_PORT_RST 0x1f048 570 571 572// memoryMap:EP0F0Reg 573 574 575// addressBlock: bif_bx_pf_SYSDEC 576// base address: 0x0 577#define mmSBIOS_SCRATCH_0 0x0048 // duplicate 578#define mmSBIOS_SCRATCH_0_BASE_IDX 0 579#define mmSBIOS_SCRATCH_1 0x0049 // duplicate 580#define mmSBIOS_SCRATCH_1_BASE_IDX 0 581#define mmSBIOS_SCRATCH_2 0x004a // duplicate 582#define mmSBIOS_SCRATCH_2_BASE_IDX 0 583#define mmSBIOS_SCRATCH_3 0x004b // duplicate 584#define mmSBIOS_SCRATCH_3_BASE_IDX 0 585#define mmBIOS_SCRATCH_0 0x004c // duplicate 586#define mmBIOS_SCRATCH_0_BASE_IDX 0 587#define mmBIOS_SCRATCH_1 0x004d // duplicate 588#define mmBIOS_SCRATCH_1_BASE_IDX 0 589#define mmBIOS_SCRATCH_2 0x004e // duplicate 590#define mmBIOS_SCRATCH_2_BASE_IDX 0 591#define mmBIOS_SCRATCH_3 0x004f // duplicate 592#define mmBIOS_SCRATCH_3_BASE_IDX 0 593#define mmBIOS_SCRATCH_4 0x0050 // duplicate 594#define mmBIOS_SCRATCH_4_BASE_IDX 0 595#define mmBIOS_SCRATCH_5 0x0051 // duplicate 596#define mmBIOS_SCRATCH_5_BASE_IDX 0 597#define mmBIOS_SCRATCH_6 0x0052 // duplicate 598#define mmBIOS_SCRATCH_6_BASE_IDX 0 599#define mmBIOS_SCRATCH_7 0x0053 // duplicate 600#define mmBIOS_SCRATCH_7_BASE_IDX 0 601#define mmBIOS_SCRATCH_8 0x0054 // duplicate 602#define mmBIOS_SCRATCH_8_BASE_IDX 0 603#define mmBIOS_SCRATCH_9 0x0055 // duplicate 604#define mmBIOS_SCRATCH_9_BASE_IDX 0 605#define mmBIOS_SCRATCH_10 0x0056 // duplicate 606#define mmBIOS_SCRATCH_10_BASE_IDX 0 607#define mmBIOS_SCRATCH_11 0x0057 // duplicate 608#define mmBIOS_SCRATCH_11_BASE_IDX 0 609#define mmBIOS_SCRATCH_12 0x0058 // duplicate 610#define mmBIOS_SCRATCH_12_BASE_IDX 0 611#define mmBIOS_SCRATCH_13 0x0059 // duplicate 612#define mmBIOS_SCRATCH_13_BASE_IDX 0 613#define mmBIOS_SCRATCH_14 0x005a // duplicate 614#define mmBIOS_SCRATCH_14_BASE_IDX 0 615#define mmBIOS_SCRATCH_15 0x005b // duplicate 616#define mmBIOS_SCRATCH_15_BASE_IDX 0 617#define mmBIF_RLC_INTR_CNTL 0x0060 // duplicate 618#define mmBIF_RLC_INTR_CNTL_BASE_IDX 0 619#define mmBIF_VCE_INTR_CNTL 0x0061 // duplicate 620#define mmBIF_VCE_INTR_CNTL_BASE_IDX 0 621#define mmBIF_UVD_INTR_CNTL 0x0062 // duplicate 622#define mmBIF_UVD_INTR_CNTL_BASE_IDX 0 623#define mmGFX_MMIOREG_CAM_ADDR0 0x0080 // duplicate 624#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 0 625#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 // duplicate 626#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 0 627#define mmGFX_MMIOREG_CAM_ADDR1 0x0082 // duplicate 628#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 0 629#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 // duplicate 630#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 0 631#define mmGFX_MMIOREG_CAM_ADDR2 0x0084 // duplicate 632#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 0 633#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 // duplicate 634#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 0 635#define mmGFX_MMIOREG_CAM_ADDR3 0x0086 // duplicate 636#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 0 637#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 // duplicate 638#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 0 639#define mmGFX_MMIOREG_CAM_ADDR4 0x0088 // duplicate 640#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 0 641#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 // duplicate 642#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 0 643#define mmGFX_MMIOREG_CAM_ADDR5 0x008a // duplicate 644#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 0 645#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x008b // duplicate 646#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 0 647#define mmGFX_MMIOREG_CAM_ADDR6 0x008c // duplicate 648#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 0 649#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x008d // duplicate 650#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 0 651#define mmGFX_MMIOREG_CAM_ADDR7 0x008e // duplicate 652#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 0 653#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x008f // duplicate 654#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 0 655#define mmGFX_MMIOREG_CAM_CNTL 0x0090 // duplicate 656#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 0 657#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x0091 // duplicate 658#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 0 659#define mmGFX_MMIOREG_CAM_ONE_CPL 0x0092 // duplicate 660#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 0 661#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 // duplicate 662#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 0 663 664 665// addressBlock: bif_bx_pf_SYSPFVFDEC 666// base address: 0x0 667#define mmMM_INDEX 0x0000 // duplicate 668#define mmMM_INDEX_BASE_IDX 0 669#define mmMM_DATA 0x0001 // duplicate 670#define mmMM_DATA_BASE_IDX 0 671#define mmMM_INDEX_HI 0x0006 // duplicate 672#define mmMM_INDEX_HI_BASE_IDX 0 673#define mmSYSHUB_INDEX_OVLP 0x0008 // duplicate 674#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 675#define mmSYSHUB_DATA_OVLP 0x0009 // duplicate 676#define mmSYSHUB_DATA_OVLP_BASE_IDX 0 677#define mmPCIE_INDEX 0x000c // duplicate 678#define mmPCIE_INDEX_BASE_IDX 0 679#define mmPCIE_DATA 0x000d // duplicate 680#define mmPCIE_DATA_BASE_IDX 0 681#define mmPCIE_INDEX2 0x000e // duplicate 682#define mmPCIE_INDEX2_BASE_IDX 0 683#define mmPCIE_DATA2 0x000f // duplicate 684#define mmPCIE_DATA2_BASE_IDX 0 685 686 687// addressBlock: rcc_dwn_BIFDEC1 688// base address: 0x0 689#define mmDN_PCIE_RESERVED 0x0d60 // duplicate 690#define mmDN_PCIE_RESERVED_BASE_IDX 0 691#define mmDN_PCIE_SCRATCH 0x0d61 // duplicate 692#define mmDN_PCIE_SCRATCH_BASE_IDX 0 693#define mmDN_PCIE_CNTL 0x0d63 // duplicate 694#define mmDN_PCIE_CNTL_BASE_IDX 0 695#define mmDN_PCIE_CONFIG_CNTL 0x0d64 // duplicate 696#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 0 697#define mmDN_PCIE_RX_CNTL2 0x0d65 // duplicate 698#define mmDN_PCIE_RX_CNTL2_BASE_IDX 0 699#define mmDN_PCIE_BUS_CNTL 0x0d66 // duplicate 700#define mmDN_PCIE_BUS_CNTL_BASE_IDX 0 701#define mmDN_PCIE_CFG_CNTL 0x0d67 // duplicate 702#define mmDN_PCIE_CFG_CNTL_BASE_IDX 0 703#define mmDN_PCIE_STRAP_F0 0x0d68 // duplicate 704#define mmDN_PCIE_STRAP_F0_BASE_IDX 0 705#define mmDN_PCIE_STRAP_MISC 0x0d69 // duplicate 706#define mmDN_PCIE_STRAP_MISC_BASE_IDX 0 707#define mmDN_PCIE_STRAP_MISC2 0x0d6a // duplicate 708#define mmDN_PCIE_STRAP_MISC2_BASE_IDX 0 709 710 711// addressBlock: rcc_dwnp_BIFDEC1 712// base address: 0x0 713#define mmPCIEP_RESERVED 0x0d6c // duplicate 714#define mmPCIEP_RESERVED_BASE_IDX 0 715#define mmPCIEP_SCRATCH 0x0d6d // duplicate 716#define mmPCIEP_SCRATCH_BASE_IDX 0 717#define mmPCIE_ERR_CNTL 0x0d6f // duplicate 718#define mmPCIE_ERR_CNTL_BASE_IDX 0 719#define mmPCIE_RX_CNTL 0x0d70 // duplicate 720#define mmPCIE_RX_CNTL_BASE_IDX 0 721#define mmPCIE_LC_SPEED_CNTL 0x0d71 // duplicate 722#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 0 723#define mmPCIE_LC_CNTL2 0x0d72 // duplicate 724#define mmPCIE_LC_CNTL2_BASE_IDX 0 725#define mmPCIEP_STRAP_MISC 0x0d73 // duplicate 726#define mmPCIEP_STRAP_MISC_BASE_IDX 0 727#define mmLTR_MSG_INFO_FROM_EP 0x0d74 // duplicate 728#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 0 729 730 731// addressBlock: rcc_ep_BIFDEC1 732// base address: 0x0 733#define mmEP_PCIE_SCRATCH 0x0d43 // duplicate 734#define mmEP_PCIE_SCRATCH_BASE_IDX 0 735#define mmEP_PCIE_CNTL 0x0d45 // duplicate 736#define mmEP_PCIE_CNTL_BASE_IDX 0 737#define mmEP_PCIE_INT_CNTL 0x0d46 // duplicate 738#define mmEP_PCIE_INT_CNTL_BASE_IDX 0 739#define mmEP_PCIE_INT_STATUS 0x0d47 // duplicate 740#define mmEP_PCIE_INT_STATUS_BASE_IDX 0 741#define mmEP_PCIE_RX_CNTL2 0x0d48 // duplicate 742#define mmEP_PCIE_RX_CNTL2_BASE_IDX 0 743#define mmEP_PCIE_BUS_CNTL 0x0d49 // duplicate 744#define mmEP_PCIE_BUS_CNTL_BASE_IDX 0 745#define mmEP_PCIE_CFG_CNTL 0x0d4a // duplicate 746#define mmEP_PCIE_CFG_CNTL_BASE_IDX 0 747#define mmEP_PCIE_OBFF_CNTL 0x0d4b // duplicate 748#define mmEP_PCIE_OBFF_CNTL_BASE_IDX 0 749#define mmEP_PCIE_TX_LTR_CNTL 0x0d4c // duplicate 750#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 0 751#define mmEP_PCIE_STRAP_MISC 0x0d4f // duplicate 752#define mmEP_PCIE_STRAP_MISC_BASE_IDX 0 753#define mmEP_PCIE_STRAP_MISC2 0x0d50 // duplicate 754#define mmEP_PCIE_STRAP_MISC2_BASE_IDX 0 755#define mmEP_PCIE_STRAP_PI 0x0d51 // duplicate 756#define mmEP_PCIE_STRAP_PI_BASE_IDX 0 757#define mmEP_PCIE_F0_DPA_CAP 0x0d52 // duplicate 758#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 0 759#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0d53 // duplicate 760#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 0 761#define mmEP_PCIE_F0_DPA_CNTL 0x0d53 // duplicate 762#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 0 763#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0d53 // duplicate 764#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 0 765#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0d54 // duplicate 766#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 0 767#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0d54 // duplicate 768#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 0 769#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0d54 // duplicate 770#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 0 771#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0d54 // duplicate 772#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 0 773#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0d55 // duplicate 774#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 0 775#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0d55 // duplicate 776#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 0 777#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0d55 // duplicate 778#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 0 779#define mmEP_PCIE_PME_CONTROL 0x0d55 // duplicate 780#define mmEP_PCIE_PME_CONTROL_BASE_IDX 0 781#define mmEP_PCIEP_RESERVED 0x0d56 // duplicate 782#define mmEP_PCIEP_RESERVED_BASE_IDX 0 783#define mmEP_PCIE_TX_CNTL 0x0d58 // duplicate 784#define mmEP_PCIE_TX_CNTL_BASE_IDX 0 785#define mmEP_PCIE_TX_REQUESTER_ID 0x0d59 // duplicate 786#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 0 787#define mmEP_PCIE_ERR_CNTL 0x0d5a // duplicate 788#define mmEP_PCIE_ERR_CNTL_BASE_IDX 0 789#define mmEP_PCIE_RX_CNTL 0x0d5b // duplicate 790#define mmEP_PCIE_RX_CNTL_BASE_IDX 0 791#define mmEP_PCIE_LC_SPEED_CNTL 0x0d5c // duplicate 792#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 0 793 794 795// addressBlock: bif_bx_pf_BIFDEC1 796// base address: 0x0 797#define mmBIF_MM_INDACCESS_CNTL 0x0e06 // duplicate 798#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 0 799#define mmBUS_CNTL 0x0e07 // duplicate 800#define mmBUS_CNTL_BASE_IDX 0 801#define mmBIF_SCRATCH0 0x0e08 // duplicate 802#define mmBIF_SCRATCH0_BASE_IDX 0 803#define mmBIF_SCRATCH1 0x0e09 // duplicate 804#define mmBIF_SCRATCH1_BASE_IDX 0 805#define mmBX_RESET_EN 0x0e0d // duplicate 806#define mmBX_RESET_EN_BASE_IDX 0 807#define mmMM_CFGREGS_CNTL 0x0e0e // duplicate 808#define mmMM_CFGREGS_CNTL_BASE_IDX 0 809#define mmBX_RESET_CNTL 0x0e10 // duplicate 810#define mmBX_RESET_CNTL_BASE_IDX 0 811#define mmINTERRUPT_CNTL 0x0e11 // duplicate 812#define mmINTERRUPT_CNTL_BASE_IDX 0 813#define mmINTERRUPT_CNTL2 0x0e12 // duplicate 814#define mmINTERRUPT_CNTL2_BASE_IDX 0 815#define mmCLKREQB_PAD_CNTL 0x0e18 // duplicate 816#define mmCLKREQB_PAD_CNTL_BASE_IDX 0 817#define mmCLKREQB_PERF_COUNTER 0x0e19 // duplicate 818#define mmCLKREQB_PERF_COUNTER_BASE_IDX 0 819#define mmBIF_CLK_CTRL 0x0e1a // duplicate 820#define mmBIF_CLK_CTRL_BASE_IDX 0 821#define mmBIF_FEATURES_CONTROL_MISC 0x0e1b // duplicate 822#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 0 823#define mmBIF_DOORBELL_CNTL 0x0e1c // duplicate 824#define mmBIF_DOORBELL_CNTL_BASE_IDX 0 825#define mmBIF_DOORBELL_INT_CNTL 0x0e1d // duplicate 826#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 0 827#define mmBIF_SLVARB_MODE 0x0e1e // duplicate 828#define mmBIF_SLVARB_MODE_BASE_IDX 0 829#define mmBIF_FB_EN 0x0e1f // duplicate 830#define mmBIF_FB_EN_BASE_IDX 0 831#define mmBIF_BUSY_DELAY_CNTR 0x0e20 // duplicate 832#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 0 833#define mmBIF_PERFMON_CNTL 0x0e21 // duplicate 834#define mmBIF_PERFMON_CNTL_BASE_IDX 0 835#define mmBIF_PERFCOUNTER0_RESULT 0x0e22 // duplicate 836#define mmBIF_PERFCOUNTER0_RESULT_BASE_IDX 0 837#define mmBIF_PERFCOUNTER1_RESULT 0x0e23 // duplicate 838#define mmBIF_PERFCOUNTER1_RESULT_BASE_IDX 0 839#define mmBIF_MST_TRANS_PENDING_VF 0x0e29 // duplicate 840#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 0 841#define mmBIF_SLV_TRANS_PENDING_VF 0x0e2a // duplicate 842#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 0 843#define mmBACO_CNTL 0x0e2b // duplicate 844#define mmBACO_CNTL_BASE_IDX 0 845#define mmBIF_BACO_EXIT_TIME0 0x0e2c // duplicate 846#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 0 847#define mmBIF_BACO_EXIT_TIMER1 0x0e2d // duplicate 848#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 0 849#define mmBIF_BACO_EXIT_TIMER2 0x0e2e // duplicate 850#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 0 851#define mmBIF_BACO_EXIT_TIMER3 0x0e2f // duplicate 852#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 0 853#define mmBIF_BACO_EXIT_TIMER4 0x0e30 // duplicate 854#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 0 855#define mmMEM_TYPE_CNTL 0x0e31 // duplicate 856#define mmMEM_TYPE_CNTL_BASE_IDX 0 857#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0e33 // duplicate 858#define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 0 859#define mmBIF_VDDGFX_GFX0_LOWER 0x0e34 // duplicate 860#define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 0 861#define mmBIF_VDDGFX_GFX0_UPPER 0x0e35 // duplicate 862#define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 0 863#define mmBIF_VDDGFX_GFX1_LOWER 0x0e36 // duplicate 864#define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 0 865#define mmBIF_VDDGFX_GFX1_UPPER 0x0e37 // duplicate 866#define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 0 867#define mmBIF_VDDGFX_GFX2_LOWER 0x0e38 // duplicate 868#define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 0 869#define mmBIF_VDDGFX_GFX2_UPPER 0x0e39 // duplicate 870#define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 0 871#define mmBIF_VDDGFX_GFX3_LOWER 0x0e3a // duplicate 872#define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 0 873#define mmBIF_VDDGFX_GFX3_UPPER 0x0e3b // duplicate 874#define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 0 875#define mmBIF_VDDGFX_GFX4_LOWER 0x0e3c // duplicate 876#define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 0 877#define mmBIF_VDDGFX_GFX4_UPPER 0x0e3d // duplicate 878#define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 0 879#define mmBIF_VDDGFX_GFX5_LOWER 0x0e3e // duplicate 880#define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 0 881#define mmBIF_VDDGFX_GFX5_UPPER 0x0e3f // duplicate 882#define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 0 883#define mmBIF_VDDGFX_RSV1_LOWER 0x0e40 // duplicate 884#define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 0 885#define mmBIF_VDDGFX_RSV1_UPPER 0x0e41 // duplicate 886#define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 0 887#define mmBIF_VDDGFX_RSV2_LOWER 0x0e42 // duplicate 888#define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 0 889#define mmBIF_VDDGFX_RSV2_UPPER 0x0e43 // duplicate 890#define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 0 891#define mmBIF_VDDGFX_RSV3_LOWER 0x0e44 // duplicate 892#define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 0 893#define mmBIF_VDDGFX_RSV3_UPPER 0x0e45 // duplicate 894#define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 0 895#define mmBIF_VDDGFX_RSV4_LOWER 0x0e46 // duplicate 896#define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 0 897#define mmBIF_VDDGFX_RSV4_UPPER 0x0e47 // duplicate 898#define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 0 899#define mmBIF_VDDGFX_FB_CMP 0x0e48 // duplicate 900#define mmBIF_VDDGFX_FB_CMP_BASE_IDX 0 901#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0e49 // duplicate 902#define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 0 903#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x0e4a // duplicate 904#define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 0 905#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x0e4b // duplicate 906#define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 0 907#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x0e4c // duplicate 908#define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 0 909#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x0e4d // duplicate 910#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 0 911#define mmREMAP_HDP_REG_FLUSH_CNTL 0x0e4e // duplicate 912#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 0 913#define mmBIF_RB_CNTL 0x0e4f // duplicate 914#define mmBIF_RB_CNTL_BASE_IDX 0 915#define mmBIF_RB_BASE 0x0e50 // duplicate 916#define mmBIF_RB_BASE_BASE_IDX 0 917#define mmBIF_RB_RPTR 0x0e51 // duplicate 918#define mmBIF_RB_RPTR_BASE_IDX 0 919#define mmBIF_RB_WPTR 0x0e52 // duplicate 920#define mmBIF_RB_WPTR_BASE_IDX 0 921#define mmBIF_RB_WPTR_ADDR_HI 0x0e53 // duplicate 922#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 0 923#define mmBIF_RB_WPTR_ADDR_LO 0x0e54 // duplicate 924#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 0 925#define mmMAILBOX_INDEX 0x0e55 // duplicate 926#define mmMAILBOX_INDEX_BASE_IDX 0 927#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x0e62 // duplicate 928#define mmBIF_GPUIOV_RESET_NOTIFICATION_BASE_IDX 0 929#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0e63 // duplicate 930#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 0 931#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0e64 // duplicate 932#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 0 933#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0e65 // duplicate 934#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 0 935#define mmBIF_GMI_WRR_WEIGHT 0x0e66 // duplicate 936#define mmBIF_GMI_WRR_WEIGHT_BASE_IDX 0 937#define mmNBIF_STRAP_WRITE_CTRL 0x0e67 // duplicate 938#define mmNBIF_STRAP_WRITE_CTRL_BASE_IDX 0 939#define mmBIF_PERSTB_PAD_CNTL 0x0e68 // duplicate 940#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 0 941#define mmBIF_PX_EN_PAD_CNTL 0x0e69 // duplicate 942#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 0 943#define mmBIF_REFPADKIN_PAD_CNTL 0x0e6a // duplicate 944#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 0 945#define mmBIF_CLKREQB_PAD_CNTL 0x0e6b // duplicate 946#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 0 947 948 949// addressBlock: rcc_pf_0_BIFDEC1 950// base address: 0x0 951#define mmRCC_BACO_CNTL_MISC 0x0da7 // duplicate 952#define mmRCC_BACO_CNTL_MISC_BASE_IDX 0 953#define mmRCC_RESET_EN 0x0da8 // duplicate 954#define mmRCC_RESET_EN_BASE_IDX 0 955#define mmRCC_VDM_SUPPORT 0x0da9 // duplicate 956#define mmRCC_VDM_SUPPORT_BASE_IDX 0 957#define mmRCC_PEER_REG_RANGE0 0x0dde // duplicate 958#define mmRCC_PEER_REG_RANGE0_BASE_IDX 0 959#define mmRCC_PEER_REG_RANGE1 0x0ddf // duplicate 960#define mmRCC_PEER_REG_RANGE1_BASE_IDX 0 961#define mmRCC_BUS_CNTL 0x0de1 // duplicate 962#define mmRCC_BUS_CNTL_BASE_IDX 0 963#define mmRCC_CONFIG_CNTL 0x0de2 // duplicate 964#define mmRCC_CONFIG_CNTL_BASE_IDX 0 965#define mmRCC_CONFIG_F0_BASE 0x0de6 // duplicate 966#define mmRCC_CONFIG_F0_BASE_BASE_IDX 0 967#define mmRCC_CONFIG_APER_SIZE 0x0de7 // duplicate 968#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 0 969#define mmRCC_CONFIG_REG_APER_SIZE 0x0de8 // duplicate 970#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 0 971#define mmRCC_XDMA_LO 0x0de9 // duplicate 972#define mmRCC_XDMA_LO_BASE_IDX 0 973#define mmRCC_XDMA_HI 0x0dea // duplicate 974#define mmRCC_XDMA_HI_BASE_IDX 0 975#define mmRCC_FEATURES_CONTROL_MISC 0x0deb // duplicate 976#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 0 977#define mmRCC_BUSNUM_CNTL1 0x0dec // duplicate 978#define mmRCC_BUSNUM_CNTL1_BASE_IDX 0 979#define mmRCC_BUSNUM_LIST0 0x0ded // duplicate 980#define mmRCC_BUSNUM_LIST0_BASE_IDX 0 981#define mmRCC_BUSNUM_LIST1 0x0dee // duplicate 982#define mmRCC_BUSNUM_LIST1_BASE_IDX 0 983#define mmRCC_BUSNUM_CNTL2 0x0def // duplicate 984#define mmRCC_BUSNUM_CNTL2_BASE_IDX 0 985#define mmRCC_CAPTURE_HOST_BUSNUM 0x0df0 // duplicate 986#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 0 987#define mmRCC_HOST_BUSNUM 0x0df1 // duplicate 988#define mmRCC_HOST_BUSNUM_BASE_IDX 0 989#define mmRCC_PEER0_FB_OFFSET_HI 0x0df2 // duplicate 990#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 0 991#define mmRCC_PEER0_FB_OFFSET_LO 0x0df3 // duplicate 992#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 0 993#define mmRCC_PEER1_FB_OFFSET_HI 0x0df4 // duplicate 994#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 0 995#define mmRCC_PEER1_FB_OFFSET_LO 0x0df5 // duplicate 996#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 0 997#define mmRCC_PEER2_FB_OFFSET_HI 0x0df6 // duplicate 998#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 0 999#define mmRCC_PEER2_FB_OFFSET_LO 0x0df7 // duplicate 1000#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 0
1001#define mmRCC_PEER3_FB_OFFSET_HI 0x0df8 // duplicate 1002#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 0 1003#define mmRCC_PEER3_FB_OFFSET_LO 0x0df9 // duplicate 1004#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 0 1005#define mmRCC_DEVFUNCNUM_LIST0 0x0dfa // duplicate 1006#define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 0 1007#define mmRCC_DEVFUNCNUM_LIST1 0x0dfb // duplicate 1008#define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 0 1009#define mmRCC_DEV0_LINK_CNTL 0x0dfd // duplicate 1010#define mmRCC_DEV0_LINK_CNTL_BASE_IDX 0 1011#define mmRCC_CMN_LINK_CNTL 0x0dfe // duplicate 1012#define mmRCC_CMN_LINK_CNTL_BASE_IDX 0 1013#define mmRCC_EP_REQUESTERID_RESTORE 0x0dff // duplicate 1014#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 0 1015#define mmRCC_LTR_LSWITCH_CNTL 0x0e00 // duplicate 1016#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 0 1017#define mmRCC_MH_ARB_CNTL 0x0e01 // duplicate 1018#define mmRCC_MH_ARB_CNTL_BASE_IDX 0 1019 1020 1021// addressBlock: rcc_pf_0_BIFDEC2 1022// base address: 0x0 1023#define mmGFXMSIX_VECT0_ADDR_LO 0x10800 // duplicate 1024#define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 0 1025#define mmGFXMSIX_VECT0_ADDR_HI 0x10801 // duplicate 1026#define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 0 1027#define mmGFXMSIX_VECT0_MSG_DATA 0x10802 // duplicate 1028#define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 0 1029#define mmGFXMSIX_VECT0_CONTROL 0x10803 // duplicate 1030#define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 0 1031#define mmGFXMSIX_VECT1_ADDR_LO 0x10804 // duplicate 1032#define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 0 1033#define mmGFXMSIX_VECT1_ADDR_HI 0x10805 // duplicate 1034#define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 0 1035#define mmGFXMSIX_VECT1_MSG_DATA 0x10806 // duplicate 1036#define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 0 1037#define mmGFXMSIX_VECT1_CONTROL 0x10807 // duplicate 1038#define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 0 1039#define mmGFXMSIX_VECT2_ADDR_LO 0x10808 // duplicate 1040#define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 0 1041#define mmGFXMSIX_VECT2_ADDR_HI 0x10809 // duplicate 1042#define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 0 1043#define mmGFXMSIX_VECT2_MSG_DATA 0x1080a // duplicate 1044#define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 0 1045#define mmGFXMSIX_VECT2_CONTROL 0x1080b // duplicate 1046#define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 0 1047#define mmGFXMSIX_PBA 0x10c00 // duplicate 1048#define mmGFXMSIX_PBA_BASE_IDX 0 1049 1050 1051// addressBlock: rcc_strap_BIFDEC1 1052// base address: 0x0 1053#define mmRCC_DEV0_PORT_STRAP0 0x0d27 // duplicate 1054#define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 0 1055#define mmRCC_DEV0_PORT_STRAP1 0x0d28 // duplicate 1056#define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 0 1057#define mmRCC_DEV0_PORT_STRAP2 0x0d29 // duplicate 1058#define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 0 1059#define mmRCC_DEV0_PORT_STRAP3 0x0d2a // duplicate 1060#define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 0 1061#define mmRCC_DEV0_PORT_STRAP4 0x0d2b // duplicate 1062#define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 0 1063#define mmRCC_DEV0_PORT_STRAP5 0x0d2c // duplicate 1064#define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 0 1065#define mmRCC_DEV0_PORT_STRAP6 0x0d2d // duplicate 1066#define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 0 1067#define mmRCC_DEV0_PORT_STRAP7 0x0d2e // duplicate 1068#define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 0 1069#define mmRCC_DEV0_EPF0_STRAP0 0x0d2f // duplicate 1070#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 0 1071#define mmRCC_DEV0_EPF0_STRAP1 0x0d30 // duplicate 1072#define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 0 1073#define mmRCC_DEV0_EPF0_STRAP13 0x0d31 // duplicate 1074#define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 0 1075#define mmRCC_DEV0_EPF0_STRAP2 0x0d32 // duplicate 1076#define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 0 1077#define mmRCC_DEV0_EPF0_STRAP3 0x0d33 // duplicate 1078#define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 0 1079#define mmRCC_DEV0_EPF0_STRAP4 0x0d34 // duplicate 1080#define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 0 1081#define mmRCC_DEV0_EPF0_STRAP5 0x0d35 // duplicate 1082#define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 0 1083#define mmRCC_DEV0_EPF0_STRAP8 0x0d36 // duplicate 1084#define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 0 1085#define mmRCC_DEV0_EPF0_STRAP9 0x0d37 // duplicate 1086#define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 0 1087#define mmRCC_DEV0_EPF1_STRAP0 0x0d38 // duplicate 1088#define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 0 1089#define mmRCC_DEV0_EPF1_STRAP10 0x0d39 // duplicate 1090#define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 0 1091#define mmRCC_DEV0_EPF1_STRAP11 0x0d3a // duplicate 1092#define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 0 1093#define mmRCC_DEV0_EPF1_STRAP12 0x0d3b // duplicate 1094#define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 0 1095#define mmRCC_DEV0_EPF1_STRAP13 0x0d3c // duplicate 1096#define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 0 1097#define mmRCC_DEV0_EPF1_STRAP2 0x0d3d // duplicate 1098#define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 0 1099#define mmRCC_DEV0_EPF1_STRAP3 0x0d3e // duplicate 1100#define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 0 1101#define mmRCC_DEV0_EPF1_STRAP4 0x0d3f // duplicate 1102#define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 0 1103#define mmRCC_DEV0_EPF1_STRAP5 0x0d40 // duplicate 1104#define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 0 1105#define mmRCC_DEV0_EPF1_STRAP6 0x0d41 // duplicate 1106#define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 0 1107#define mmRCC_DEV0_EPF1_STRAP7 0x0d42 // duplicate 1108#define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 0 1109 1110 1111// addressBlock: bif_bx_pf_BIFPFVFDEC1 1112// base address: 0x0 1113#define mmBIF_BME_STATUS 0x0e0b // duplicate 1114#define mmBIF_BME_STATUS_BASE_IDX 0 1115#define mmBIF_ATOMIC_ERR_LOG 0x0e0c // duplicate 1116#define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 0 1117#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0e13 // duplicate 1118#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 0 1119#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0e14 // duplicate 1120#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 0 1121#define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x0e15 // duplicate 1122#define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 0 1123#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x0e16 // duplicate 1124#define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 0 1125#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x0e17 // duplicate 1126#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 0 1127#define mmGPU_HDP_FLUSH_REQ 0x0e26 // duplicate 1128#define mmGPU_HDP_FLUSH_REQ_BASE_IDX 0 1129#define mmGPU_HDP_FLUSH_DONE 0x0e27 // duplicate 1130#define mmGPU_HDP_FLUSH_DONE_BASE_IDX 0 1131#define mmBIF_TRANS_PENDING 0x0e28 // duplicate 1132#define mmBIF_TRANS_PENDING_BASE_IDX 0 1133#define mmMAILBOX_MSGBUF_TRN_DW0 0x0e56 // duplicate 1134#define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 0 1135#define mmMAILBOX_MSGBUF_TRN_DW1 0x0e57 // duplicate 1136#define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 0 1137#define mmMAILBOX_MSGBUF_TRN_DW2 0x0e58 // duplicate 1138#define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 0 1139#define mmMAILBOX_MSGBUF_TRN_DW3 0x0e59 // duplicate 1140#define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 0 1141#define mmMAILBOX_MSGBUF_RCV_DW0 0x0e5a // duplicate 1142#define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 0 1143#define mmMAILBOX_MSGBUF_RCV_DW1 0x0e5b // duplicate 1144#define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 0 1145#define mmMAILBOX_MSGBUF_RCV_DW2 0x0e5c // duplicate 1146#define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 0 1147#define mmMAILBOX_MSGBUF_RCV_DW3 0x0e5d // duplicate 1148#define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 0 1149#define mmMAILBOX_CONTROL 0x0e5e // duplicate 1150#define mmMAILBOX_CONTROL_BASE_IDX 0 1151#define mmMAILBOX_INT_CNTL 0x0e5f // duplicate 1152#define mmMAILBOX_INT_CNTL_BASE_IDX 0 1153#define mmBIF_VMHV_MAILBOX 0x0e60 // duplicate 1154#define mmBIF_VMHV_MAILBOX_BASE_IDX 0 1155 1156 1157// addressBlock: rcc_pf_0_BIFPFVFDEC1 1158// base address: 0x0 1159#define mmRCC_DOORBELL_APER_EN 0x0de0 // duplicate 1160#define mmRCC_DOORBELL_APER_EN_BASE_IDX 0 1161#define mmRCC_CONFIG_MEMSIZE 0x0de3 // duplicate 1162#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 0 1163#define mmRCC_CONFIG_RESERVED 0x0de4 // duplicate 1164#define mmRCC_CONFIG_RESERVED_BASE_IDX 0 1165#define mmRCC_IOV_FUNC_IDENTIFIER 0x0de5 // duplicate 1166#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 0 1167 1168 1169// addressBlock: syshub_mmreg_ind_syshubdec 1170// base address: 0x0 1171#define mmSYSHUB_INDEX 0x0008 1172#define mmSYSHUB_INDEX_BASE_IDX 0 1173#define mmSYSHUB_DATA 0x0009 1174#define mmSYSHUB_DATA_BASE_IDX 0 1175 1176 1177// addressBlock: rcc_strap_rcc_strap_internal 1178// base address: 0x10100000 1179#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 0x403c000 // duplicate 1180#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_BASE_IDX 3 1181#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 0x403c001 // duplicate 1182#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_BASE_IDX 3 1183#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 0x403c002 // duplicate 1184#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_BASE_IDX 3 1185#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 0x403c003 // duplicate 1186#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_BASE_IDX 3 1187#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 0x403c004 // duplicate 1188#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_BASE_IDX 3 1189#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 0x403c005 // duplicate 1190#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_BASE_IDX 3 1191#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 0x403c006 // duplicate 1192#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_BASE_IDX 3 1193#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 0x403c007 // duplicate 1194#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_BASE_IDX 3 1195#define mmRCC_DEV1_PORT_STRAP0 0x403c080 1196#define mmRCC_DEV1_PORT_STRAP0_BASE_IDX 3 1197#define mmRCC_DEV1_PORT_STRAP1 0x403c081 1198#define mmRCC_DEV1_PORT_STRAP1_BASE_IDX 3 1199#define mmRCC_DEV1_PORT_STRAP2 0x403c082 1200#define mmRCC_DEV1_PORT_STRAP2_BASE_IDX 3 1201#define mmRCC_DEV1_PORT_STRAP3 0x403c083 1202#define mmRCC_DEV1_PORT_STRAP3_BASE_IDX 3 1203#define mmRCC_DEV1_PORT_STRAP4 0x403c084 1204#define mmRCC_DEV1_PORT_STRAP4_BASE_IDX 3 1205#define mmRCC_DEV1_PORT_STRAP5 0x403c085 1206#define mmRCC_DEV1_PORT_STRAP5_BASE_IDX 3 1207#define mmRCC_DEV1_PORT_STRAP6 0x403c086 1208#define mmRCC_DEV1_PORT_STRAP6_BASE_IDX 3 1209#define mmRCC_DEV1_PORT_STRAP7 0x403c087 1210#define mmRCC_DEV1_PORT_STRAP7_BASE_IDX 3 1211#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 0x403cc00 // duplicate 1212#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_BASE_IDX 3 1213#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 0x403cc01 // duplicate 1214#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_BASE_IDX 3 1215#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 0x403cc02 // duplicate 1216#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_BASE_IDX 3 1217#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 0x403cc03 // duplicate 1218#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_BASE_IDX 3 1219#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 0x403cc04 // duplicate 1220#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_BASE_IDX 3 1221#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 0x403cc05 // duplicate 1222#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_BASE_IDX 3 1223#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 0x403cc08 // duplicate 1224#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_BASE_IDX 3 1225#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 0x403cc09 // duplicate 1226#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_BASE_IDX 3 1227#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 0x403cc0d // duplicate 1228#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_BASE_IDX 3 1229#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 0x403cc80 // duplicate 1230#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_BASE_IDX 3 1231#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 0x403cc82 // duplicate 1232#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_BASE_IDX 3 1233#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 0x403cc83 // duplicate 1234#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_BASE_IDX 3 1235#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 0x403cc84 // duplicate 1236#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_BASE_IDX 3 1237#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 0x403cc85 // duplicate 1238#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_BASE_IDX 3 1239#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 0x403cc86 // duplicate 1240#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_BASE_IDX 3 1241#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 0x403cc87 // duplicate 1242#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_BASE_IDX 3 1243#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 0x403cc8a // duplicate 1244#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_BASE_IDX 3 1245#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 0x403cc8b // duplicate 1246#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_BASE_IDX 3 1247#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 0x403cc8c // duplicate 1248#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_BASE_IDX 3 1249#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 0x403cc8d // duplicate 1250#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_BASE_IDX 3 1251#define mmRCC_DEV0_EPF2_STRAP0 0x403cd00 1252#define mmRCC_DEV0_EPF2_STRAP0_BASE_IDX 3 1253#define mmRCC_DEV0_EPF2_STRAP2 0x403cd02 1254#define mmRCC_DEV0_EPF2_STRAP2_BASE_IDX 3 1255#define mmRCC_DEV0_EPF2_STRAP3 0x403cd03 1256#define mmRCC_DEV0_EPF2_STRAP3_BASE_IDX 3 1257#define mmRCC_DEV0_EPF2_STRAP4 0x403cd04 1258#define mmRCC_DEV0_EPF2_STRAP4_BASE_IDX 3 1259#define mmRCC_DEV0_EPF2_STRAP5 0x403cd05 1260#define mmRCC_DEV0_EPF2_STRAP5_BASE_IDX 3 1261#define mmRCC_DEV0_EPF2_STRAP6 0x403cd06 1262#define mmRCC_DEV0_EPF2_STRAP6_BASE_IDX 3 1263#define mmRCC_DEV0_EPF2_STRAP13 0x403cd0d 1264#define mmRCC_DEV0_EPF2_STRAP13_BASE_IDX 3 1265#define mmRCC_DEV0_EPF3_STRAP0 0x403cd80 1266#define mmRCC_DEV0_EPF3_STRAP0_BASE_IDX 3 1267#define mmRCC_DEV0_EPF3_STRAP2 0x403cd82 1268#define mmRCC_DEV0_EPF3_STRAP2_BASE_IDX 3 1269#define mmRCC_DEV0_EPF3_STRAP3 0x403cd83 1270#define mmRCC_DEV0_EPF3_STRAP3_BASE_IDX 3 1271#define mmRCC_DEV0_EPF3_STRAP4 0x403cd84 1272#define mmRCC_DEV0_EPF3_STRAP4_BASE_IDX 3 1273#define mmRCC_DEV0_EPF3_STRAP5 0x403cd85 1274#define mmRCC_DEV0_EPF3_STRAP5_BASE_IDX 3 1275#define mmRCC_DEV0_EPF3_STRAP6 0x403cd86 1276#define mmRCC_DEV0_EPF3_STRAP6_BASE_IDX 3 1277#define mmRCC_DEV0_EPF3_STRAP13 0x403cd8d 1278#define mmRCC_DEV0_EPF3_STRAP13_BASE_IDX 3 1279#define mmRCC_DEV0_EPF4_STRAP0 0x403ce00 1280#define mmRCC_DEV0_EPF4_STRAP0_BASE_IDX 3 1281#define mmRCC_DEV0_EPF4_STRAP2 0x403ce02 1282#define mmRCC_DEV0_EPF4_STRAP2_BASE_IDX 3 1283#define mmRCC_DEV0_EPF4_STRAP3 0x403ce03 1284#define mmRCC_DEV0_EPF4_STRAP3_BASE_IDX 3 1285#define mmRCC_DEV0_EPF4_STRAP4 0x403ce04 1286#define mmRCC_DEV0_EPF4_STRAP4_BASE_IDX 3 1287#define mmRCC_DEV0_EPF4_STRAP5 0x403ce05 1288#define mmRCC_DEV0_EPF4_STRAP5_BASE_IDX 3 1289#define mmRCC_DEV0_EPF4_STRAP6 0x403ce06 1290#define mmRCC_DEV0_EPF4_STRAP6_BASE_IDX 3 1291#define mmRCC_DEV0_EPF4_STRAP13 0x403ce0d 1292#define mmRCC_DEV0_EPF4_STRAP13_BASE_IDX 3 1293#define mmRCC_DEV0_EPF5_STRAP0 0x403ce80 1294#define mmRCC_DEV0_EPF5_STRAP0_BASE_IDX 3 1295#define mmRCC_DEV0_EPF5_STRAP2 0x403ce82 1296#define mmRCC_DEV0_EPF5_STRAP2_BASE_IDX 3 1297#define mmRCC_DEV0_EPF5_STRAP3 0x403ce83 1298#define mmRCC_DEV0_EPF5_STRAP3_BASE_IDX 3 1299#define mmRCC_DEV0_EPF5_STRAP4 0x403ce84 1300#define mmRCC_DEV0_EPF5_STRAP4_BASE_IDX 3 1301#define mmRCC_DEV0_EPF5_STRAP5 0x403ce85 1302#define mmRCC_DEV0_EPF5_STRAP5_BASE_IDX 3 1303#define mmRCC_DEV0_EPF5_STRAP6 0x403ce86 1304#define mmRCC_DEV0_EPF5_STRAP6_BASE_IDX 3 1305#define mmRCC_DEV0_EPF5_STRAP13 0x403ce8d 1306#define mmRCC_DEV0_EPF5_STRAP13_BASE_IDX 3 1307#define mmRCC_DEV0_EPF6_STRAP0 0x403cf00 1308#define mmRCC_DEV0_EPF6_STRAP0_BASE_IDX 3 1309#define mmRCC_DEV0_EPF6_STRAP2 0x403cf02 1310#define mmRCC_DEV0_EPF6_STRAP2_BASE_IDX 3 1311#define mmRCC_DEV0_EPF6_STRAP3 0x403cf03 1312#define mmRCC_DEV0_EPF6_STRAP3_BASE_IDX 3 1313#define mmRCC_DEV0_EPF6_STRAP4 0x403cf04 1314#define mmRCC_DEV0_EPF6_STRAP4_BASE_IDX 3 1315#define mmRCC_DEV0_EPF6_STRAP5 0x403cf05 1316#define mmRCC_DEV0_EPF6_STRAP5_BASE_IDX 3 1317#define mmRCC_DEV0_EPF6_STRAP6 0x403cf06 1318#define mmRCC_DEV0_EPF6_STRAP6_BASE_IDX 3 1319#define mmRCC_DEV0_EPF6_STRAP13 0x403cf0d 1320#define mmRCC_DEV0_EPF6_STRAP13_BASE_IDX 3 1321#define mmRCC_DEV0_EPF7_STRAP0 0x403cf80 1322#define mmRCC_DEV0_EPF7_STRAP0_BASE_IDX 3 1323#define mmRCC_DEV0_EPF7_STRAP2 0x403cf82 1324#define mmRCC_DEV0_EPF7_STRAP2_BASE_IDX 3 1325#define mmRCC_DEV0_EPF7_STRAP3 0x403cf83 1326#define mmRCC_DEV0_EPF7_STRAP3_BASE_IDX 3 1327#define mmRCC_DEV0_EPF7_STRAP4 0x403cf84 1328#define mmRCC_DEV0_EPF7_STRAP4_BASE_IDX 3 1329#define mmRCC_DEV0_EPF7_STRAP5 0x403cf85 1330#define mmRCC_DEV0_EPF7_STRAP5_BASE_IDX 3 1331#define mmRCC_DEV0_EPF7_STRAP6 0x403cf86 1332#define mmRCC_DEV0_EPF7_STRAP6_BASE_IDX 3 1333#define mmRCC_DEV0_EPF7_STRAP13 0x403cf8d 1334#define mmRCC_DEV0_EPF7_STRAP13_BASE_IDX 3 1335#define mmRCC_DEV1_EPF0_STRAP0 0x403d000 1336#define mmRCC_DEV1_EPF0_STRAP0_BASE_IDX 3 1337#define mmRCC_DEV1_EPF0_STRAP2 0x403d002 1338#define mmRCC_DEV1_EPF0_STRAP2_BASE_IDX 3 1339#define mmRCC_DEV1_EPF0_STRAP3 0x403d003 1340#define mmRCC_DEV1_EPF0_STRAP3_BASE_IDX 3 1341#define mmRCC_DEV1_EPF0_STRAP4 0x403d004 1342#define mmRCC_DEV1_EPF0_STRAP4_BASE_IDX 3 1343#define mmRCC_DEV1_EPF0_STRAP5 0x403d005 1344#define mmRCC_DEV1_EPF0_STRAP5_BASE_IDX 3 1345#define mmRCC_DEV1_EPF0_STRAP6 0x403d006 1346#define mmRCC_DEV1_EPF0_STRAP6_BASE_IDX 3 1347#define mmRCC_DEV1_EPF0_STRAP13 0x403d00d 1348#define mmRCC_DEV1_EPF0_STRAP13_BASE_IDX 3 1349#define mmRCC_DEV1_EPF1_STRAP0 0x403d080 1350#define mmRCC_DEV1_EPF1_STRAP0_BASE_IDX 3 1351#define mmRCC_DEV1_EPF1_STRAP2 0x403d082 1352#define mmRCC_DEV1_EPF1_STRAP2_BASE_IDX 3 1353#define mmRCC_DEV1_EPF1_STRAP3 0x403d083 1354#define mmRCC_DEV1_EPF1_STRAP3_BASE_IDX 3 1355#define mmRCC_DEV1_EPF1_STRAP4 0x403d084 1356#define mmRCC_DEV1_EPF1_STRAP4_BASE_IDX 3 1357#define mmRCC_DEV1_EPF1_STRAP5 0x403d085 1358#define mmRCC_DEV1_EPF1_STRAP5_BASE_IDX 3 1359#define mmRCC_DEV1_EPF1_STRAP6 0x403d086 1360#define mmRCC_DEV1_EPF1_STRAP6_BASE_IDX 3 1361#define mmRCC_DEV1_EPF1_STRAP13 0x403d08d 1362#define mmRCC_DEV1_EPF1_STRAP13_BASE_IDX 3 1363#define mmRCC_DEV1_EPF2_STRAP0 0x403d100 1364#define mmRCC_DEV1_EPF2_STRAP0_BASE_IDX 3 1365#define mmRCC_DEV1_EPF2_STRAP2 0x403d102 1366#define mmRCC_DEV1_EPF2_STRAP2_BASE_IDX 3 1367#define mmRCC_DEV1_EPF2_STRAP3 0x403d103 1368#define mmRCC_DEV1_EPF2_STRAP3_BASE_IDX 3 1369#define mmRCC_DEV1_EPF2_STRAP4 0x403d104 1370#define mmRCC_DEV1_EPF2_STRAP4_BASE_IDX 3 1371#define mmRCC_DEV1_EPF2_STRAP5 0x403d105 1372#define mmRCC_DEV1_EPF2_STRAP5_BASE_IDX 3 1373#define mmRCC_DEV1_EPF2_STRAP6 0x403d106 1374#define mmRCC_DEV1_EPF2_STRAP6_BASE_IDX 3 1375#define mmRCC_DEV1_EPF2_STRAP13 0x403d10d 1376#define mmRCC_DEV1_EPF2_STRAP13_BASE_IDX 3 1377 1378 1379// addressBlock: bif_rst_bif_rst_regblk 1380// base address: 0x10100000 1381#define ixHARD_RST_CTRL 0x38000 1382#define ixRSMU_SOFT_RST_CTRL 0x38004 1383#define ixSELF_SOFT_RST 0x38008 1384#define ixGFX_DRV_MODE1_RST_CTRL 0x3800c 1385#define ixBIF_RST_MISC_CTRL 0x38010 1386#define ixBIF_RST_MISC_CTRL2 0x38014 1387#define ixBIF_RST_MISC_CTRL3 0x38018 1388#define ixBIF_RST_GFXVF_FLR_IDLE 0x3801c 1389#define ixDEV0_PF0_FLR_RST_CTRL 0x38020 1390#define ixDEV0_PF1_FLR_RST_CTRL 0x38024 1391#define ixDEV0_PF2_FLR_RST_CTRL 0x38028 1392#define ixDEV0_PF3_FLR_RST_CTRL 0x3802c 1393#define ixDEV0_PF4_FLR_RST_CTRL 0x38030 1394#define ixDEV0_PF5_FLR_RST_CTRL 0x38034 1395#define ixDEV0_PF6_FLR_RST_CTRL 0x38038 1396#define ixDEV0_PF7_FLR_RST_CTRL 0x3803c 1397#define ixBIF_INST_RESET_INTR_STS 0x38040 1398#define ixBIF_PF_FLR_INTR_STS 0x38044 1399#define ixBIF_D3HOTD0_INTR_STS 0x38048 1400#define ixBIF_POWER_INTR_STS 0x38050 1401#define ixBIF_PF_DSTATE_INTR_STS 0x38054 1402#define ixBIF_PF0_VF_FLR_INTR_STS 0x38060 1403#define ixBIF_INST_RESET_INTR_MASK 0x38080 1404#define ixBIF_PF_FLR_INTR_MASK 0x38084 1405#define ixBIF_D3HOTD0_INTR_MASK 0x38088 1406#define ixBIF_POWER_INTR_MASK 0x38090 1407#define ixBIF_PF_DSTATE_INTR_MASK 0x38094 1408#define ixBIF_PF0_VF_FLR_INTR_MASK 0x380a0 1409#define ixBIF_PF_FLR_RST 0x38100 1410#define ixBIF_PF0_VF_FLR_RST 0x38120 1411#define ixBIF_DEV0_PF0_DSTATE_VALUE 0x38140 1412#define ixBIF_DEV0_PF1_DSTATE_VALUE 0x38144 1413#define ixBIF_DEV0_PF2_DSTATE_VALUE 0x38148 1414#define ixBIF_DEV0_PF3_DSTATE_VALUE 0x3814c 1415#define ixBIF_DEV0_PF4_DSTATE_VALUE 0x38150 1416#define ixBIF_DEV0_PF5_DSTATE_VALUE 0x38154 1417#define ixBIF_DEV0_PF6_DSTATE_VALUE 0x38158 1418#define ixBIF_DEV0_PF7_DSTATE_VALUE 0x3815c 1419#define ixDEV0_PF0_D3HOTD0_RST_CTRL 0x381e0 1420#define ixDEV0_PF1_D3HOTD0_RST_CTRL 0x381e4 1421#define ixDEV0_PF2_D3HOTD0_RST_CTRL 0x381e8 1422#define ixDEV0_PF3_D3HOTD0_RST_CTRL 0x381ec 1423#define ixDEV0_PF4_D3HOTD0_RST_CTRL 0x381f0 1424#define ixDEV0_PF5_D3HOTD0_RST_CTRL 0x381f4 1425#define ixDEV0_PF6_D3HOTD0_RST_CTRL 0x381f8 1426#define ixDEV0_PF7_D3HOTD0_RST_CTRL 0x381fc 1427#define ixBIF_PORT0_DSTATE_VALUE 0x388c0 1428 1429 1430// addressBlock: bif_misc_bif_misc_regblk 1431// base address: 0x10100000 1432#define ixMISC_SCRATCH 0x3a000 1433#define ixINTR_LINE_POLARITY 0x3a004 1434#define ixINTR_LINE_ENABLE 0x3a008 1435#define ixOUTSTANDING_VC_ALLOC 0x3a00c 1436#define ixBIFC_MISC_CTRL0 0x3a010 1437#define ixBIFC_MISC_CTRL1 0x3a014 1438#define ixBIFC_BME_ERR_LOG 0x3a018 1439#define ixBIFC_RCCBIH_BME_ERR_LOG 0x3a01c 1440#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0x3a020 1441#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0x3a024 1442#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0x3a028 1443#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0x3a02c 1444#define ixNBIF_VWIRE_CTRL 0x3a040 1445#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL 0x3a044 1446#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0 0x3a048 1447#define ixNBIF_SMN_VWR_VCHG_TRIG 0x3a050 1448#define ixNBIF_SMN_VWR_WTRIG_CNTL 0x3a054 1449#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0x3a058 1450#define ixNBIF_MGCG_CTRL 0x3a05c 1451#define ixNBIF_DS_CTRL_LCLK 0x3a060 1452#define ixSMN_MST_CNTL0 0x3a064 1453#define ixSMN_MST_EP_CNTL1 0x3a068 1454#define ixSMN_MST_EP_CNTL2 0x3a06c 1455#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL 0x3a070 1456#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0 0x3a074 1457#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1 0x3a078 1458#define ixNBIF_SDP_VWR_VCHG_TRIG 0x3a07c 1459#define ixBME_DUMMY_CNTL_0 0x3a098 1460#define ixBIFC_THT_CNTL 0x3a09c 1461#define ixBIFC_HSTARB_CNTL 0x3a0a0 1462#define ixBIFC_GSI_CNTL 0x3a0a4 1463#define ixBIFC_PCIEFUNC_CNTL 0x3a0a8 1464#define ixBIFC_SDP_CNTL_0 0x3a0b0 1465#define ixBIFC_PERF_CNTL_0 0x3a0c0 1466#define ixBIFC_PERF_CNTL_1 0x3a0c4 1467#define ixBIFC_PERF_CNT_MMIO_RD 0x3a0c8 1468#define ixBIFC_PERF_CNT_MMIO_WR 0x3a0cc 1469#define ixBIFC_PERF_CNT_DMA_RD 0x3a0d0 1470#define ixBIFC_PERF_CNT_DMA_WR 0x3a0d4 1471#define ixNBIF_REGIF_ERRSET_CTRL 0x3a0d8 1472#define ixSMN_MST_EP_CNTL3 0x3a0f0 1473#define ixSMN_MST_EP_CNTL4 0x3a0f4 1474#define ixBIF_SELFRING_BUFFER_VID 0x3a100 1475#define ixBIF_SELFRING_VECTOR_CNTL 0x3a104 1476 1477 1478// addressBlock: bif_ras_bif_ras_regblk 1479// base address: 0x10100000 1480#define ixBIF_RAS_LEAF0_CTRL 0x39000 1481#define ixBIF_RAS_LEAF1_CTRL 0x39004 1482#define ixBIF_RAS_LEAF2_CTRL 0x39008 1483#define ixBIF_RAS_MISC_CTRL 0x39100 1484#define ixBIF_IOHUB_RAS_IH_CNTL 0x39ff8 1485#define ixBIF_RAS_VWR_FROM_IOHUB 0x39ffc 1486 1487 1488// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC 1489// base address: 0x10134000 1490#define ixRCC_PFC_LTR_CNTL 0x0100 // duplicate 1491#define ixRCC_PFC_PME_RESTORE 0x0104 // duplicate 1492#define ixRCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate 1493#define ixRCC_PFC_STICKY_RESTORE_1 0x010c // duplicate 1494#define ixRCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate 1495#define ixRCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate 1496#define ixRCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate 1497#define ixRCC_PFC_STICKY_RESTORE_5 0x011c // duplicate 1498#define ixRCC_PFC_AUXPWR_CNTL 0x0120 // duplicate 1499 1500 1501// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC 1502// base address: 0x10134200 1503#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 0x0100 // duplicate 1504#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 0x0104 // duplicate 1505#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate 1506#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0x010c // duplicate 1507#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate 1508#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate 1509#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate 1510#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0x011c // duplicate 1511#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0x0120 // duplicate 1512 1513 1514// addressBlock: pciemsix_amdgfx_MSIXTDEC 1515// base address: 0x10170000 1516#define ixPCIEMSIX_VECT0_ADDR_LO 0x0000 1517#define ixPCIEMSIX_VECT0_ADDR_HI 0x0004 1518#define ixPCIEMSIX_VECT0_MSG_DATA 0x0008 1519#define ixPCIEMSIX_VECT0_CONTROL 0x000c 1520#define ixPCIEMSIX_VECT1_ADDR_LO 0x0010 1521#define ixPCIEMSIX_VECT1_ADDR_HI 0x0014 1522#define ixPCIEMSIX_VECT1_MSG_DATA 0x0018 1523#define ixPCIEMSIX_VECT1_CONTROL 0x001c 1524#define ixPCIEMSIX_VECT2_ADDR_LO 0x0020 1525#define ixPCIEMSIX_VECT2_ADDR_HI 0x0024 1526#define ixPCIEMSIX_VECT2_MSG_DATA 0x0028 1527#define ixPCIEMSIX_VECT2_CONTROL 0x002c 1528#define ixPCIEMSIX_VECT3_ADDR_LO 0x0030 1529#define ixPCIEMSIX_VECT3_ADDR_HI 0x0034 1530#define ixPCIEMSIX_VECT3_MSG_DATA 0x0038 1531#define ixPCIEMSIX_VECT3_CONTROL 0x003c 1532#define ixPCIEMSIX_VECT4_ADDR_LO 0x0040 1533#define ixPCIEMSIX_VECT4_ADDR_HI 0x0044 1534#define ixPCIEMSIX_VECT4_MSG_DATA 0x0048 1535#define ixPCIEMSIX_VECT4_CONTROL 0x004c 1536#define ixPCIEMSIX_VECT5_ADDR_LO 0x0050 1537#define ixPCIEMSIX_VECT5_ADDR_HI 0x0054 1538#define ixPCIEMSIX_VECT5_MSG_DATA 0x0058 1539#define ixPCIEMSIX_VECT5_CONTROL 0x005c 1540#define ixPCIEMSIX_VECT6_ADDR_LO 0x0060 1541#define ixPCIEMSIX_VECT6_ADDR_HI 0x0064 1542#define ixPCIEMSIX_VECT6_MSG_DATA 0x0068 1543#define ixPCIEMSIX_VECT6_CONTROL 0x006c 1544#define ixPCIEMSIX_VECT7_ADDR_LO 0x0070 1545#define ixPCIEMSIX_VECT7_ADDR_HI 0x0074 1546#define ixPCIEMSIX_VECT7_MSG_DATA 0x0078 1547#define ixPCIEMSIX_VECT7_CONTROL 0x007c 1548#define ixPCIEMSIX_VECT8_ADDR_LO 0x0080 1549#define ixPCIEMSIX_VECT8_ADDR_HI 0x0084 1550#define ixPCIEMSIX_VECT8_MSG_DATA 0x0088 1551#define ixPCIEMSIX_VECT8_CONTROL 0x008c 1552#define ixPCIEMSIX_VECT9_ADDR_LO 0x0090 1553#define ixPCIEMSIX_VECT9_ADDR_HI 0x0094 1554#define ixPCIEMSIX_VECT9_MSG_DATA 0x0098 1555#define ixPCIEMSIX_VECT9_CONTROL 0x009c 1556#define ixPCIEMSIX_VECT10_ADDR_LO 0x00a0 1557#define ixPCIEMSIX_VECT10_ADDR_HI 0x00a4 1558#define ixPCIEMSIX_VECT10_MSG_DATA 0x00a8 1559#define ixPCIEMSIX_VECT10_CONTROL 0x00ac 1560#define ixPCIEMSIX_VECT11_ADDR_LO 0x00b0 1561#define ixPCIEMSIX_VECT11_ADDR_HI 0x00b4 1562#define ixPCIEMSIX_VECT11_MSG_DATA 0x00b8 1563#define ixPCIEMSIX_VECT11_CONTROL 0x00bc 1564#define ixPCIEMSIX_VECT12_ADDR_LO 0x00c0 1565#define ixPCIEMSIX_VECT12_ADDR_HI 0x00c4 1566#define ixPCIEMSIX_VECT12_MSG_DATA 0x00c8 1567#define ixPCIEMSIX_VECT12_CONTROL 0x00cc 1568#define ixPCIEMSIX_VECT13_ADDR_LO 0x00d0 1569#define ixPCIEMSIX_VECT13_ADDR_HI 0x00d4 1570#define ixPCIEMSIX_VECT13_MSG_DATA 0x00d8 1571#define ixPCIEMSIX_VECT13_CONTROL 0x00dc 1572#define ixPCIEMSIX_VECT14_ADDR_LO 0x00e0 1573#define ixPCIEMSIX_VECT14_ADDR_HI 0x00e4 1574#define ixPCIEMSIX_VECT14_MSG_DATA 0x00e8 1575#define ixPCIEMSIX_VECT14_CONTROL 0x00ec 1576#define ixPCIEMSIX_VECT15_ADDR_LO 0x00f0 1577#define ixPCIEMSIX_VECT15_ADDR_HI 0x00f4 1578#define ixPCIEMSIX_VECT15_MSG_DATA 0x00f8 1579#define ixPCIEMSIX_VECT15_CONTROL 0x00fc 1580#define ixPCIEMSIX_VECT16_ADDR_LO 0x0100 1581#define ixPCIEMSIX_VECT16_ADDR_HI 0x0104 1582#define ixPCIEMSIX_VECT16_MSG_DATA 0x0108 1583#define ixPCIEMSIX_VECT16_CONTROL 0x010c 1584#define ixPCIEMSIX_VECT17_ADDR_LO 0x0110 1585#define ixPCIEMSIX_VECT17_ADDR_HI 0x0114 1586#define ixPCIEMSIX_VECT17_MSG_DATA 0x0118 1587#define ixPCIEMSIX_VECT17_CONTROL 0x011c 1588#define ixPCIEMSIX_VECT18_ADDR_LO 0x0120 1589#define ixPCIEMSIX_VECT18_ADDR_HI 0x0124 1590#define ixPCIEMSIX_VECT18_MSG_DATA 0x0128 1591#define ixPCIEMSIX_VECT18_CONTROL 0x012c 1592#define ixPCIEMSIX_VECT19_ADDR_LO 0x0130 1593#define ixPCIEMSIX_VECT19_ADDR_HI 0x0134 1594#define ixPCIEMSIX_VECT19_MSG_DATA 0x0138 1595#define ixPCIEMSIX_VECT19_CONTROL 0x013c 1596#define ixPCIEMSIX_VECT20_ADDR_LO 0x0140 1597#define ixPCIEMSIX_VECT20_ADDR_HI 0x0144 1598#define ixPCIEMSIX_VECT20_MSG_DATA 0x0148 1599#define ixPCIEMSIX_VECT20_CONTROL 0x014c 1600#define ixPCIEMSIX_VECT21_ADDR_LO 0x0150 1601#define ixPCIEMSIX_VECT21_ADDR_HI 0x0154 1602#define ixPCIEMSIX_VECT21_MSG_DATA 0x0158 1603#define ixPCIEMSIX_VECT21_CONTROL 0x015c 1604#define ixPCIEMSIX_VECT22_ADDR_LO 0x0160 1605#define ixPCIEMSIX_VECT22_ADDR_HI 0x0164 1606#define ixPCIEMSIX_VECT22_MSG_DATA 0x0168 1607#define ixPCIEMSIX_VECT22_CONTROL 0x016c 1608#define ixPCIEMSIX_VECT23_ADDR_LO 0x0170 1609#define ixPCIEMSIX_VECT23_ADDR_HI 0x0174 1610#define ixPCIEMSIX_VECT23_MSG_DATA 0x0178 1611#define ixPCIEMSIX_VECT23_CONTROL 0x017c 1612#define ixPCIEMSIX_VECT24_ADDR_LO 0x0180 1613#define ixPCIEMSIX_VECT24_ADDR_HI 0x0184 1614#define ixPCIEMSIX_VECT24_MSG_DATA 0x0188 1615#define ixPCIEMSIX_VECT24_CONTROL 0x018c 1616#define ixPCIEMSIX_VECT25_ADDR_LO 0x0190 1617#define ixPCIEMSIX_VECT25_ADDR_HI 0x0194 1618#define ixPCIEMSIX_VECT25_MSG_DATA 0x0198 1619#define ixPCIEMSIX_VECT25_CONTROL 0x019c 1620#define ixPCIEMSIX_VECT26_ADDR_LO 0x01a0 1621#define ixPCIEMSIX_VECT26_ADDR_HI 0x01a4 1622#define ixPCIEMSIX_VECT26_MSG_DATA 0x01a8 1623#define ixPCIEMSIX_VECT26_CONTROL 0x01ac 1624#define ixPCIEMSIX_VECT27_ADDR_LO 0x01b0 1625#define ixPCIEMSIX_VECT27_ADDR_HI 0x01b4 1626#define ixPCIEMSIX_VECT27_MSG_DATA 0x01b8 1627#define ixPCIEMSIX_VECT27_CONTROL 0x01bc 1628#define ixPCIEMSIX_VECT28_ADDR_LO 0x01c0 1629#define ixPCIEMSIX_VECT28_ADDR_HI 0x01c4 1630#define ixPCIEMSIX_VECT28_MSG_DATA 0x01c8 1631#define ixPCIEMSIX_VECT28_CONTROL 0x01cc 1632#define ixPCIEMSIX_VECT29_ADDR_LO 0x01d0 1633#define ixPCIEMSIX_VECT29_ADDR_HI 0x01d4 1634#define ixPCIEMSIX_VECT29_MSG_DATA 0x01d8 1635#define ixPCIEMSIX_VECT29_CONTROL 0x01dc 1636#define ixPCIEMSIX_VECT30_ADDR_LO 0x01e0 1637#define ixPCIEMSIX_VECT30_ADDR_HI 0x01e4 1638#define ixPCIEMSIX_VECT30_MSG_DATA 0x01e8 1639#define ixPCIEMSIX_VECT30_CONTROL 0x01ec 1640#define ixPCIEMSIX_VECT31_ADDR_LO 0x01f0 1641#define ixPCIEMSIX_VECT31_ADDR_HI 0x01f4 1642#define ixPCIEMSIX_VECT31_MSG_DATA 0x01f8 1643#define ixPCIEMSIX_VECT31_CONTROL 0x01fc 1644 1645 1646// addressBlock: pciemsix_amdgfx_MSIXPDEC 1647// base address: 0x10171000 1648#define ixPCIEMSIX_PBA 0x0000 1649 1650 1651// addressBlock: syshub_mmreg_ind_syshubind 1652// base address: 0x0 1653#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate 1654#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate 1655#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate 1656#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate 1657#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate 1658#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate 1659#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate 1660#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate 1661#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate 1662#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate 1663#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate 1664#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate 1665#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate 1666#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate 1667#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL 0x10300 // duplicate 1668#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE 0x10308 // duplicate 1669#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER 0x1030c // duplicate 1670#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH 0x10f00 // duplicate 1671#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate 1672#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate 1673#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate 1674#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate 1675#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate 1676#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate 1677#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate 1678#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate 1679#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate 1680#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate 1681#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate 1682#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate 1683#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate 1684#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate 1685#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate 1686#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate 1687 1688#endif 1689