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28#ifndef KGD_KFD_INTERFACE_H_INCLUDED
29#define KGD_KFD_INTERFACE_H_INCLUDED
30
31#include <linux/types.h>
32#include <linux/bitmap.h>
33#include <linux/dma-fence.h>
34
35struct pci_dev;
36
37#define KFD_INTERFACE_VERSION 2
38#define KGD_MAX_QUEUES 128
39
40struct kfd_dev;
41struct kgd_dev;
42
43struct kgd_mem;
44
45enum kfd_preempt_type {
46 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
47 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
48};
49
50struct kfd_cu_info {
51 uint32_t num_shader_engines;
52 uint32_t num_shader_arrays_per_engine;
53 uint32_t num_cu_per_sh;
54 uint32_t cu_active_number;
55 uint32_t cu_ao_mask;
56 uint32_t simd_per_cu;
57 uint32_t max_waves_per_simd;
58 uint32_t wave_front_size;
59 uint32_t max_scratch_slots_per_cu;
60 uint32_t lds_size;
61 uint32_t cu_bitmap[4][4];
62};
63
64
65struct kfd_local_mem_info {
66 uint64_t local_mem_size_private;
67 uint64_t local_mem_size_public;
68 uint32_t vram_width;
69 uint32_t mem_clk_max;
70};
71
72enum kgd_memory_pool {
73 KGD_POOL_SYSTEM_CACHEABLE = 1,
74 KGD_POOL_SYSTEM_WRITECOMBINE = 2,
75 KGD_POOL_FRAMEBUFFER = 3,
76};
77
78enum kgd_engine_type {
79 KGD_ENGINE_PFP = 1,
80 KGD_ENGINE_ME,
81 KGD_ENGINE_CE,
82 KGD_ENGINE_MEC1,
83 KGD_ENGINE_MEC2,
84 KGD_ENGINE_RLC,
85 KGD_ENGINE_SDMA1,
86 KGD_ENGINE_SDMA2,
87 KGD_ENGINE_MAX
88};
89
90struct kgd2kfd_shared_resources {
91
92 unsigned int compute_vmid_bitmap;
93
94
95 uint32_t num_pipe_per_mec;
96
97
98 uint32_t num_queue_per_pipe;
99
100
101 DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
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113
114 unsigned int sdma_doorbell[2][2];
115 unsigned int reserved_doorbell_mask;
116 unsigned int reserved_doorbell_val;
117
118
119 phys_addr_t doorbell_physical_address;
120
121
122 size_t doorbell_aperture_size;
123
124
125 size_t doorbell_start_offset;
126
127
128 uint64_t gpuvm_size;
129
130
131 int drm_render_minor;
132};
133
134struct tile_config {
135 uint32_t *tile_config_ptr;
136 uint32_t *macro_tile_config_ptr;
137 uint32_t num_tile_configs;
138 uint32_t num_macro_tile_configs;
139
140 uint32_t gb_addr_config;
141 uint32_t num_banks;
142 uint32_t num_ranks;
143};
144
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149
150#define ALLOC_MEM_FLAGS_VRAM (1 << 0)
151#define ALLOC_MEM_FLAGS_GTT (1 << 1)
152#define ALLOC_MEM_FLAGS_USERPTR (1 << 2)
153#define ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
154
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158
159#define ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
160#define ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
161#define ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
162#define ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
163#define ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
164#define ALLOC_MEM_FLAGS_COHERENT (1 << 26)
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265
266struct kfd2kgd_calls {
267 int (*init_gtt_mem_allocation)(struct kgd_dev *kgd, size_t size,
268 void **mem_obj, uint64_t *gpu_addr,
269 void **cpu_ptr);
270
271 void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj);
272
273 void (*get_local_mem_info)(struct kgd_dev *kgd,
274 struct kfd_local_mem_info *mem_info);
275 uint64_t (*get_gpu_clock_counter)(struct kgd_dev *kgd);
276
277 uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd);
278
279 int (*alloc_pasid)(unsigned int bits);
280 void (*free_pasid)(unsigned int pasid);
281
282
283 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
284 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
285 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
286
287 int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid,
288 unsigned int vmid);
289
290 int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
291
292 int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
293 uint32_t queue_id, uint32_t __user *wptr,
294 uint32_t wptr_shift, uint32_t wptr_mask,
295 struct mm_struct *mm);
296
297 int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
298 uint32_t __user *wptr, struct mm_struct *mm);
299
300 int (*hqd_dump)(struct kgd_dev *kgd,
301 uint32_t pipe_id, uint32_t queue_id,
302 uint32_t (**dump)[2], uint32_t *n_regs);
303
304 int (*hqd_sdma_dump)(struct kgd_dev *kgd,
305 uint32_t engine_id, uint32_t queue_id,
306 uint32_t (**dump)[2], uint32_t *n_regs);
307
308 bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
309 uint32_t pipe_id, uint32_t queue_id);
310
311 int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type,
312 unsigned int timeout, uint32_t pipe_id,
313 uint32_t queue_id);
314
315 bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd);
316
317 int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
318 unsigned int timeout);
319
320 int (*address_watch_disable)(struct kgd_dev *kgd);
321 int (*address_watch_execute)(struct kgd_dev *kgd,
322 unsigned int watch_point_id,
323 uint32_t cntl_val,
324 uint32_t addr_hi,
325 uint32_t addr_lo);
326 int (*wave_control_execute)(struct kgd_dev *kgd,
327 uint32_t gfx_index_val,
328 uint32_t sq_cmd);
329 uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
330 unsigned int watch_point_id,
331 unsigned int reg_offset);
332 bool (*get_atc_vmid_pasid_mapping_valid)(
333 struct kgd_dev *kgd,
334 uint8_t vmid);
335 uint16_t (*get_atc_vmid_pasid_mapping_pasid)(
336 struct kgd_dev *kgd,
337 uint8_t vmid);
338
339 uint16_t (*get_fw_version)(struct kgd_dev *kgd,
340 enum kgd_engine_type type);
341 void (*set_scratch_backing_va)(struct kgd_dev *kgd,
342 uint64_t va, uint32_t vmid);
343 int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
344
345 void (*get_cu_info)(struct kgd_dev *kgd,
346 struct kfd_cu_info *cu_info);
347 uint64_t (*get_vram_usage)(struct kgd_dev *kgd);
348
349 int (*create_process_vm)(struct kgd_dev *kgd, void **vm,
350 void **process_info, struct dma_fence **ef);
351 int (*acquire_process_vm)(struct kgd_dev *kgd, struct file *filp,
352 void **vm, void **process_info, struct dma_fence **ef);
353 void (*destroy_process_vm)(struct kgd_dev *kgd, void *vm);
354 uint32_t (*get_process_page_dir)(void *vm);
355 void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
356 uint32_t vmid, uint32_t page_table_base);
357 int (*alloc_memory_of_gpu)(struct kgd_dev *kgd, uint64_t va,
358 uint64_t size, void *vm,
359 struct kgd_mem **mem, uint64_t *offset,
360 uint32_t flags);
361 int (*free_memory_of_gpu)(struct kgd_dev *kgd, struct kgd_mem *mem);
362 int (*map_memory_to_gpu)(struct kgd_dev *kgd, struct kgd_mem *mem,
363 void *vm);
364 int (*unmap_memory_to_gpu)(struct kgd_dev *kgd, struct kgd_mem *mem,
365 void *vm);
366 int (*sync_memory)(struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
367 int (*map_gtt_bo_to_kernel)(struct kgd_dev *kgd, struct kgd_mem *mem,
368 void **kptr, uint64_t *size);
369 int (*restore_process_bos)(void *process_info, struct dma_fence **ef);
370
371 int (*invalidate_tlbs)(struct kgd_dev *kgd, uint16_t pasid);
372 int (*invalidate_tlbs_vmid)(struct kgd_dev *kgd, uint16_t vmid);
373
374 int (*submit_ib)(struct kgd_dev *kgd, enum kgd_engine_type engine,
375 uint32_t vmid, uint64_t gpu_addr,
376 uint32_t *ib_cmd, uint32_t ib_len);
377};
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406struct kgd2kfd_calls {
407 void (*exit)(void);
408 struct kfd_dev* (*probe)(struct kgd_dev *kgd, struct pci_dev *pdev,
409 const struct kfd2kgd_calls *f2g);
410 bool (*device_init)(struct kfd_dev *kfd,
411 const struct kgd2kfd_shared_resources *gpu_resources);
412 void (*device_exit)(struct kfd_dev *kfd);
413 void (*interrupt)(struct kfd_dev *kfd, const void *ih_ring_entry);
414 void (*suspend)(struct kfd_dev *kfd);
415 int (*resume)(struct kfd_dev *kfd);
416 int (*quiesce_mm)(struct mm_struct *mm);
417 int (*resume_mm)(struct mm_struct *mm);
418 int (*schedule_evict_and_restore_process)(struct mm_struct *mm,
419 struct dma_fence *fence);
420};
421
422int kgd2kfd_init(unsigned interface_version,
423 const struct kgd2kfd_calls **g2f);
424
425#endif
426