1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#include "pp_debug.h"
24#include <linux/errno.h>
25#include "hwmgr.h"
26#include "hardwaremanager.h"
27#include "power_state.h"
28
29
30#define TEMP_RANGE_MIN (0)
31#define TEMP_RANGE_MAX (80 * 1000)
32
33#define PHM_FUNC_CHECK(hw) \
34 do { \
35 if ((hw) == NULL || (hw)->hwmgr_func == NULL) \
36 return -EINVAL; \
37 } while (0)
38
39int phm_setup_asic(struct pp_hwmgr *hwmgr)
40{
41 PHM_FUNC_CHECK(hwmgr);
42
43 if (NULL != hwmgr->hwmgr_func->asic_setup)
44 return hwmgr->hwmgr_func->asic_setup(hwmgr);
45
46 return 0;
47}
48
49int phm_power_down_asic(struct pp_hwmgr *hwmgr)
50{
51 PHM_FUNC_CHECK(hwmgr);
52
53 if (NULL != hwmgr->hwmgr_func->power_off_asic)
54 return hwmgr->hwmgr_func->power_off_asic(hwmgr);
55
56 return 0;
57}
58
59int phm_set_power_state(struct pp_hwmgr *hwmgr,
60 const struct pp_hw_power_state *pcurrent_state,
61 const struct pp_hw_power_state *pnew_power_state)
62{
63 struct phm_set_power_state_input states;
64
65 PHM_FUNC_CHECK(hwmgr);
66
67 states.pcurrent_state = pcurrent_state;
68 states.pnew_state = pnew_power_state;
69
70 if (NULL != hwmgr->hwmgr_func->power_state_set)
71 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
72
73 return 0;
74}
75
76int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
77{
78 int ret = -EINVAL;;
79 PHM_FUNC_CHECK(hwmgr);
80
81 if (smum_is_dpm_running(hwmgr)) {
82 pr_info("dpm has been enabled\n");
83 return 0;
84 }
85
86 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
87 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
88
89 return ret;
90}
91
92int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
93{
94 int ret = -EINVAL;
95
96 PHM_FUNC_CHECK(hwmgr);
97
98 if (!smum_is_dpm_running(hwmgr)) {
99 pr_info("dpm has been disabled\n");
100 return 0;
101 }
102
103 if (hwmgr->hwmgr_func->dynamic_state_management_disable)
104 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
105
106 return ret;
107}
108
109int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
110{
111 int ret = 0;
112
113 PHM_FUNC_CHECK(hwmgr);
114
115 if (hwmgr->hwmgr_func->force_dpm_level != NULL)
116 ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
117
118 return ret;
119}
120
121int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
122 struct pp_power_state *adjusted_ps,
123 const struct pp_power_state *current_ps)
124{
125 PHM_FUNC_CHECK(hwmgr);
126
127 if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
128 return hwmgr->hwmgr_func->apply_state_adjust_rules(
129 hwmgr,
130 adjusted_ps,
131 current_ps);
132 return 0;
133}
134
135int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr)
136{
137 PHM_FUNC_CHECK(hwmgr);
138
139 if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL)
140 return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr);
141 return 0;
142}
143
144int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
145{
146 PHM_FUNC_CHECK(hwmgr);
147
148 if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
149 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
150 return 0;
151}
152
153int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
154{
155 PHM_FUNC_CHECK(hwmgr);
156
157 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
158 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
159
160 return 0;
161}
162
163int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
164{
165 PHM_FUNC_CHECK(hwmgr);
166
167 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
168 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
169
170 return 0;
171}
172
173int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr)
174{
175 PHM_FUNC_CHECK(hwmgr);
176
177 if (NULL != hwmgr->hwmgr_func->pre_display_config_changed)
178 hwmgr->hwmgr_func->pre_display_config_changed(hwmgr);
179
180 return 0;
181
182}
183
184int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
185{
186 PHM_FUNC_CHECK(hwmgr);
187
188 if (NULL != hwmgr->hwmgr_func->display_config_changed)
189 hwmgr->hwmgr_func->display_config_changed(hwmgr);
190
191 return 0;
192}
193
194int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
195{
196 PHM_FUNC_CHECK(hwmgr);
197
198 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
199 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
200
201 return 0;
202}
203
204int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
205{
206 PHM_FUNC_CHECK(hwmgr);
207
208 if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
209 return -EINVAL;
210
211 return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
212}
213
214int phm_register_irq_handlers(struct pp_hwmgr *hwmgr)
215{
216 PHM_FUNC_CHECK(hwmgr);
217
218 if (hwmgr->hwmgr_func->register_irq_handlers != NULL)
219 return hwmgr->hwmgr_func->register_irq_handlers(hwmgr);
220
221 return 0;
222}
223
224
225
226
227
228
229
230int phm_start_thermal_controller(struct pp_hwmgr *hwmgr)
231{
232 int ret = 0;
233 struct PP_TemperatureRange range = {TEMP_RANGE_MIN, TEMP_RANGE_MAX};
234 struct amdgpu_device *adev = hwmgr->adev;
235
236 if (hwmgr->hwmgr_func->get_thermal_temperature_range)
237 hwmgr->hwmgr_func->get_thermal_temperature_range(
238 hwmgr, &range);
239
240 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_ThermalController)
242 && hwmgr->hwmgr_func->start_thermal_controller != NULL)
243 ret = hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
244
245 adev->pm.dpm.thermal.min_temp = range.min;
246 adev->pm.dpm.thermal.max_temp = range.max;
247
248 return ret;
249}
250
251
252bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
253{
254 PHM_FUNC_CHECK(hwmgr);
255
256 if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
257 return false;
258
259 return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
260}
261
262
263int phm_check_states_equal(struct pp_hwmgr *hwmgr,
264 const struct pp_hw_power_state *pstate1,
265 const struct pp_hw_power_state *pstate2,
266 bool *equal)
267{
268 PHM_FUNC_CHECK(hwmgr);
269
270 if (hwmgr->hwmgr_func->check_states_equal == NULL)
271 return -EINVAL;
272
273 return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
274}
275
276int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
277 const struct amd_pp_display_configuration *display_config)
278{
279 int index = 0;
280 int number_of_active_display = 0;
281
282 PHM_FUNC_CHECK(hwmgr);
283
284 if (display_config == NULL)
285 return -EINVAL;
286
287 if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
288 hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
289
290 for (index = 0; index < display_config->num_path_including_non_display; index++) {
291 if (display_config->displays[index].controller_id != 0)
292 number_of_active_display++;
293 }
294
295 if (NULL != hwmgr->hwmgr_func->set_active_display_count)
296 hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
297
298 if (hwmgr->hwmgr_func->store_cc6_data == NULL)
299 return -EINVAL;
300
301
302
303 if (hwmgr->hwmgr_func->store_cc6_data)
304 hwmgr->hwmgr_func->store_cc6_data(hwmgr,
305 display_config->cpu_pstate_separation_time,
306 display_config->cpu_cc6_disable,
307 display_config->cpu_pstate_disable,
308 display_config->nb_pstate_switch_disable);
309
310 return 0;
311}
312
313int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
314 struct amd_pp_simple_clock_info *info)
315{
316 PHM_FUNC_CHECK(hwmgr);
317
318 if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
319 return -EINVAL;
320 return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
321}
322
323int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
324{
325 PHM_FUNC_CHECK(hwmgr);
326
327 if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
328 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
329
330 return 0;
331}
332
333
334int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
335 PHM_PerformanceLevelDesignation designation, uint32_t index,
336 PHM_PerformanceLevel *level)
337{
338 PHM_FUNC_CHECK(hwmgr);
339 if (hwmgr->hwmgr_func->get_performance_level == NULL)
340 return -EINVAL;
341
342 return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
343
344
345}
346
347
348
349
350
351
352
353
354
355
356int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
357 PHM_PerformanceLevelDesignation designation)
358{
359 int result;
360 PHM_PerformanceLevel performance_level;
361
362 PHM_FUNC_CHECK(hwmgr);
363
364 PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
365 PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
366
367 result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
368
369 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
370
371
372 pclock_info->min_mem_clk = performance_level.memory_clock;
373 pclock_info->min_eng_clk = performance_level.coreClock;
374 pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
375
376
377 result = phm_get_performance_level(hwmgr, state, designation,
378 (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
379
380 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
381
382 pclock_info->max_mem_clk = performance_level.memory_clock;
383 pclock_info->max_eng_clk = performance_level.coreClock;
384 pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
385
386 return 0;
387}
388
389int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
390{
391 PHM_FUNC_CHECK(hwmgr);
392
393 if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
394 return -EINVAL;
395
396 return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
397
398}
399
400int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
401{
402 PHM_FUNC_CHECK(hwmgr);
403
404 if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
405 return -EINVAL;
406
407 return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
408
409}
410
411int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
412 enum amd_pp_clock_type type,
413 struct pp_clock_levels_with_latency *clocks)
414{
415 PHM_FUNC_CHECK(hwmgr);
416
417 if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
418 return -EINVAL;
419
420 return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
421
422}
423
424int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
425 enum amd_pp_clock_type type,
426 struct pp_clock_levels_with_voltage *clocks)
427{
428 PHM_FUNC_CHECK(hwmgr);
429
430 if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
431 return -EINVAL;
432
433 return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
434
435}
436
437int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
438 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
439{
440 PHM_FUNC_CHECK(hwmgr);
441
442 if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
443 return -EINVAL;
444
445 return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
446 wm_with_clock_ranges);
447}
448
449int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
450 struct pp_display_clock_request *clock)
451{
452 PHM_FUNC_CHECK(hwmgr);
453
454 if (!hwmgr->hwmgr_func->display_clock_voltage_request)
455 return -EINVAL;
456
457 return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
458}
459
460int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
461{
462 PHM_FUNC_CHECK(hwmgr);
463
464 if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
465 return -EINVAL;
466
467 return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
468}
469
470int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr)
471{
472 PHM_FUNC_CHECK(hwmgr);
473
474 if (hwmgr->hwmgr_func->disable_smc_firmware_ctf == NULL)
475 return -EINVAL;
476
477 return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr);
478}
479